JP2001015609A - Semiconductor device, manufacture thereof, and liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method therefor wherein variations in the amount of main current can be reduced and the electrical characteristics can hence be improved, by making uniform the LDD lengths (lengths of lightly doped regions) of a plurality of kinds of IGFETs (insulating gate field-effect transistors) on a single substrate, which have different dielectric breakdown values in particular, and further to provide a liquid crystal driver and a method therefor wherein variations in offset voltage can be reduced. SOLUTION: In a liquid crystal driver device (a semiconductor device for a liquid crystal driver), the lengths of LDD regions 52 and 56 of an LDD- structured low dielectric breakdown IGFET are made uniform by self alignment, and the lengths of LDD regions 61 and 65 of an LDD-structured high dielectric breakdown IGFET are made uniform by self alignment, both IGFETs constituting a differential amplifier circuit. The LDD lengths are determined by a side wall spacer mask formed on the sidewalls of gate electrodes 40 to 43. When the LDD lengths are uniform, variations in the amount of main current are reduced, and hence variations in the offset voltage of the differential amplifier circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, a liquid crystal display, and a method for manufacturing a semiconductor device. In particular, the present invention relates to a semiconductor device provided with a plurality of types of insulated gate field effect transistors on the same substrate, a liquid crystal display device provided with the semiconductor device as a liquid crystal driver device, and a method for manufacturing the semiconductor device. More specifically, the present invention provides
A semiconductor device in which a low-breakdown-voltage insulated-gate field-effect transistor and a high-breakdown-voltage insulated-gate field-effect transistor are mixed on the same substrate. The present invention relates to a liquid crystal driver device in which a differential amplifier circuit for driving the liquid crystal is constructed, a liquid crystal display device including the liquid crystal driver device, and a method of manufacturing the liquid crystal driver device.

[0002]

2. Description of the Related Art The present inventor has been developing a liquid crystal driver device (driver semiconductor device) which is incorporated in a liquid crystal display device and drives a video signal line of a liquid crystal display portion.
This liquid crystal driver device includes a differential amplifier circuit for driving the video signal line selected by the decoder circuit. The transistor on the output stage side of the differential amplifier circuit is, for example, a standard low withstand voltage metal-oxide-semiconductor-type insulated-gate field-effect transistor (hereinafter simply referred to as “MO”) having an operating voltage of 3 V to 5 V.
SFET. " ). The differential amplifier transistor and the active load transistor on the input stage side of the differential amplifier circuit are composed of, for example, high-voltage (or medium-voltage) MOSFETs with operating voltages of 11 V to 15 V.

An LDD structure is employed in this type of MOSFET in order to prevent a change in threshold voltage and a short channel effect due to generation of hot carriers due to high integration. The LDD structure is a structure in which a high impurity density region and a low impurity density region between the high impurity density region and the channel region form a drain region of a MOSFET. In other words, in the LDD structure, the generation of hot carriers is reduced by increasing the extension of the empty layer formed at the pn junction between the channel region and the low impurity density region of the drain region to reduce the electric field intensity near the drain region. Can be suppressed. In addition, the LDD structure can reduce the amount of diffusion of the low impurity density region of the drain region toward the channel region, so that the bonding of the empty layer between the source region and the drain region is prevented and the short channel The effect can be prevented.

A manufacturing process of a MOSFET adopting the LDD structure is as follows.

(1) First, a gate oxide film is formed on a substrate, and a gate electrode is formed on the gate oxide film.

(2) Impurities are introduced at a low impurity density into the surface of the substrate by ion implantation using the gate electrode as a mask, thereby forming a low impurity density region. The low-impurity-density region is formed by self-alignment with no misalignment in manufacturing with respect to the gate electrode.

(3) Thereafter, a sidewall spacer mask is formed on the side wall of the gate electrode. The sidewall spacer mask is formed, for example, by depositing a polycrystalline silicon film on the entire surface of the substrate by chemical vapor deposition (CVD), and performing reactive ion etching (RIE) on the entire surface of the polycrystalline silicon film by the formed film thickness. Is formed only on the side wall of the gate electrode. Since the sidewall spacer mask can be formed within the range of the variation in the thickness of the polycrystalline silicon film and the variation in the etching amount, the thickness of the sidewall spacer mask, that is, the length of the sidewall spacer mask (in the direction of the channel length). The film thickness from the side wall surface of the gate electrode in the same direction) is smaller than the amount of misalignment and can be formed with high processing accuracy. In addition, the length of the sidewall spacer mask is substantially determined by the film thickness and the amount of etching, and is formed on the side wall of the gate electrode in a self-alignment manner with the gate electrode.

(4) Impurities are introduced at a high dose (area impurity density) into the surface of the substrate by ion implantation using a sidewall spacer mask to form a high impurity density region. Since the sidewall spacer mask is formed in a self-alignment manner on the side wall of the gate electrode, the high impurity density region is formed in a self-alignment manner with respect to the gate electrode with the sidewall spacer mask interposed therebetween. The distance between the high impurity density region and the channel region, that is, the LDD length, which is the effective length of the low impurity density region between the channel region and the high impurity density region, is determined by the sidewall spacer mask length, the amount of impurity diffusion, Can be determined substantially. By forming a high impurity density region, the source region,
Each of the drain regions is formed, and the MOSFET employing the LDD structure can be completed.

In the liquid crystal driver device under development by the present inventor, a low breakdown voltage MOSFET having an LDD structure and an L
Since a high-voltage MOSFET with a DD structure is mixed, a manufacturing process has been established, and an attempt has been made to adopt a manufacturing process that enables efficient production of a high-voltage MOSFET, centering on a proven low-voltage MOSFET. I have. That is,
The low-voltage MOSFET with the LDD structure is basically manufactured based on the above-described manufacturing process, and at least the step of forming the gate electrode of the low-voltage MOSFET with the LDD structure, the step of forming the sidewall spacer mask, and the high impurity density The process of forming the region is also used for manufacturing a high-breakdown-voltage MOSFET having an LDD structure (formed in the same manufacturing process), and the number of manufacturing processes is reduced.

[0010]

However, in the above-mentioned liquid crystal driver device and its manufacturing process, the following points have not been considered.

(1) Since the required breakdown voltage is different between the low breakdown voltage MOSFET having the LDD structure and the high breakdown voltage MOSFET having the LDD structure, the MOSFET having the higher breakdown voltage is compared with the LDD length of the low breakdown voltage MOSFET which determines the breakdown voltage. It is necessary to lengthen the LDD length that determines the withstand voltage of the device. For this reason, in the manufacturing process, low withstand voltage
In the same manufacturing process as the process of forming the sidewall spacer mask of the MOSFET, a sidewall spacer mask is also formed in the high breakdown voltage MOSFET, but a resist mask longer than the length of the sidewall spacer mask is additionally used. The LDD length is lengthened by forming a high impurity density region by using it. However, LDD
In manufacturing a MOSFET with a high breakdown voltage, the resist mask will be misaligned with respect to the gate electrode.
LDD length, especially LDD length on the source region side, LDD length on the drain region side
The length varies among the lengths.

(2) Variations in the LDD length caused in the fabrication of a high breakdown voltage MOSFET having an LDD structure are caused by the high breakdown voltage of the LDD structure.
This causes a change in the drain current of the MOSFET, thereby changing the current-voltage characteristics of the MOSFET with a high breakdown voltage.

(3) Since the high-voltage MOSFET having the LDD structure forms the differential amplifier transistor on the input stage side of the differential amplifier circuit in the liquid crystal driver device, the offset voltage of the differential amplifier circuit varies. I do. The offset voltage (Vos) is a voltage obtained by subtracting the input voltage (Vin) to the differential amplifier from the output voltage (Vout) of the differential amplifier.

(4) Variations in the offset voltage of the differential amplifier circuit of the liquid crystal driver device result in variations in the driving voltage of the video signal lines in the liquid crystal display device, and "color unevenness" of vertical stripes occurs in the liquid crystal display. As a result, the image quality of the liquid crystal display unit is deteriorated, and the image quality performance of the liquid crystal display device is degraded.

(5) In the liquid crystal driver device, in order to correct the variation of the offset voltage of the differential amplifier circuit,
It is necessary to separately mount an offset voltage correction circuit.
When such an offset voltage correction circuit is mounted, the degree of integration of the liquid crystal driver device is reduced.

(6) When a liquid crystal display device is incorporated in a notebook personal computer, the power consumption of the built-in battery is increased because the power consumption increases in an offset voltage correction circuit separately mounted in the liquid crystal driver device. And the driving time of the personal computer is shortened.

The present invention has been made to solve the above problems. Therefore, a first object of the present invention is to make the LDD lengths (lengths of low impurity density regions) of a plurality of types of insulated gate field effect transistors (hereinafter referred to as “IGFETs”) formed on the same substrate uniform. It is an object of the present invention to provide a semiconductor device which can reduce variations in the amount of main current and improve electric characteristics. Here, “IGFET” is used to mean a transistor including at least a MOSFET and a metal-insulator-semiconductor field-effect transistor (MISFET). In particular, the present invention provides a liquid crystal driver device (or a semiconductor device) that can reduce variations in offset voltage of a differential amplifier circuit, prevent poor image quality of a liquid crystal display unit, and improve the performance of a liquid crystal display device. The purpose is to: Furthermore, there is no need to mount an offset voltage correction circuit,
It is an object to provide a liquid crystal driver device (or a semiconductor device) capable of improving the degree of integration.

A fourth object of the present invention is to provide a liquid crystal display device capable of reducing the variation in the offset voltage of the differential amplifier circuit and improving the image quality of the liquid crystal display.

A third object of the present invention is to realize a high-performance liquid crystal display device having a liquid crystal driver device that does not need to mount an offset voltage correction circuit, and to reduce power consumption in the liquid crystal driver device. To provide a personal computer capable of extending the driving time.

A fourth object of the present invention is to eliminate variations in LDD length (length of a low impurity density region) due to misalignment in manufacturing in each of a plurality of types of IGFETs mounted on the same substrate. Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of making the LDD length uniform.

A fifth object of the present invention is to achieve optimization of each of a low breakdown voltage IGFET having an LDD structure and a high breakdown voltage IGFET having an LDD structure while achieving the sixth object of the present invention. A method of manufacturing a semiconductor device is provided. In particular, a seventh object of the present invention is to provide a method of manufacturing a semiconductor device which does not adversely affect the characteristics of a low breakdown voltage IGFET having an LDD structure when manufacturing a high breakdown voltage IGFET having an LDD structure.

A sixth object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the number of manufacturing steps while achieving the sixth object of the present invention. In particular, a sixth object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the number of manufacturing steps by reducing the number of steps of removing a sidewall spacer mask.

A seventh object of the present invention is to reduce the number of masks for forming an impurity density region and to reduce the number of manufacturing steps, while achieving the fourth object of the present invention. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

An eighth object of the present invention is to achieve a semiconductor which can shorten the film forming time of the sidewall spacer mask forming layer and reduce the manufacturing time while achieving the fourth object of the present invention. It is to provide a method of manufacturing the device.

[0025]

In order to solve the above problems, a first feature of the present invention is to provide a semiconductor device having a first feature.
A first high impurity density region formed in self-alignment with a first gate electrode on the first channel region in the vicinity of the first channel region; and at least the first channel region and the first channel region.
Formed by a low breakdown voltage IGFET including a first main electrode region having a first low impurity density region formed in self-alignment with a first gate electrode between the high impurity density region A transistor on the stage side and a second transistor formed in self-alignment with a second gate electrode on the second channel region near a second channel region formed on the same substrate as the transistor on the output stage side. 2 high impurity density regions, and at least between the second channel region and the second high impurity density regions are formed in self-alignment with the second gate electrode;
An input-stage-side differential amplification transistor formed of a high-breakdown-voltage IGFET including a second main electrode region having a second low-impurity-density region longer in the channel length direction than the first low-impurity-density region; That is, a differential amplifier circuit having a load transistor is provided.

Here, the "high impurity density region formed by self-alignment with the gate electrode" means that the gate electrode is formed without requiring alignment in manufacturing (without misalignment in manufacturing) with respect to the gate electrode. Used in the sense of a high impurity density region. Similarly, “a low impurity density region formed between a channel region and a high impurity density region in a self-alignment manner with respect to a gate electrode” refers to a channel region which does not require manufacturing alignment with the gate electrode. Is used to mean a low impurity density region formed between the high impurity density region and the high impurity density region. The “main electrode region having a high impurity density region and a low impurity density region” is used to mean a drain region or a source region having a high impurity density region and a low impurity density region. “The low impurity density region formed at least between the channel region and the high impurity density region” means that at least the low impurity density region only needs to be formed at least between the channel region and the high impurity density region. This is used in a sense, and a low impurity density region may be formed below the bottom surface of the high impurity density region in addition to between the channel region and the high impurity density region. The “low impurity density region” is used to mean a semiconductor region (diffusion region) formed with an impurity density lower than that of a high impurity density region for forming an LDD structure. "The second low impurity density region longer in the channel length direction than the first low impurity density region" refers to the first low impurity density region length of the low breakdown voltage IGFET, that is, the second low impurity density region of the high breakdown voltage IGFET that is longer than the LDD length. 2, which means that the length of the low impurity density region, that is, the LDD length is long.

In the semiconductor device according to the first aspect of the present invention, the low breakdown voltage IGFET and the high breakdown voltage IGFET are both LDD.
It is preferred that the structure is constituted.

In the semiconductor device according to the first aspect of the present invention, the first low impurity density region and the first high impurity density region of the low breakdown voltage IGFET are both the first gate. Since the electrodes are formed in a self-aligned manner with respect to the electrodes, the length (LDD length) of the first low impurity density region can be made uniform. Similarly, since both the second low impurity density region and the second high impurity density region of the high breakdown voltage IGFET are formed in self-alignment with the second gate electrode, the second low impurity density region Length (LDD length) can be made uniform. Therefore, the variation in the amount of main current of the IGFET for low withstand voltage and the variation in the amount of main current of the IGFET for high withstand voltage can both be reduced, and the electrical characteristics of the semiconductor device can be improved.

In the first aspect of the present invention, the "differential amplifier circuit" is preferably a negative feedback type differential amplifier circuit. The gate electrode of the "differential amplifier transistor" of the differential amplifier circuit is an input signal terminal (for example, a decode signal input terminal).
, And a second differential amplifier transistor having a gate electrode connected to an output signal terminal (for example, a video signal terminal). The “active load transistor” includes a first active load transistor connected in series to a drain region of the first differential amplifier transistor, and a second active load transistor connected in series to a drain region of the second differential amplifier transistor. It is preferable to include an active load transistor as a set. The "output stage transistor"
Preferably, the gate electrode is connected to the drain region of the second differential amplifier transistor and the drain region of the second active load transistor, the source region is connected to a reference power supply potential, and the drain region is connected to an output signal terminal.

In the semiconductor device according to the first aspect of the present invention, the IGFET for low withstand voltage and the IGFET for high withstand voltage both reduce the variation in the amount of main current and improve the electrical characteristics. In particular, the variation of the main current amount of the differential amplification transistor (the variation of the drain current of the first differential amplification transistor) can be reduced,
Variations in the offset voltage of the differential amplifier circuit can be reduced.

According to a second feature of the present invention, in the semiconductor device according to the first feature of the present invention, the differential amplifier circuit constructs a driver circuit unit for driving a video signal line of a liquid crystal display section of a liquid crystal display device. That is. The “semiconductor device” according to the second feature of the present invention is used to mean a liquid crystal driver device (a semiconductor device for a liquid crystal driver or a semiconductor chip for a liquid crystal driver). The “driver circuit unit” includes at least a differential amplifier circuit, a decoder circuit,
It is preferable to include a register circuit and a data control circuit.

In the semiconductor device (liquid crystal driver device) according to the second feature of the present invention, which is configured as described above,
Differential amplification transistor (IGFE for high withstand voltage)
T) Variations in the amount of main current can be reduced to reduce variations in the offset voltage of the differential amplifier circuit. Therefore, it is possible to prevent poor image quality of the liquid crystal display of the liquid crystal display device, Performance can be improved. Further, in the (liquid crystal driver device) according to the second aspect of the present invention, it is possible to reduce the variation in the offset voltage of the differential amplifier circuit, so that it is not necessary to separately mount an offset voltage correction circuit, and the integration degree is improved. Can be improved.

A third feature of the present invention is that, in a liquid crystal display device, a first high voltage formed near a first channel region and self-aligned with a first gate electrode on the first channel region. A first main region having an impurity density region and a first low impurity density region formed at least between the first channel region and the first high impurity density region in a self-aligned manner with respect to the first gate electrode; An output stage transistor having an electrode region, a second high impurity density region formed in the vicinity of the second channel region in a self-aligned manner with respect to a second gate electrode on the second channel region, and at least A second low-impurity region formed between the second channel region and the second high-impurity-density region in a self-aligned manner with respect to the second gate electrode, and longer in the channel length direction than the first low-impurity-density region. Second with a density region A differential amplifier circuit having an input stage differential amplifier transistor and an active load transistor having an electrode region, a liquid crystal driver device including a driver circuit unit having the differential amplifier circuit, and a driver circuit of the liquid crystal driver device And a liquid crystal display having a video signal line driven by the unit.

In the liquid crystal display device according to the third aspect of the present invention, the main current of the differential amplifier transistor of the differential amplifier circuit of the liquid crystal driver device (semiconductor device for liquid crystal driver) is varied. , The variation in the offset voltage of the differential amplifier circuit can be reduced, so that the image quality of the liquid crystal display unit can be prevented from being poor, and the display performance can be improved. further,
In the liquid crystal display device according to the third aspect of the present invention, by reducing the variation of the offset voltage of the differential amplifier circuit of the liquid crystal driver device, it is not necessary to mount a separate offset voltage correction circuit, thereby reducing power consumption. Can be reduced. In particular, when the liquid crystal display device according to the third feature of the present invention is incorporated in a notebook personal computer driven by a built-in battery, the power consumption of the built-in battery of the notebook personal computer can be reduced. , Driving for a long time can be realized.

A fourth feature of the present invention is that in the method of manufacturing a semiconductor device, (1) a first channel region is formed in a first region of a substrate, and a second channel region is formed in a second region different from the first region of the substrate. Forming a second channel region in the region; (2) forming a first channel region;
Forming a first gate electrode on the channel region through a first gate insulating film, and forming a second gate electrode on the second channel region through a second gate insulating film; (3) a first low impurity density region formed in self-alignment with the first gate electrode in contact with the first channel region in the first region;
A first sidewall spacer mask formed in a self-alignment manner with respect to the first gate electrode, and a self-alignment with the first sidewall spacer mask with a first low impurity density region interposed in the first channel region The first formed by
Forming a first impurity-doped IGFET having a high impurity density region, and a second low impurity density formed in self-alignment with a second gate electrode in contact with a second channel region in a second region. Region on the side wall of the second gate electrode.
A second sidewall spacer mask that is formed in a self-aligned manner with respect to the gate electrode and is longer than the length of the first sidewall spacer mask;
Forming a second IGFET having a second high impurity density region formed in self-alignment with the second sidewall spacer mask with the low impurity density region interposed therebetween. .

Here, "forming the first IGFET" in the step (3) means that each of the first low impurity density region, the first sidewall spacer mask, and the first high impurity density region is a result. The first high impurity density region must be formed after the first sidewall spacer mask, while the first low impurity density region is formed by the first IGFET. May be formed either before the formation of the sidewall spacer mask or after the formation of the first high impurity density region. Similarly, "second
Forming an IGFET of the second low impurity density region,
A second IGFET, each of which has a second sidewall spacer mask and a second high impurity density region
The second high impurity density region needs to be formed after the second sidewall spacer mask, while the second low impurity density region forms the second sidewall spacer mask. Before or after forming the second high impurity density region. In addition, the "formation of the first IGFET and the second IGFET
"Forming a second IGFET after forming a first IGFET"
When forming the GFET, the first after forming the second IGFET
Is used as an expression including any case of forming an IGFET.

In the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, the first sidewall spacer mask and the first high impurity density region of the first IGFET are each formed by the first gate electrode. Therefore, the length of the first low impurity density region of the first IGFET, that is, the LDD length, can be formed with a uniform LDD length without misalignment in manufacturing. Similarly, the second IGFET
Since the second sidewall spacer mask and the second high impurity density region are formed by self-alignment,
The length of the second low impurity density region, that is, the LDD length of the IGFET can be formed with a uniform LDD length without misalignment in manufacturing.

A fifth feature of the present invention is that, in the method of manufacturing a semiconductor device, (1) a first channel region is formed in a first region of a substrate, and a second channel region different from the first region of the substrate is formed. Forming a second channel region in the region;
Forming a first gate electrode on the second channel region via a first gate insulating film, and forming a second gate electrode on the second channel region via a second gate insulating film; (3) A first low impurity density region is formed in self-alignment with the first gate electrode in contact with the first channel region in the first region, and in contact with the second channel region in the second region. Forming a second low impurity density region by self-alignment with the second gate electrode, and (4) forming a first self-alignment with the first gate electrode on a side wall of the first gate electrode. Forming a sidewall spacer mask; and (5) using the first sidewall spacer mask in the first region and self-aligning the first sidewall spacer mask with the first channel region in the first channel region. 1
Forming a first high-impurity-density region with the low-impurity-density region interposed therebetween to form a first IGFET; and (6) removing the first sidewall spacer mask.
(7) forming a second sidewall spacer mask longer in the channel length direction than the first sidewall spacer mask on the side wall of the second gate electrode in self-alignment with the second gate electrode; 8) using a second sidewall spacer mask in the second region, and self-aligning the second sidewall spacer mask with the second sidewall spacer mask;
Forming a second high-impurity-density region with a second low-impurity-density region interposed in the channel region and forming a second IGFET.

In the method for manufacturing a semiconductor device according to the fifth aspect of the present invention, in addition to the effects obtained by the method for manufacturing a semiconductor device according to the fourth aspect of the present invention,
Since the first IGFET is formed earlier than the second IGFET, the optimum first IGFET can be formed without being affected by the formation of the second IGFET. For example, the first I
Since the processing damage of the second IGFET is not added to the ion implantation buffer oxide film formed on the main electrode region of the GFET, the first low impurity density region and Substrate (silicon substrate) by ion implantation of impurities for forming first high impurity density region
It can be introduced into the surface portion, and the occurrence of damage due to ion implantation into the substrate surface portion can be prevented. Furthermore, since the peak of the density of the ion-implanted impurity can be set on the substrate surface side, the first main electrode region can be formed shallow (shallowed), and the first IGFET can be formed.
Fine processing can be realized. As a result, the degree of integration of the semiconductor device can be improved, and the first IGFE
The switching operation speed can be increased by reducing the parasitic capacitance added to the first main electrode region of T.

A sixth feature of the present invention is that, in the method of manufacturing a semiconductor device, (1) a first channel region is formed in a first region of a substrate, and a second channel region is formed in the first region of the substrate. Forming a second channel region in the region; (2) forming a first channel region;
Forming a first gate electrode on the second channel region via a first gate insulating film, and forming a second gate electrode on the second channel region via a second gate insulating film; (3) A first low impurity density region is formed in self-alignment with the first gate electrode in contact with the first channel region in the first region, and in contact with the second channel region in the second region. Forming a second low impurity density region by self-alignment with the second gate electrode, and (4) forming a first self-alignment with the first gate electrode on a side wall of the first gate electrode. Forming a side wall spacer mask and forming a first side wall spacer mask on the side wall of the second gate electrode in the same manufacturing process in a self-aligned manner with respect to the second gate electrode; In the area, the first
The first sidewall spacer mask is used and the first low impurity density region is interposed in the first channel region in self-alignment with the first sidewall spacer mask.
Forming a first IGFET by forming a high impurity density region of (1) and (6) manufacturing the same first sidewall spacer mask for each of the side walls of the first gate electrode and the side wall of the second gate electrode. And (7) a second sidewall spacer mask that is self-aligned with the second gate electrode on the side wall of the second gate electrode and is longer in the channel length direction than the first sidewall spacer mask. Forming a second sidewall spacer mask on the side wall of the first gate electrode by self-alignment with the first gate electrode in the same manufacturing process; and (8) forming a second sidewall spacer mask in the second region. The second high impurity concentration is formed in the second channel region by self-alignment with the second sidewall spacer mask with the second low impurity density region interposed therebetween. Forming a degree region, forming a second IGFET, (9) the side walls of the second gate electrode, the first
And removing the second side wall spacer mask on each side wall of the gate electrode by the same manufacturing process.

In the method for manufacturing a semiconductor device according to the sixth aspect of the present invention, in addition to the effects obtained by the method for manufacturing a semiconductor device according to the fifth aspect of the present invention,
Forming a first sidewall spacer mask on a side wall of the first gate electrode and a side wall of the second gate electrode of the second IGFET when forming the first high impurity density region of the first IGFET; After forming the first high impurity density region,
By removing the first sidewall spacer mask in the first region and the second region in the same manufacturing process, it is possible to selectively remove the first sidewall spacer mask only in the first region newly. The first sidewall spacer mask can be removed by etching the entire surface of the substrate without requiring a mask step. Similarly, when forming the second high impurity density region of the second IGFET, a second sidewall spacer mask is formed on the side wall of the second gate electrode and the side wall of the first gate electrode of the first IGFET. After forming the second high-impurity-density region, the second sidewall spacer mask is removed in the second region and the first region, so that the second region is newly formed only in the second region. The second sidewall spacer mask can be removed by etching the entire surface of the substrate without requiring a mask step for selectively removing the sidewall spacer mask. Therefore, the first
Since a new mask step for selectively removing each of the side wall spacer mask and the second side wall spacer mask is not required, the number of manufacturing steps of the semiconductor device can be reduced.

According to a seventh feature of the present invention, in a method of manufacturing a semiconductor device, (1) a first channel region is formed in a first region of a substrate, and a second channel region different from the first region of the substrate is formed. Forming a second channel region in the region; (2) forming a first channel region;
Forming a first gate electrode on the second channel region via a first gate insulating film, and forming a second gate electrode on the second channel region via a second gate insulating film; (3) a step of forming a sidewall spacer mask on the side wall of the first gate electrode and the side wall of the second gate electrode by the same manufacturing process; and (4) a step of opening the first region and opening the second
Forming a first mask that covers the area of
(5) A first mask and a sidewall spacer mask are used in the first region, and a first high impurity of the first conductivity type is self-aligned with the sidewall spacer mask near the first channel region. Forming a high density region, removing the sidewall spacer mask on the side wall of the first gate electrode by using the first mask, and then forming at least the first channel region and the first high impurity density region; Forming a first low-impurity-density region of the first conductivity type in self-alignment with the first gate electrode to form a first IGFET, and (6) removing the first mask Forming a second mask in which the second region is opened and the first region is covered; and (7) forming a second mask using the second mask and the sidewall spacer mask in the second region. The size near the channel region A second high-impurity-density region of a second conductivity type opposite to the first conductivity type is formed in self-alignment with the wall spacer mask, and then the second mask is used to form a second high impurity density region. The side wall spacer mask on the side wall of the gate electrode is removed, and thereafter, between the second channel region and the second high impurity density region, the second gate electrode is self-aligned with the second conductivity type. Forming a second low impurity density region and forming a second IGFET.

Here, "the first conductive type first low impurity density region and the first high impurity density region formed with the first
“IGFET” is used to mean, for example, an n-channel conductive IGFET. "The second IGFE in which the second low impurity density region and the second high impurity density region of the second conductivity type are formed.
"T" is used to mean, for example, a p-channel conductivity type IGFET.

In the method for manufacturing a semiconductor device according to the seventh aspect of the present invention, the first high impurity density region of the first IGFET and the first Each of the low impurity density regions can be formed, and the sidewall spacer mask on the side wall of the first gate electrode can be removed. Further, by using one second mask,
Since each of the second high impurity density region and the second low impurity density region of the second IGFET can be formed and the sidewall spacer mask on the side wall of the second gate electrode can be removed, The number of manufacturing steps can be reduced.

According to an eighth feature of the present invention, in the method of manufacturing a semiconductor device, (1) a first channel region is formed in a first region of a substrate, and a second channel region is formed in a second region different from the first region of the substrate. Forming a second channel region in the region;
Forming a first gate electrode on the second channel region via a first gate insulating film, and forming a second gate electrode on the second channel region via a second gate insulating film; (3) A first low impurity density region is formed in self-alignment with the first gate electrode in contact with the first channel region in the first region, and in contact with the second channel region in the second region. Forming a second low-impurity-density region by self-alignment with the second gate electrode, and (4) forming a first sidewall spacer mask formation layer on the first region and the second region. The first region is formed in a state where the second region is covered with the first sidewall spacer mask forming layer.
Forming a first sidewall spacer mask on the side wall of the first gate electrode in a self-aligned manner with respect to the first gate electrode from the first sidewall spacer mask forming layer on the region of (5); In the first region, the first sidewall spacer mask is used, and the first low impurity density region is interposed in the first channel region in self alignment with the first sidewall spacer mask. Forming a high impurity density region and forming a first IGFET; and (6) forming a second sidewall spacer mask on the first sidewall spacer mask forming layer and the first region in the second region. Forming a formation layer and forming a first layer on the second region;
And from the second sidewall spacer mask forming layer,
Forming a second sidewall spacer mask on the side wall of the second gate electrode in self-alignment with the second gate electrode; and (7) using the second sidewall spacer mask in the second region Then, a second high impurity density region is formed by interposing a second low impurity density region in the second channel region in a self-alignment with the second sidewall spacer mask to form a second IGFET. And at least steps.

Here, the “first side wall spacer mask formed on the side wall of the first gate electrode” is the first side wall spacer mask.
May be removed before the formation of the second sidewall spacer mask forming layer after the formation of the high impurity density region, or may be left as it is.

In the method of manufacturing a semiconductor device according to the eighth aspect of the present invention, the first sidewall spacer mask forming layer for forming the first high impurity density region of the first IGFET is formed. A first sidewall left on the second region and a second sidewall spacer mask for forming a second high impurity density region of the second IGFET left on the second region Since the second sidewall spacer mask formation layer and the second sidewall spacer mask formation layer for stacking can be formed, the thickness of the second sidewall spacer mask formation layer can be reduced, The manufacturing time of the semiconductor device can be reduced by an amount corresponding to the decrease in the film thickness.

[0048]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) The following embodiments of the present invention will be described with reference to the drawings.

<System Structure of Liquid Crystal Driver Device and Liquid Crystal Display Device> FIG. 2A shows a liquid crystal driver device (a semiconductor device for a liquid crystal driver or a liquid crystal driver) incorporated in the liquid crystal display device according to the first embodiment of the present invention. FIG. 4 is a plan layout diagram of a semiconductor chip for use in the present invention. As shown in FIG. 2A, the planar shape of the liquid crystal driver device 1 is formed in a rectangular shape that is long in the horizontal direction. In the first embodiment of the present invention, the long side of the liquid crystal driver device 1 (FIG. 2)
(A), the upper and lower sides have a dimension of 17.42 mm, and the short side (the right and left sides in FIG. 2 (A)) has a dimension of 3.19.
mm. An output pad in which a plurality of output pads (external output terminals or bonding pads) for connecting to the video signal line 22 (see FIG. 3) of the liquid crystal display unit 2 is arranged in a peripheral region along the upper side of the liquid crystal driver device 1. An area 10 (Vout) is provided. The liquid crystal driver 1 has an input pad area 11 in which a plurality of input pads (external input terminals or bonding pads) for inputting a decode signal for selecting a video signal line 22, a circuit control signal, a power supply and the like are arranged. Are arranged.

A main decoder circuit 12 is disposed substantially at the center of the central area of the liquid crystal driver device 1. In the central region of the liquid crystal driver device 1, the main decoder circuit 12 is centered, and the right side in FIG.
The driver circuit unit array 13 is provided on each left side.
Are arranged.

FIG. 2B is a block circuit diagram of the driver circuit unit 130 according to the first embodiment of the present invention. FIG. 2 shows the driver circuit unit array 13.
A plurality of driver circuit units 130 shown in (B) are regularly arranged in the horizontal direction in the figure. In the liquid crystal driver device 1 according to the first embodiment of the present invention, 192 driver circuit units 130 are arranged in the driver circuit unit array 13 on the right side of the main decoder circuit 12, and the driver on the left side of the main decoder circuit 12 is arranged. Similarly, in the circuit unit array 13, 192 driver circuit units 130 are arranged, and a total of 384 driver circuit units 130 are arranged. That is, the liquid crystal driver device 1 according to the first embodiment of the present invention has 384 outputs capable of driving 384 video signal lines 22. Note that the liquid crystal driver device 1 according to the first embodiment of the present invention is not limited to this number of gradations, but can display 256 gradations.

Each driver circuit unit 130
Denotes a negative feedback type differential amplifier circuit (op-amp) 131, a decoder circuit (sub-decoder circuit) 132, and a register circuit 1
33 and a data control circuit 134, and these circuits 131 to 134 are connected in series. The output stage side of the differential amplifier circuit 131 is the driver circuit unit 13
It is electrically connected to the output pad 101 (Vout) provided every 0.

FIG. 3 is a circuit diagram of the differential amplifier circuit 131 of the liquid crystal driver device 1 and the liquid crystal display section 2 of the liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 3, the differential amplifier circuit 131 is a p-channel IGFET for bias.
Q _PL1 and Q _PL2 , an output n-channel IGFET Q _NL1 used as an output stage transistor, and a set of differential input p-channel IGFs used as a differential amplification transistor on the input stage side
ETQ _PH1 , Q _PH2 , one set of n-channel I for active load
GFET Q _NH1 , Q _NH2 , and capacitive element C are provided.

[0054] p-channel bias IGFETQ _PL1, Q _PL2,
Each of the output n-channel IGFETQ _NL1 is formed as a low-voltage transistor in a range of, for example, the operating voltage 3V to 5V. Each of the p-channel IGFETs Q _PH1 and Q _PH2 for differential input and the n-channel IGFETs Q _NH1 and Q _NH2 for active load is formed as, for example, a high withstand voltage transistor (or a medium withstand voltage transistor) within the operating voltage range of 11V to 15V.

The source regions (main current regions) of the bias p-channel IGFETs Q _PL1 and Q _PL2 are connected to an amplifier power supply voltage terminal AV _DD , and their gate electrodes are connected to a bias circuit (not shown ₎ through a bias terminal _Vb. It is connected.

Each source region of the differential input p-channel IGFETs Q _PH1 and Q _PH2 is a bias p-channel IGFET Q _PH1 .
It is connected to the drain region (main electrode region) of _PL1 .
The gate electrode of the p-channel IGFET Q _PH1 for differential input is connected to the signal input terminal Vin, and a drive signal from the decoder circuit 132 is input to the signal input terminal Vin. The gate electrode of the p-channel IGFET Q _PH2 for differential input is connected to the drain region of the p-channel IGFET Q _PL2 for bias, the drain region of the n-channel IGFET Q _NL1 for output, and to the output pad 101 (Vout). The drain region of the p-channel IGFET Q _PH1 for differential input is connected to the drain region and the gate electrode of the n-channel IGFET Q _NH1 for active load, and the gate electrode of the n-channel IGFET Q _NH2 for active load. The drain region of the differential input p-channel IGFET Q _{PH2 is connected to} the drain region of the active load n-channel IGFET Q _NH2 and the gate electrode of the output n-channel IGFET Q _NL1 . Capacitor C is a p-channel IGFET Q for differential input
It is inserted between the gate electrode and the drain region of _PH2 .

N-Channel IGFET for Active Load
The source regions of Q _NH1 and Q _NH2 are reference voltage terminals A
Connected to V _SS . A source region of the output n-channel IGFETQ _NL1 is connected to the reference voltage terminal AV _SS as well.

The liquid crystal display section 2 of the liquid crystal display device shown in FIG.
A plurality of video signal lines 2 extending in the horizontal direction and arranged in the vertical direction
2 and a plurality of vertical scanning lines 21 extending in the vertical direction and arranged in a plurality of horizontal directions. It is arranged in a way. One pixel 20 includes a thin film transistor (TFT) Q _TFT and a liquid crystal LCD disposed between a pixel electrode and a common electrode. The gate electrode of the thin film transistor Q _TFT is connected to a vertical scanning line 21, the drain region is connected to the video signal line 22, the source region is connected to the pixel electrode. The common electrode is connected to a common power supply terminal _VCOM . The thin film transistor Q _TFT has, for example, a source region in a polycrystalline silicon film or an amorphous silicon film formed on a transparent glass substrate,
A channel region and a drain region are formed, and a gate electrode is formed in the channel region with a gate insulating film interposed therebetween.

A plurality of liquid crystal driver devices 1 are arranged along the liquid crystal display unit 2 in accordance with the number of video signal lines 22 arranged on the liquid crystal display unit 2.

<Cross-Sectional Structure of Liquid Crystal Driver Device> FIG. 1 shows a liquid crystal driver device 1 according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional structural view of a main part of FIG. As shown in FIG. 1, the liquid crystal driver device 1 is configured using a p ⁻ type semiconductor substrate 30 made of single crystal silicon having a low impurity density as a base material. The output n of the differential amplifier circuit 131 shown in FIG.
Low-voltage n-channel IGFETQ _NL such channel IGFETQ _NL1 is the left end in FIG. 1, the bias for the p-channel IGFETQ _PL1, Q _PL2
The low-breakdown-voltage p-channel IGFET Q _PL is shown on the left side of the center in FIG. For differential input of differential amplifier circuit 131
High withstand voltage (or medium withstand voltage) of p-channel IGFET Q _PH1 , Q _PH2 etc.
p-channel IGFETQ _PH at the right end in FIG. 1, the high-voltage n-channel I of n such channels IGFETQ _NH1, Q _NH2 for active load
GFETQ _NH is shown on the right side of the center in FIG.
That is, in the liquid crystal driver device 1, the low breakdown voltage IGFE
T is the low-voltage n-channel IGFETQ _NL and a low-voltage p-channel IGFET
Consists of a complementary structure with and Q _PL, the high-voltage IGFET similarly high breakdown voltage p-channel IGFETQ _PH and high breakdown voltage n-channel IGF
It has a complementary structure with ETQ _NH .

The low-breakdown-voltage n-channel IGFET Q _NL is provided in a region surrounded by the element isolation region 31 on the main surface of the p ^- type well region 303 having a low impurity density.
Well region 303 is formed on the main surface of semiconductor substrate 30. In the liquid crystal driver device 1 according to the first embodiment of the present invention, a field silicon oxide film formed by selectively oxidizing the surface of the semiconductor substrate 30 is used for the element isolation region 31. A p-type channel stopper region 33 having a higher impurity density than the well region 303 is formed in a region along the bottom surface of the element isolation region 31 on the surface of the well region 303. Low withstand voltage n-channel IGFET Q
_NL is a channel region formed by the well region 303;
A gate insulating film 35 on the channel region, a gate electrode 40 on the gate insulating film 35, and a source region and a drain region having an LDD structure are constructed.

The gate insulating film 35 includes a silicon oxide film,
Single-layer films such as oxynitride films, silicon oxide films,
Any of oxynitride film, silicon nitride film, etc. 2
A composite film obtained by laminating more than two types of films can be used practically. The gate electrode 40 is formed of a polycrystalline silicon film and a polycide film made of a tungsten silicide film laminated on the surface thereof in the liquid crystal driver device 1 according to the first embodiment of the present invention. The gate electrode 40 may be made of a polycrystalline silicon film, a high melting metal silicide film such as a tungsten silicide film or a titanium silicide film, a single layer film of a high melting metal film such as a tungsten film or a titanium film, or a polycrystalline silicon film. A composite film in which a high-melting-point metal silicide film or a high-melting-point metal film is laminated on the film can be practically used.

Source region, drain region (main current region)
Are each formed of an n-type low impurity density region (semiconductor region or diffusion region) 52 and an n ⁺ -type high impurity density region (semiconductor region or diffusion region) 53 which are LDD portions. The low impurity density region 52 is formed in contact with the channel region, and is formed at least between the channel region and the high impurity density region 53 formed near the channel region. The low impurity density region 52 is formed in a self-aligned manner with respect to the gate electrode 40, that is, without alignment in manufacturing (without alignment deviation). The high impurity density region 53 is formed in a self-aligned manner on a side wall spacer mask (not shown) formed on the side wall of the gate electrode 40 in a self-aligned manner with respect to the side wall of the gate electrode 40, which will be described in detail later in a manufacturing method. As a result, the gate electrode 40 is formed in a self-aligned manner. The length of the low impurity density region 52 in the channel length direction, that is, the LDD length is effectively determined by each of the thickness of the sidewall spacer mask and the lateral diffusion amount of the impurity, and according to the first embodiment of the present invention. In such a liquid crystal driver device 1, 100 nm or less, preferably 5 nm or less.
It is formed within a range of 0 nm to 70 nm.

The low breakdown voltage n according to the first embodiment of the present invention
The channel IGFET Q _NL has a low impurity density region 52 in which the diffusion depth is deeper than the diffusion depth of the high impurity density region 53 and the low impurity density region 52 is disposed along the side and bottom surfaces of the high impurity density region 53. Although it has a structure similar to the drain structure, since the length of the low impurity density region 52 between the channel region and the high impurity density region 53, that is, the LDD length is adjusted using the sidewall spacer mask, This will be described as an LDD structure.

[0065] Further, in the low-voltage n-channel IGFETQ _NL according to the first embodiment of the present invention, which is formed in high impurity concentration than the well region 303 between the channel region and the low impurity concentration region 52 p A type semiconductor region (p pocket region) 51 is provided. The p-type semiconductor region 51 can suppress the extension of the empty layer formed in the channel region from the low impurity density region 52, and can further suppress the short channel effect.

Source region of low voltage n-channel IGFET Q _NL
A wiring 77 is electrically connected to each high impurity density region 53 of the drain region. The liquid crystal driver device 1 according to the first embodiment of the present invention employs a two-layer wiring structure, and the wiring 77 is formed as a first-layer wiring of the two-layer wiring. The wiring 77 is formed on an interlayer insulating film 75 covering the entire surface of the semiconductor substrate 30.
High impurity density region 53 through connection hole 76 formed in
It is connected to the.

Further, a wiring 81 formed as a second-layer wiring of a two-layer wiring is electrically connected to the wiring 77. The wiring 81 is formed on the interlayer insulating film 78 covering the entire surface of the semiconductor substrate 30 on the wiring 77, and is connected to the wiring 77 through a connecting hole wiring 80 buried in a connecting hole 79 formed in the interlayer insulating film 78. ing.

The low-breakdown-voltage p-channel IGFET Q _PL is disposed in a region surrounded by the element isolation region 31 on the main surface of the n ⁻ -type well region 301 having a low impurity density.
The well region 301 is formed on the main surface of the semiconductor substrate 30. The element isolation region 31 is a low withstand voltage n-channel I
GFETQ _NL those same and the element isolation region 31 disposed around the are used. An n-type channel stopper region 32 having a higher impurity density than the well region 301 is formed in a region along the bottom surface of the element isolation region 31 on the surface of the well region 301. Low voltage p-channel IGFET Q _PL
Is constructed including a channel region formed by the well region 301, a gate insulating film 36 on the channel region, a gate electrode 41 on the gate insulating film 36, and a source region and a drain region having an LDD structure. I have.

[0069] The gate insulating film 36, each of the gate electrodes 41, the gate insulating film 3 of the low-voltage n-channel IGFETQ _NL
5. The same material and the same layer as the respective gate electrodes 40 are used.

Source region, drain region (main current region)
Are each formed of a p-type low impurity density region (semiconductor region or diffusion region) 55 and ap ⁺ -type high impurity density region (semiconductor region or diffusion region) 56 which are LDD portions. The low impurity density region 55 is formed in contact with the channel region, and is formed at least between the channel region and the high impurity density region 56 formed near the channel region. The low impurity density region 55 is formed in self alignment with the gate electrode 41. The high impurity density region 56 is formed in a self-alignment manner with a side wall spacer mask (not shown) formed on the side wall of the gate electrode 41 in a self-alignment manner with the side wall of the gate electrode 41, which will be described in detail later in a manufacturing method. As a result, the gate electrode 41 is formed in a self-aligned manner. Length That LDD length of the low impurity concentration region 55 in the channel length direction, like the LDD length of the low-voltage n-channel IGFETQ _NL, 100nm or less, preferably formed in the range of 50 nm to 70 nm.

The low breakdown voltage p according to the first embodiment of the present invention
In the channel IGFET Q _PL , the diffusion depth of the low impurity density region 55 is deeper than the diffusion depth of the high impurity density region 56, like the low breakdown voltage n-channel IGFET Q _NL.
Has a structure similar to a double drain structure in which a low impurity density region 55 is arranged along the side and bottom surfaces of the low impurity density region 55 between the channel region and the high impurity density region 56. That is, since the LDD length is adjusted using the sidewall spacer mask, the description will be made as an LDD structure.

Source region of low voltage p-channel IGFET Q _PL
A wiring 77 as a first-layer wiring is electrically connected to each of the high impurity density regions 56 in the drain region.
Further, a wiring 81 as a second layer wiring is electrically connected to the wiring 77 through a connection hole wiring 80.

[0073] On the other hand, the high-voltage n-channel IGFETQ _NH, the basic structure is the same as the low-voltage n-channel IGFETQ _NL, p of low impurity density ^- the main surface of the mold well region 304,
It is arranged in a region surrounded by the element isolation region 31. The well region 304 is formed on the main surface of the semiconductor substrate 30. A region along the bottom surface of the element isolation region 31 on the surface of the well region 304 is
P-type channel stopper region 33 having an impurity density higher than 4
Are formed. The high-breakdown-voltage n-channel IGFET Q _NH includes a channel region formed by the well region 304, a gate insulating film 37 on the channel region, a gate electrode 42 on the gate insulating film 37, a source region and a drain region having an LDD structure. It is built with.

The gate insulating film 37 basically has a low breakdown voltage n
The gate insulating film 35 of the channel IGFETQ _NL, are formed in the same material as the respective gate insulating films 36 of a low voltage p-channel IGFETQ _PL, and is formed with a thick thickness in order to increase the breakdown voltage. The gate electrode 42 has a low withstand voltage n channel I
GFET Q _NL gate electrode 40, low breakdown voltage p-channel IGFET Q _PL
And is formed of the same material as each of the gate electrodes 41.

Source region, drain region (main current region)
Are each formed of an n-type low impurity density region (semiconductor region or diffusion region) 61 and an n ⁺ -type high impurity density region (semiconductor region or diffusion region) 62 which are LDD portions. The low impurity density region 61 is formed in contact with the channel region, and is formed at least between the channel region and the high impurity density region 62 formed near the channel region. The low impurity density region 61 is formed in self alignment with the gate electrode 42. High impurity concentration regions 53 of low voltage n-channel IGFETQ _NL, like the respective high impurity concentration region 56 of the low-voltage p-channel IGFETQ _PL, the high impurity concentration regions 62,
As will be described in detail later in the manufacturing method, the gate electrode 42 is formed in a self-aligned manner with a side wall spacer mask (not shown) formed in a self-aligned manner with respect to the gate electrode 42, and as a result, the gate is formed. The electrode 42 is formed in a self-aligned manner. The length of the low impurity density region 61 in the channel length direction, that is, the LDD length is effectively determined by each of the thickness of the sidewall spacer mask and the lateral diffusion amount of the impurity, and in order to improve the breakdown voltage,
Liquid crystal driver device 1 according to the first embodiment of the present invention
Is formed in a thickness of 100 nm or more, preferably in the range of 400 nm to 600 nm.

The high breakdown voltage n according to the first embodiment of the present invention
Although the channel IGFET Q _NH has an almost complete LDD structure in which the diffusion depth of the low impurity density region 61 and the diffusion depth of the high impurity density region 62 are equal, the present invention is not necessarily limited to this structure. it may be constituted by LDD structure similar to a double diffusion structure such as n-channel IGFETQ _NL.

The source region of the high breakdown voltage n-channel IGFET Q _NH ,
A wiring 77 serving as a first-layer wiring is electrically connected to each of the high impurity density regions 62 in the drain region.
Further, although not shown in FIG. 1, a wiring 81 as a second layer wiring is connected to the wiring 77 through a connection hole wiring 80.

[0078] High-voltage p-channel IGFETQ _PH, the basic structure is the same as the low withstand voltage p-channel IGFETQ _PL, n low impurity density ^- the main surface of the mold well region 302, around the element isolation region 31 It is located in the enclosed area. Well region 302 is formed on the main surface of semiconductor substrate 30. An n-type channel stopper region 32 having a higher impurity density than the well region 302 is formed in a region along the bottom surface of the inter-element isolation region 31 on the surface of the well region 302. The high-breakdown-voltage p-channel IGFET Q _PH includes a channel region formed by the well region 302, a gate insulating film 38 on the channel region, a gate electrode 43 on the gate insulating film 38, a source region and a drain region having an LDD structure. It is built with.

Each of the gate insulating film 38 and the gate electrode 43 is the gate insulating film 3 of the high-breakdown-voltage n-channel IGFET Q _NH
7. The gate electrode 42 is formed of the same material and the same layer as each of the gate electrodes 42.

Source region, drain region (main current region)
Are each formed of a p-type low impurity density region (semiconductor region or diffusion region) 65 and a p ⁺ -type high impurity density region (semiconductor region or diffusion region) 66 which are LDD portions. The low impurity density region 65 is formed in contact with the channel region, and is formed at least between the channel region and the high impurity density region 66 formed near the channel region. The low impurity density region 65 is formed in self alignment with the gate electrode 43. High impurity concentration regions 53 of low voltage n-channel IGFETQ _NL, like the respective high impurity concentration region 56 of the low-voltage p-channel IGFETQ _PL, the high impurity concentration region 66,
As will be described in detail in a later-described manufacturing method, the gate electrode 43 is formed in a self-alignment manner with a side wall spacer mask (not shown) formed in a self-alignment manner with respect to the gate electrode 43, and as a result, the gate The electrode 43 is formed in a self-aligned manner. The length of the low impurity density region 65 in the channel length direction, that is, the LDD length is a high withstand voltage n-channel IGFE
As in the LDD length of TQ _NH , 100 nm or more, preferably 400 nm to 60 nm
It is formed within the range of 0 nm.

The high withstand voltage p according to the first embodiment of the present invention
Although the channel IGFET Q _PH has a substantially complete LDD structure in which the diffusion depth of the low impurity density region 65 and the diffusion depth of the high impurity density region 66 are equal, the present invention is not necessarily limited to this structure. it may be constituted by LDD structure similar to a double diffusion structure such as a p-channel IGFETQ _PL.

The source region of the high-breakdown-voltage p-channel IGFET Q _PH ,
A wiring 77 serving as a first-layer wiring is electrically connected to each of the high impurity density regions 65 in the drain region.
Further, a wiring 81 as a second layer wiring is connected to the wiring 77 through a connection hole wiring 80.

A final protective film 82 is formed on the entire surface of the semiconductor substrate 30 on the wiring 81. Final protective film 82
Are formed for the purpose of preventing intrusion of contaminants from the outside to the inside of the liquid crystal driver device 1 and reducing stress from the outside.

<Method of Manufacturing Liquid Crystal Driver Device>
A method for manufacturing the above-described liquid crystal driver device 1 will be described. 4A to 16 and FIGS. 17 to 20 are process cross-sectional views for explaining a method of manufacturing the liquid crystal driver device 1 according to the first embodiment of the present invention. .

(1) First, a low impurity density p ⁻ type semiconductor substrate 30 made of single crystal silicon is prepared (FIG. 4A).
reference). As the semiconductor substrate 30, for example, a substrate having a resistance of about 4.5 Ωcm to 6.0 Ωcm can be practically used.

(2) On the main surface of the semiconductor substrate 30,
The formation region of the low withstand voltage p-channel IGFETQ _PL of low impurity density
n ^- -type well region 301, the high-voltage p region for forming the channel IGFETQ _PH n ^- each type well region 302 is formed in the same manufacturing process, even lower voltage n-channel IGFETQ _NL as shown in FIG. 4 (A) A p ^- type well region 303 in the formation region,
Each of the p ^- type well regions 304 is formed in the formation region of the high breakdown voltage n-channel IGFET Q _NH by the same manufacturing process. Each of the well regions 301 and 302 is doped with, for example, phosphorus (P) ions as an n-type impurity at an area impurity density (dose amount) of about 10 ¹² atoms / cm ² to 10 ¹³ atoms / cm ² and an acceleration energy of 150 keV to 170 keV. Under the conditions described above, it can be formed by introducing ions into the main surface of the semiconductor substrate 30 by ion implantation. Each of the well regions 303 and 304 is doped with, for example, boron (B) ions as p-type impurities at 10 ¹² at.
oms / cm ² to 10 ¹³ atoms / cm ² dose, 90 keV to 110 ke
Under the condition of V acceleration energy, it can be formed by introducing ions into the main surface of the semiconductor substrate 30 by ion implantation.

(3) As shown in FIG. 4B, an element isolation region 31 is formed on the surface of the semiconductor substrate 30 between the formation regions of the IGFETs Q _NL , Q _PL , Q _NH , and Q _PH. . The element isolation region 31 is formed in a semiconductor substrate 30 (actually, well regions 301 to 30) in a hydrogen (H ₂ ) gas and oxygen (O ₂ ) gas atmosphere at a temperature of 800 ° C. to 1000 ° C.
It can be formed by selectively oxidizing the surface of 4). The element isolation region 31 is formed to a thickness of, for example, 650 nm to 800 nm.

(4) Each IGFET Q _NL , Q _PL ,
In the formation region of Q _NH and Q _PH , well regions 301 to 3
A buffer silicon oxide film (dummy silicon oxide film) 310 is formed on each surface of the semiconductor device 04 (FIG. 5).
(A)). The buffer silicon oxide film 310 is formed for the purpose of reducing damage to the surface portions of the well regions 301 to 304 due to ion implantation, preventing intrusion of contaminants, and the like. The buffer silicon oxide film 310 is formed, for example, in an atmosphere of O ₂ gas and hydrogen chloride (HCl) gas at 800 ° C. to 95 ° C.
At a temperature of 0 ° C., each of the well regions 301 to 304 can be formed by dry oxidation. The buffer silicon oxide film 310 has a thickness of, for example, 20 nm.
It is formed with a thickness of about 25 nm.

[0089] (5) introducing a threshold voltage adjusting impurities 308 in the surface portion of the well region 303 in the formation region of the low-breakdown-voltage n-channel IGFETQ _NL (see FIG. 5 (A)). The impurity 308 for adjusting the threshold voltage is introduced twice in the liquid crystal driver 1 according to the first embodiment of the present invention, and the impurity density profile is optimized. The first time, for example, B ions as p-type impurities, 10
Under the conditions of a dose (area impurity density) of about ¹² atoms / cm ² to 10 ¹³ atoms / cm ^{2 and} an acceleration energy of 110 keV to 130 keV, a peak is formed in a relatively deep portion of the well region 303 by ion implantation. It is introduced through the silicon oxide film 310 for buffering. The second time, for example
B ions are implanted as p-type impurities into a relatively shallow portion of the well region 303 by ion implantation under the conditions of a dose (area impurity density) of about 10 ¹² atoms / cm ^{2 and} an acceleration energy of 20 keV to 30 keV. It is introduced through the buffer silicon oxide film 310 so as to have a peak.

[0090] Subsequently, to introduce a threshold voltage adjusting impurities 306 in the surface portion of the well region 301 are formed in the formation region of the low withstand voltage p-channel IGFETQ _PL (see FIG. 5 (A)). The threshold voltage adjusting impurity 306 is introduced three times in the liquid crystal driver device 1 according to the first embodiment of the present invention for the same reason as the threshold voltage adjusting impurity 308. In the first time, the well region 301 is implanted, for example, by ion-implanting P ions as n-type impurities under the conditions of a dose (area impurity density) of about 10 ¹³ atoms / cm ^{2 and} an acceleration energy of 280 keV to 320 keV. Is introduced through the buffering silicon oxide film 310 so as to have a peak at a relatively deep portion. The second time, for example
By implanting arsenic (As) ions as n-type impurities under conditions of a dose (area impurity density) of about 10 ¹³ atoms / cm ^{2 and} an acceleration energy of 280 keV to 320 keV, the well region 301 It is introduced through the buffer silicon oxide film 310 so as to have a peak at a deep portion. In the third time, for example, a p-type impurity is used. B ions are used as the p-type impurity under the conditions of a dose (area impurity density) of about 10 ¹² atoms / cm ^{2 and} an acceleration energy of 15 keV to 25 keV. The implantation is performed through the buffer silicon oxide film 310 so as to have a peak at a relatively shallow portion of the well region 303.

Subsequently, a threshold voltage adjusting impurity 309 is introduced into the surface portion of the well region 304 in the formation region of the high breakdown voltage n-channel IGFET Q _NH (see FIG. 5A). The threshold voltage adjusting impurity 309 is introduced twice in the liquid crystal driver device 1 according to the first embodiment of the present invention for the same reason as the threshold voltage adjusting impurity 308. In the first time, the well region 304 is implanted, for example, by implanting B ions as p-type impurities under the conditions of a dose (area impurity density) of about 10 ¹² atoms / cm ^{2 and} an acceleration energy of 150 keV to 180 keV. Is introduced through the buffering silicon oxide film 310 so as to have a peak at a relatively deep portion. The second time, for example
By implanting B ions as p-type impurities under the conditions of a dose (area impurity density) of about 10 ¹² atoms / cm ^{2 and} an acceleration energy of 30 keV to 50 keV, a relatively shallow portion of the well region 304 is formed. It is introduced through the buffer silicon oxide film 310 so as to have a peak.

Then, as shown in FIG.
The well region 30 in the formation region of the p-channel IGFET Q _PH
Then, a threshold voltage adjusting impurity 307 is introduced into the surface portion of the second substrate. The threshold voltage adjusting impurity 307 is introduced in three steps in the liquid crystal driver device 1 according to the first embodiment of the present invention for the same reason as the threshold voltage adjusting impurity 308. In the first time, the well region 302 is implanted, for example, by ion-implanting P ions as n-type impurities under the conditions of a dose (area impurity density) of about 10 ¹³ atoms / cm ^{2 and} an acceleration energy of 280 keV to 320 keV. Is introduced through the buffering silicon oxide film 310 so as to have a peak at a relatively deep portion. The second time, for example
By ion implantation of As ions as n-type impurities under the conditions of a dose (area impurity density) of about 10 ¹³ atoms / cm ^{2 and} an acceleration energy of 280 keV to 320 keV, a relatively deep portion of the well region 302 is formed. It is introduced through the buffer silicon oxide film 310 so as to have a peak. Third
In the third time, for example, a p-type impurity is used, and B ions are implanted as the p-type impurity under the conditions of a dose (area impurity density) of about 10 ¹² atoms / cm ^{2 and} an acceleration energy of 15 keV to 25 keV. As a result, the impurity is introduced through the buffer silicon oxide film 310 so as to have a peak at a relatively shallow portion of the well region 302.

(6) A p-type channel stopper region 33 having a higher impurity density than each of the well regions 303 and 304 is formed on the surface of each of the well regions 303 and 304 below the bottom surface of the element isolation region 31 ( FIG.
(B)). The channel stopper region 33 is formed, for example, by ion-implanting B ions as p-type impurities under the conditions of a dose (area impurity density) of about 10 ¹² atoms / cm ^{2 and} an acceleration energy of 110 keV to 130 keV. It can be formed on each surface portion of the well regions 303 and 304 passing through the separation region 31.

Subsequently, as shown in FIG. 5B, the well regions 301 and
Well regions 301, 30 are provided on respective surface portions of 302.
2. An n-type channel stopper region 32 having a higher impurity density than that of each of the gate electrodes 2 is formed. This channel stopper region 32
Is, for example, P ions as n-type impurities at 10 ¹³ atoms / cm ²
Ion implantation is performed under the conditions of a moderate dose (area impurity density) and acceleration energy of 280 keV to 320 keV to form a well region 301 through the element isolation region 31.
302 can be formed on each surface portion.

(7) The silicon oxide film for buffer 310 on the surface of the well regions 301 to 304 is removed.
Thereafter, for example, in an atmosphere of O ₂ gas and HCl gas, 700 ° C. to 80 ° C.
At a temperature of 0 ° C., the surface of each of the well regions 301 to 304 is wet-oxidized to obtain a structure shown in FIG.
As shown in FIG. 7, at least the gate insulating film 37A on the surface of the well region 304 in the formation region of the high breakdown voltage n-channel IGFET Q _NH and the gate insulating film 38A on the surface of the well region 302 in the formation region of the high breakdown voltage p-channel IGFET Q _PH To form Each of the gate insulating films 37A and 38A is formed of a silicon oxide film, for example, 15 nm to 20 nm.
It is formed with a film thickness of about. Thickness gate insulating film 37A is formed to a thickness increased for the purpose of improvement in breakdown voltage of the high voltage n-channel IGFETQ _NH, similarly the gate insulating film 38A is for the purpose of improvement in breakdown voltage of the high voltage p-channel IGFETQ _PH Formed for increase.

[0096] (8) (corresponding to 37A or 38A) low-voltage n-gate insulating film on the surface of the channel IGFETQ _NL well region 303 in the formation region of the low withstand voltage p-channel IGF
The gate insulating film (similarly, 37A or 38A) on the surface of the well region 301 is selectively removed in the ETQ _PL formation region. Thereafter, for example, in a O ₂ gas and HCl gas atmosphere at a temperature of 700 ° C. to 800 ° C., the well region 3
By wet oxidizing the respective surfaces of the n-channel IGFETs 01 to 304 as shown in FIG.
Q _NL gate insulating film 35 on the surface of the well region 303 in the formation region of the gate insulating film 36 on the surface of the well region 301 in the low-voltage p-channel IGFETQ _PL formation region of the are formed respectively, and the high-voltage n Channel IGFET
Gate further grown gate insulating film 37A on the surface of the well region 304 are formed in the formation region of the Q _NH insulating film 3
7, a gate insulating film 38 in which a gate insulating film 38A is further grown is formed on the surface of the well region 302 in the formation region of the high breakdown voltage p-channel IGFET Q _PH .
Each of the gate insulating films 35 and 36 is formed of a silicon oxide film and has a thickness of, for example, about 8 nm to 10 nm. Each of the gate insulating films 37 and 38 is formed of a silicon oxide film and has a thickness of, for example, about 20 nm to 25 nm.

(9) For example, low-pressure CVD is performed on the entire surface of the semiconductor substrate 30 including the respective surfaces of the gate insulating films 35 to 38.
To form a polycrystalline silicon film 461 (FIG. 7A)
reference). The polycrystalline silicon film 461 is, for example, 180 nm to 220 nm.
It is formed with a film thickness of. Next, POCl ₃ gas, O ₂ gas and N ₂
P, which is an n-type impurity, is diffused into the polycrystalline silicon film 461 for about 60 to 80 minutes at a temperature of 800 ° C. to 900 ° C. in a mixed gas atmosphere of gas, and the specific resistance of the polycrystalline silicon film 461 is set to 80Ω. Adjust within the range of / □ to 120Ω / □. Then, as shown in FIG. 7A, the polycrystalline silicon film 461 is formed.
A tungsten silicide (WSi ₂ ) film 462 is formed on the entire upper surface by, for example, sputtering. The WSi ₂ film 462 is formed with a thickness of, for example, 180 nm to 220 nm.

(10) As shown in FIG. 7A, each of the WSi ₂ film 462 and the polycrystalline silicon film 461 is patterned using the same mask (not shown) to form a low breakdown voltage n-channel IGF.
On the polycrystalline silicon film 401 in the ETQ _NL formation region
The gate electrode 40 by stacking a WSi ₂ film 402, the low-voltage p-channel IGFETQ _PL polycrystalline silicon film 4 in a region of the
The gate electrode 41 by stacking the WSi ₂ layer 412 on the 11, the high-voltage n-channel IGFETQ gate electrode 4 formed by laminating a WSi ₂ film 422 on the polysilicon film 421 in the formation region of the _NH
2. In the formation region of the high-breakdown-voltage p-channel IGFET Q _PH , each of the gate electrodes 43 in which the WSi ₂ film 432 is laminated on the polycrystalline silicon film 431 is formed. For patterning, for example, reactive ion etching (RIE)
ing) can be used practically. Gate electrode 4
The gate length of each of the gates 0 and 41 is, for example, 0.8 μm, and the gate length of each of the gate electrodes 42, 43 is, for example, 8 μm to 10 μm.

(11) The formation region of the high breakdown voltage n-channel IGFET Q _NH is opened, and the other formation regions (Q _NL , Q _PL , Q
A mask 901 which _covers the _PH formation regions is formed (see FIG. 8A). As the mask 901, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high-breakdown-voltage n-channel IGFET Q _NH , an n-type impurity having a low impurity density is introduced into the main surface of the well region 304 by using the mask 901 and the gate electrode 42 as an ion implantation mask.
As shown in FIG. 8A, an n-type low impurity density region 61 is formed. This low impurity density region 61 is formed in self-alignment with the gate electrode 42 in contact with the channel region without any manufacturing alignment. The low impurity density region 61
For example, P ions are used as n-type impurities at 10 ¹² atoms / cm ² to 10
A dose of about ¹³ atoms / cm ² (area impurity density), 60 keV
Under the condition of acceleration energy of about 80 keV, ions are implanted to form the main surface of the well region 304 through the gate insulating film 37.

(12) After removing the mask 901, a mask in which the formation region of the high-breakdown-voltage p-channel IGFET Q _PH is opened and the other formation regions (the formation regions of Q _NL , Q _PL and Q _NH ) are covered 902 are formed (see FIG. 8B). As the mask 902, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high breakdown voltage p-channel IGFET Q _PH , the mask 902 and the gate electrode 43 are used as an ion implantation mask, and a low impurity density p-type impurity is introduced into the main surface of the well region 302.
As shown in FIG. 8B, a p-type low impurity density region 65 is formed. The low impurity density region 65 is formed in self-alignment with the gate electrode 43 in contact with the channel region.
The low impurity density region 65 is formed, for example, by adding boron fluoride (BF ₂ ) ions as p-type impurities to 10 ¹² atoms / cm ² to 10 ¹³ atoms / cm.
Under a condition of a dose amount of about ² (area impurity density) and an acceleration energy of 40 keV to 60 keV, ions are implanted to form a main surface portion of the well region 302 through the gate insulating film 38.

(13) After removing the mask 902, each surface of the gate electrodes 40 to 43 is oxidized at a temperature of 800 ° C. to 950 ° C. in an atmosphere of N ₂ gas and O ₂ gas, for example, to As shown in FIG.
To 43 can be formed. The insulating film 45 is formed at the end of the gate electrodes 40 to 43 in contact with the respective gate insulating films 35 to 38 for the purpose of preventing electric field concentration from occurring.
It is formed with a film thickness of about 10 nm to 20 nm.

(14) The formation region of the low-breakdown-voltage n-channel IGFET Q _NL is opened, and the other formation regions (Q _PL , Q _NH , Q
A mask 903 covering each _PH formation region is formed (see FIG. 9B). As the mask 903, for example, a photoresist mask formed by a photolithography technique is used.

[0105] Subsequently, in the formation region of the low-breakdown-voltage n-channel IGFETQ _NL, using a mask 903 and the gate electrode 40 as an ion implantation mask, a p-type impurity of high impurity concentration than the well region 303 in the main surface portion of the well region 303 By the introduction, a p-type semiconductor region (p pocket region) 51 is formed as shown in FIG. The semiconductor region 51 is formed in self-alignment with the gate electrode 40 only in the vicinity of the gate electrode 40 in contact with the channel region. The semiconductor region 51 is formed, for example, by adding B ions as p-type impurities to oblique ions under the conditions of a dose (area impurity density) of about 10 ¹² atoms / cm ² to 10 ¹³ atoms / cm ^{2 and} an acceleration energy of 40 keV to 60 keV. By implantation, it is formed on the main surface of the well region 303 through the gate insulating film 35. The oblique ion implantation means that the surface of the semiconductor substrate 30 (semiconductor wafer) is rotated while being inclined at, for example, 30 degrees.
The ion implantation is performed in this state.

(15) Subsequently, using the mask 903,
In the formation region of the low-breakdown-voltage n-channel IGFETQ _NL, by using the mask 903 and the gate electrode 40 as an ion implantation mask, an n-type impurity of low impurity concentration in the main surface portion of the well region 303, FIG. 10 (A) An n-type low impurity density region 52 is formed as shown in FIG. This low impurity density region 52 is in contact with the channel region (the first region of the present invention).
In the embodiment, the semiconductor region 51 is formed in the channel region.
Is formed in a self-aligned manner with respect to the gate electrode 40. The low-impurity-density region 52 is formed, for example, by ion-implanting P ions as n-type impurities under the conditions of a dose (area impurity density) of about 10 ¹⁴ atoms / cm ^{2 and} an acceleration energy of 30 keV to 50 keV. It is formed on the main surface of the well region 303 through the insulating film 35.

(16) After removing the mask 903, a mask in which the formation region of the low-breakdown-voltage p-channel IGFET Q _PL is opened and the other formation regions (the formation regions of Q _NL , Q _NH , and Q _PH ) are covered 904 are formed (see FIG. 10B). As the mask 904, for example, a photoresist mask formed by a photolithography technique is used.

[0108] Subsequently, in the forming region of the low withstand voltage p-channel IGFETQ _PL, by using the mask 904 and the gate electrode 41 as an ion implantation mask, an p-type impurity of low impurity concentration in the main surface portion of the well region 301,
As shown in FIG. 10B, the p-type low impurity density region 55
To form This low impurity density region 55 is formed in self-alignment with the gate electrode 41 in contact with the channel region. The low impurity density region 55 is, for example,
F ₂ ions are implanted through the gate insulating film 36 by ion implantation under the conditions of a dose (area impurity density) of about 10 ¹³ atoms / cm ² to 10 ¹⁴ atoms / cm ^{2 and} an acceleration energy of 25 keV to 45 keV. It is formed on the main surface of the well region 301.

(17) After removing the mask 904, FIG.
As shown in FIG. 1A, a first-layer sidewall spacer mask forming layer 70 is formed on the entire surface of the semiconductor substrate 30 on the gate electrodes 40 to 43 (actually on the insulating film 45). This sidewall spacer mask forming layer 70
Are the low impurity density regions 51 of the low breakdown voltage n-channel IGFET Q _NL
Length in the channel direction, ie LDD length, low breakdown voltage p-channel
The channel length of the low impurity concentration region 55 of IGFETQ _PL that is intended to form a sidewall spacer mask that determines the respective LDD length (701 and 702). Sidewall spacer mask forming layer 70
In the first embodiment of the present invention, is formed to a thickness of 100 nm or less, preferably 45 nm to 55 nm, formed by low-pressure CVD.

(18) Etching corresponding to the thickness of the film formed on the entire surface of the sidewall spacer mask forming layer 70 is performed, and the insulating film 45 is interposed on the side wall of the gate electrode 40 as shown in FIG. A side wall spacer mask 701 is formed in self-alignment with the lever electrode 40, and the insulating film 4 is formed on the side wall of the gate electrode 41 in the same manufacturing process.
5 and a sidewall spacer mask 702 is self-aligned with the gate electrode 41 with the gate electrode 42 interposed therebetween.
An insulating film 45 is interposed on the side wall of the gate electrode 42 and the side wall spacer mask 703 is self-aligned with the gate electrode 42.
The insulating film 45 is interposed on the side wall of the gate electrode 43, and the side wall spacer mask 704 is formed in self alignment with the gate electrode 43. Highly selective anisotropic chemical dry etching (CD
E) can be used practically.

FIG. 21A shows a low withstand voltage n-channel IGFET Q of the liquid crystal driver 1 according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional structural view of a main part of the _{NL in} the course of manufacture. Sidewall spacer mask 701 in the formation region of the low-breakdown-voltage n-channel IGFETQ _NL can have a substantially uniform thickness on the side wall of the gate electrode 40 are formed in the side wall spacers mask length L1. Sidewall spacer mask 70
2 is the same. Sidewall spacer mask length L1
Is set to 100 nm or less, preferably 45 nm to 55 nm in the first embodiment of the present invention.

(19) The formation region of the low breakdown voltage n-channel IGFET Q _NL is opened, and the other formation regions (Q _PL , Q _NH , Q
A mask 906 covering the respective _PH formation regions is formed (see FIG. 12A). As the mask 906, for example, a photoresist mask formed by a photolithography technique is used.

[0113] Subsequently, in the formation region of the low-breakdown-voltage n-channel IGFETQ _NL, mask 906, using the gate electrode 40 and the sidewall spacer mask 701 as an ion implantation mask, the main surface portion of the n-type impurity of high impurity concentration well region 303 As shown in FIG. 12A, an n ⁺ -type high impurity density region 53 is formed. The high impurity density region 53 is formed near the gate electrode 40 near the side of the channel region separated by the sidewall spacer mask length L1.
Is formed in a self-aligned manner. High impurity density region 53
Is, for example, an As ion as an n-type impurity, 10 ¹⁵ atoms / cm ²
Dose of about 10 ¹⁶ atoms / cm ² (area impurity density), 4
Under the condition of acceleration energy of 0 keV to 60 keV, ions are implanted to form a main surface portion of the well region 303 through the gate insulating film 35.

As shown in FIG. 21A, by forming the high impurity density region 53, the length of the low impurity density region 52, that is, the LDD length LD1 is effectively determined.
The length LD1 is set to 100 nm or less, preferably about 70 nm to 90 nm. Further, by forming a high-impurity density regions 53, a source region composed of high impurity concentration regions 53 and the low-impurity density regions 52, each drain region is almost completed, be almost completed the low-voltage n-channel IGFETQ _NL it can.

(20) After removing the mask 906, a mask in which the formation region of the low-breakdown-voltage p-channel IGFET Q _PL is opened and the other formation regions (the formation regions of Q _NL , Q _NH , and Q _PH ) are covered 907 is formed (see FIG. 12B). As the mask 907, for example, a photoresist mask formed by a photolithography technique is used.

[0116] Subsequently, in the forming region of the low withstand voltage p-channel IGFETQ _PL, mask 907, using the gate electrode 41 and the sidewall spacer mask 702 as an ion implantation mask, the main surface portion of the well region 301 to p-type impurity of high impurity concentration , A p ⁺ -type high impurity density region 56 is formed as shown in FIG. This high impurity density region 56 is formed near the gate electrode 41 near the channel region separated by the sidewall spacer mask length L1.
Is formed in a self-aligned manner. High impurity density region 56
Is, for example, BF ₂ ions as p-type impurities, 10 ¹⁵ atoms / cm
A dose of about ² to 10 ¹⁶ atoms / cm ² (area impurity density),
Under the condition of acceleration energy of 25 keV to 45 keV, ions are implanted to form a main surface portion of the well region 301 through the gate insulating film 36.

By forming the high impurity density region 56, the length of the low impurity density region 55, that is, the LDD length LD1
Is effectively determined (see FIG. 21A). Further, each of the source region and the drain region including the high impurity density region 56 and the low impurity density region 55 is almost completed, and the low breakdown voltage p-channel IGFET Q _PL is substantially Can be completed.

(21) After removing the mask 907, for example, high-selection CDE is performed on the entire surface of the semiconductor substrate 30, and FIG.
As shown in (A), all the sidewall spacer masks 701 to 704 are removed at once in the same manufacturing process. That is, when forming the sidewall spacer mask 701 in the formation region of the low breakdown voltage n-channel IGFET Q _NL and the sidewall spacer mask 702 in the formation region of the low breakdown voltage p-channel IGFET Q _PL , the side wall of the formation region of the high breakdown voltage n-channel IGFET Q _NH is formed. The spacer mask 703 and the sidewall spacer mask 704 in the formation region of the high breakdown voltage p-channel IGFET Q _PH are formed in the same manufacturing process, and the latter sidewall spacer masks 703 and 704 are left without being selectively removed. Finally, when the sidewall spacer masks 701 and 702 are finally removed, the sidewall spacer masks 703 and 7 are simultaneously removed.
By removing 04, a mask step for selectively removing the sidewall spacer masks 703 and 704 is not required.

(22) As shown in FIG. 13B, the second-layer sidewall spacer mask forming layer 71 is formed on the entire surface of the semiconductor substrate 30 on the gate electrodes 40 to 43 (actually on the insulating film 45). To form This side wall spacer mask forming layer 71 is made of a high withstand voltage n-channel IGFET Q
Channel direction length or LDD length of the low impurity concentration region 61 of _NH, sidewall spacer mask (713 to determine the respective high-voltage p-channel IGFETQ low impurity in the channel direction of the density region 65 length or LDD length of _PH and 714). In the first embodiment of the present invention, the sidewall spacer mask forming layer 71 is formed to have a thickness of 100 nm or more, preferably 350 nm to 450 nm, formed by low pressure CVD.

(23) Etching corresponding to the thickness of the film formed on the entire surface of the sidewall spacer mask forming layer 71 is performed, and the insulating film 45 is interposed on the side wall of the gate electrode 40 as shown in FIG. A side wall spacer mask 711 is formed in self-alignment with the lever gate electrode 40, and the insulating film 4 is formed on the side wall of the gate electrode 41 in the same manufacturing process.
5, a sidewall spacer mask 712 is self-aligned with the gate electrode 41,
An insulating film 45 is interposed on the side wall of the gate electrode 42 so as to be self-aligned with the side wall spacer mask 713.
The insulating film 45 is interposed on the side wall of the gate electrode 43, and the side wall spacer masks 714 are formed in self alignment with the gate electrode 43, respectively. A highly anisotropic, highly selective CDE can be used for etching.

FIG. 21B shows a high breakdown voltage n-channel IGFET Q of the liquid crystal driver device 1 according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional structural view of a main part in the course of manufacturing _NH . Sidewall spacer mask 713 in a region of the high withstand voltage n-channel IGFETQ _NH is formed by a circular arc cross sectional shape thickness from top to bottom on the side walls of the gate electrode 40 gradually becomes thicker, most film thickness thicker portion It can be formed as the sidewall spacer mask length L2. The same applies to the sidewall spacer mask 714. The side wall spacer mask length L2 is set to 100 nm or more, preferably 350 nm to 450 nm in the first embodiment of the present invention.

(24) The formation region of the high-breakdown-voltage n-channel IGFET Q _NH is opened, and the other formation regions (Q _NL , Q _PL , Q
A mask 908 covering the _PH formation regions is formed (see FIG. 14B). As the mask 908, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high-breakdown-voltage n-channel IGFET Q _NH , the mask 908, the gate electrode 42 and the sidewall spacer mask 713 are used as ion implantation masks, and a high impurity density n-type impurity is added to the main surface of the well region 304. As shown in FIG. 14B, an n ⁺ -type high impurity density region 62 is formed. The high impurity density region 62 is formed near the gate electrode 42 near the channel region separated by the sidewall spacer mask length L2.
Is formed in a self-aligned manner. High impurity density region 62
Is, for example, an As ion as an n-type impurity, 10 ¹⁵ atoms / cm ²
Dose of about 10 ¹⁶ atoms / cm ² (area impurity density), 5
Under the condition of acceleration energy of 0 keV to 70 keV, ions are implanted to form a main surface portion of the well region 304 through the gate insulating film 37.

As shown in FIG. 21B, by forming the high impurity density region 62, the length of the low impurity density region 61, that is, the LDD length LD2 is effectively determined.
The length LD2 is set to 100 nm or more, preferably about 400 nm to 600 nm. Further, by forming the high impurity density region 62, each of the source region and the drain region including the high impurity density region 62 and the low impurity density region 61 is almost completed, and the high breakdown voltage n-channel IGFET Q _NH can be almost completed. it can.

(25) After removing the mask 908, a mask in which the formation region of the high breakdown voltage p-channel IGFET Q _PH is opened and the other formation regions (the formation regions of Q _NL , Q _PL , and Q _NH ) are covered 909 are formed (see FIG. 15A). As the mask 909, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high-breakdown-voltage p-channel IGFET Q _PH , the mask 909, the gate electrode 43, and the sidewall spacer mask 714 are used as ion implantation masks, and a high impurity density p-type impurity is 15A, a p ⁺ -type high impurity density region 66 is formed as shown in FIG. The high impurity density region 66 is formed near the gate electrode 43 near the channel region separated by the sidewall spacer mask length L2.
Is formed in a self-aligned manner. High impurity density region 66
Is, for example, BF ₂ ions as p-type impurities, 10 ¹⁵ atoms / cm
A dose of about ² to 10 ¹⁶ atoms / cm ² (area impurity density),
Under the condition of an acceleration energy of 40 keV to 60 keV, ions are implanted to form a main surface portion of the well region 302 through the gate insulating film 38.

By forming the high impurity density region 66, the length of the low impurity density region 65, that is, the LDD length LD2
Is effectively determined (see FIG. 21B). Further, each of the source region and the drain region including the high impurity density region 66 and the low impurity density region 65 is almost completed, and the high breakdown voltage p-channel IGFET Q _PH is substantially reduced. Can be completed.

(26) After removing the mask 909, for example, high-selection CDE is performed on the entire surface of the semiconductor substrate 30, and the removal of the sidewall spacer masks 701 to 704 is performed in the same manner as described above.
As shown in FIG. 15B, all the sidewall spacer masks 711 to 714 are removed at once in the same manufacturing process.

[0129] (27) Next, N ₂ gas atmosphere, 750 ° C. to 8
At a temperature of 50 ° C., activation annealing is performed for about 15 minutes to 25 minutes to activate each of the source region and the drain region, thereby obtaining a low breakdown voltage n as shown in FIG.
Each of the channel IGFET Q _NL , the low-breakdown-voltage p-channel IGFET Q _PL , the high-breakdown-voltage n-channel IGFET Q _NH , and the high-breakdown-voltage p-channel IGFET Q _PH can be substantially completed.

(28) As shown in FIG. 16B, an interlayer insulating film 75 is formed on the entire surface of the semiconductor substrate 30. In the liquid crystal driver device 1 according to the first embodiment of the present invention, the interlayer insulating film 75 includes a silicon oxide film 751, a boron phosphosilicate glass (BPSB) film 752, and a phosphosilicate glass (PSB) film 753. A composite film in which each is sequentially laminated is used. The silicon oxide film 751 is formed by CVD, and has a thickness of 130 nm to 170 nm. The BPSB film 752 is formed by low-pressure CVD and has a thickness of 800 nm to 1000 nm. This BPSB film 752
Is about 750 ° C. to 850 ° C. in a N ₂ gas atmosphere.
The glass flow is performed for 35 to 45 minutes, and the surface is flattened. The PSB film 753 is formed by normal pressure CVD, and its film thickness is
It is formed between 250 nm and 350 nm.

(29) Each IGFET Q _NL , Q _PL , Q
_On the source and drain regions of _NH and Q _PH ,
A connection hole 76 is formed in the interlayer insulating film 75 (see FIG. 17). The connection hole 76 is formed by an interlayer insulating film 75 by RIE, for example.
Can be formed by selectively removing.

(30) As shown in FIG.
A first layer wiring 77 connected to each of the source region and the drain region through is formed on the interlayer insulating film 75. In the liquid crystal driver device 1 according to the first embodiment of the present invention, the wiring 77 has a titanium (Ti) film 771,
A composite film in which a titanium nitride (TiN) film 772, an aluminum alloy (Al-Cu-Si) film 773, and a TiN film 774 are sequentially laminated is used. The Ti film 771 is formed by sputtering, and has a thickness of 15 nm to 25 nm. The TiN film 772 is formed by sputtering, and has a thickness of 60 nm to 80 nm. The Al-Cu-Si film 773 is formed by sputtering, and has a thickness of 500 nm to 700 nm. The TiN film 774 is formed by sputtering,
Its film thickness is formed between 25 nm and 35 nm. These Ti films 77
1, each of the TiN film 772, the Al—Cu—Si film 773, and the TiN film 774 is sequentially formed and then patterned by, eg, RIE.

(31) As shown in FIG. 18, an interlayer insulating film 78 is formed over the wiring 77 over the entire surface of the interlayer insulating film 75. In the liquid crystal driver device 1 according to the first embodiment of the present invention, as the interlayer insulating film 78, a composite film in which a tetraethoxysilane (TEOS) film 781 and a TEOS film 782 are sequentially laminated is used. . TEOS film 781
Is formed by forming a film having a thickness of about 1300 nm to 1700 nm, further applying a resist film having a thickness of 600 nm to 700 nm on the upper layer, and etching the entire surface by RIE to planarize the surface. The TEOS film 781 is finally formed with a thickness of about 500 nm to 650 nm. The TEOS film 782 is formed on the flattened surface of the TEOS film 781, and has a thickness of 450 nm to 550 nm.

(32) A connection hole 79 is formed in the interlayer insulating film 78 on the connection region between the wiring 77 and the upper layer wiring (see FIG. 19). For the connection hole 79, for example, RIE can be practically used.

(33) As shown in FIG.
A connection hole wiring 80 buried therein is formed. In the liquid crystal driver device 1 according to the first embodiment of the present invention,
A tungsten (W) film formed by selective CVD is used for the connection hole wiring 80, and the W film is formed to a thickness of, for example, 550 nm to 650 nm.

(34) As shown in FIG. 20, the second-layer wiring 81 connected to the wiring 77 through the connection hole wiring 80
Is formed on the interlayer insulating film 78. In the liquid crystal driver device 1 according to the first embodiment of the present invention, similarly to the wiring 77, the Ti film 811, the TiN film 812, the Al-
A composite film in which a Cu-Si film 813 and a TiN film 814 are sequentially laminated is used. The Ti film 811 is formed by sputtering, and has a thickness of 15 nm to 25 nm. TiN
The film 812 is formed by sputtering and has a thickness of 60 nm.
Formed at ~ 80 nm. The Al-Cu-Si film 813 is formed by sputtering, and has a thickness of 900 nm to 1100 nm. The TiN film 814 is formed by sputtering, and has a thickness of 25 nm to 35 nm. These Ti films 811, Ti
After each of the N film 812, the Al—Cu—Si film 813, and the TiN film 814 are sequentially formed, they are patterned by, for example, RIE.

(35) As shown in FIG.
1, a final protective film 82 is formed on the entire surface of the interlayer insulating film 78.
To form In the liquid crystal driver device 1 according to the first embodiment of the present invention, the final protective film 82 has a normal pressure CVD
A composite film is used in which a PSG film 821 formed by the method described above and a silicon nitride film 822 formed by the plasma CVD are sequentially laminated.

When a series of these manufacturing steps is completed, the liquid crystal driver 1 according to the first embodiment of the present invention can be completed.

[0139] As described above, the first in the liquid crystal driver device (liquid crystal driver semiconductor device) 1 according to the embodiment, the low-voltage n-channel IGFETQ length of _NL in the low impurity density regions 52 of the present invention ( LDD length) LD1, low withstand voltage p
Length of low impurity density region 55 of channel IGFET Q _PL (LDD
Long) Since all of the LDs 1 can be made uniform, variations in the current (main current amount) between the source region and the drain region can be reduced. Similarly, high withstand voltage n-channel I
GFETQ Length of low impurity density region 61 of _NH (LDD length) LD
2. Low impurity density region 65 of high breakdown voltage p-channel IGFET Q _PH
Length (LDD length) LD2 can be made uniform, so that the current between the source region and the drain region (main current)
Can be reduced. Therefore, the electrical characteristics of the liquid crystal driver device 1 can be improved.

Further, in the liquid crystal driver device 1 according to the first embodiment of the present invention, in particular, the length LD2 of the low impurity density region 65 of the high breakdown voltage p-channel IGFET Q _PH can be made uniform. Variation in the main current amount of the dynamic amplification transistor (variation in the drain current) can be reduced, and variation in the offset voltage of the differential amplifier circuit 131 can be reduced.

Further, in the liquid crystal driver 1 according to the first embodiment of the present invention, the differential amplifier 131
Can be reduced, the image quality of the liquid crystal display unit 2 of the liquid crystal display device can be prevented from being poor, and the performance of the liquid crystal display device can be improved.

Further, in the liquid crystal driver 1 according to the first embodiment of the present invention, the differential amplifier 131
Can be reduced, so that it is not necessary to separately mount an offset voltage correction circuit, and the degree of integration can be improved.

Further, in the liquid crystal display device incorporating the liquid crystal driver device 1 according to the first embodiment of the present invention, it is possible to reduce the variation of the offset voltage of the differential amplifier circuit 131 of the liquid crystal driver device 1. Therefore, the image quality of the liquid crystal display unit 2 can be prevented from being poor, and the display performance can be improved.

Further, in the liquid crystal display device incorporating the liquid crystal driver device 1 according to the first embodiment of the present invention, the variation of the offset voltage of the differential amplifier circuit 131 of the liquid crystal driver device 1 is reduced. In addition, since it is not necessary to separately mount an offset voltage correction circuit, power consumption can be reduced.

Furthermore, in a notebook personal computer in which a liquid crystal display device incorporating the liquid crystal driver device 1 according to the first embodiment of the present invention is driven by a built-in battery, the power consumption of the built-in battery can be reduced. Therefore, long-time driving can be realized.

Further, in the method of manufacturing the liquid crystal driver device 1 according to the first embodiment of the present invention, the low withstand voltage n
Low impurity density regions 52 of the channels IGFETQ _NL, the length of the sidewall spacer mask 701, since each of the high impurity concentration region 53 can be formed in self-alignment with the gate electrode 40, uniformly low impurity density regions 52 (LDD length) It can be formed with LD1. Similarly, the low impurity concentration region 55 of the low-voltage p-channel IGFETQ _PL, the sidewall spacer mask 702, the high impurity concentration region 5
6 can be formed in a self-aligned manner with respect to the gate electrode 41, and thus can be formed with a uniform low impurity density region 55 length (LDD length) LD1. Similarly, the low impurity density region 6 of the high breakdown voltage n-channel IGFET Q _NH
1. Since each of the side wall spacer mask 713 and the high impurity density region 62 can be formed in a self-aligned manner with respect to the gate electrode 42, they are formed with a uniform low impurity density region 61 length (LDD length) LD2. be able to. Similarly, since each of the low impurity density region 65, the sidewall spacer mask 714, and the high impurity density region 66 of the high breakdown voltage p-channel IGFET Q _PH can be formed in self-alignment with the gate electrode 43, a uniform low impurity The density region 65 can be formed with the length (LDD length) LD2.

Further, in the method of manufacturing the liquid crystal driver device 1 according to the first embodiment of the present invention, the high withstand voltage n
N-channel IGFET Q _NL and p-channel IGFET with lower breakdown voltage than channel IGFET Q _NH and p-channel IGFET Q _{PH with} high breakdown voltage
Since the Q _PL are formed first, the high-voltage n-channel IGFETQ
Optimal low-breakdown-voltage n-channel IGFET Q _NL and low-breakdown-voltage p without being affected by the formation of _NH and high-breakdown-voltage p-channel IGFET Q _PH
It is possible to form the channel IGFETQ _PL. For example,
In the low-voltage n-channel IGFETQ _NL, a gate insulating film 3
5 Low impurity density regions 52, are used as the ion implantation buffer oxide film when forming the respective high impurity density regions 53, in the low-voltage p-channel IGFETQ _PL, a gate insulating film 36 low impurity density regions Although they are used as buffer oxide films for ion implantation when forming each of the high impurity density regions 55 and the high impurity density regions 56, these are formed by forming the low breakdown voltage n-channel IGFET Q _NL and the low breakdown voltage p-channel IGFET Q _PL first. High breakdown voltage n-channel IGFET Q _NH
Also, no processing damage is added when forming the high breakdown voltage p-channel IGFET Q _PH . Therefore, the low breakdown voltage n-channel IGFET Q
In forming the _NL and low-voltage p-channel IGFETQ _PL, the film thickness of processing damage is not added using ion implantation buffer oxide film thick state, the low impurity concentration region 5
2 and 55, and impurities for forming each of the high impurity density regions 53 and 56 can be introduced into the surface of the semiconductor substrate 30 by ion implantation, thereby causing damage to the surface of the semiconductor substrate 30 due to ion implantation. Can be prevented. Furthermore, since the peak of the density of the ion-implanted impurity can be set on the surface side of the semiconductor substrate 30, the low breakdown voltage n-channel IGFET Q _NL and the low breakdown voltage p-channel IGFET
It is possible to realize the shallowing of the respective source and drain regions of the Q _PL. By realizing this shallowing, the degree of integration of the liquid crystal driver device 1 can be improved, and the operation speed of the liquid crystal driver device 1 can be increased by reducing the parasitic capacitance added to the source region and the drain region. be able to.

Further, in the method for manufacturing the liquid crystal driver device 1 according to the first embodiment of the present invention, the low withstand voltage n
The sidewall spacer mask 701 is formed on the side wall of the gate electrode 40 in forming the high impurity concentration region 53 of the channel IGFETQ _NL, the gate electrode 41 in forming the high impurity concentration region 56 of the low-voltage p-channel IGFETQ _PL A side wall spacer mask 702 is formed on the side wall, and a side wall spacer mask 703 is formed on the side wall of the gate electrode 42 of the high withstand voltage n-channel IGFET Q _NH.
By forming a sidewall spacer mask 704 on the side wall of the gate electrode 43 of the channel IGFET Q _PH and forming the high impurity density regions 53 and 56, all the sidewall spacer masks 701 to 704 are removed by the same manufacturing process. The side wall spacer mask 701 is formed by etching the entire surface of the semiconductor substrate 30 without requiring a mask step for selectively removing the side wall spacer masks 703 and 704 again.
To 704 can be removed at once. Further, when forming the high impurity density region 62 of the high breakdown voltage n-channel IGFET Q _NH , the sidewall spacer mask 713 is formed on the side wall of the gate electrode 42, and the high impurity density region 66 of the high breakdown voltage p-channel IGFET Q _PH is formed. A side wall spacer mask 714 is formed on the side wall of the gate electrode 43, and the gate electrode 40 of the low breakdown voltage n-channel IGFET Q _NL is formed.
A sidewall spacer mask 711 is formed on the side wall of the gate electrode 41 of the low-breakdown-voltage p-channel IGFET QPL, and a sidewall spacer mask 712 is formed on the side wall of the gate electrode 41 of the low breakdown voltage p-channel IGFET Q _PL. Since the masks 711 to 714 are removed in the same manufacturing process, the sidewall spacers are etched by the entire surface of the semiconductor substrate 30 without requiring a mask process for selectively removing the sidewall spacer masks 711 and 712. Mask 71
1 to 714 can be removed collectively. Therefore,
Since a new mask step is not required, the number of manufacturing steps of the liquid crystal driver device 1 can be reduced.

(Second Embodiment) A second embodiment of the present invention is directed to a method of manufacturing the liquid crystal driver device 1 according to the first embodiment described above, in which the high breakdown voltage IGFET is replaced by a low breakdown voltage IGFET.
This is for explaining an example in which the mask is formed before the GFET and the mask forming step is reduced.

(A) and (B) of FIG. 22 to FIG. 27 and FIG. 28 are process cross-sectional views of a liquid crystal driver device for explaining the manufacturing method according to the second embodiment of the present invention. is there.

(1) Forming an insulating film 45 covering the respective surfaces of the gate electrodes 40 to 43 shown in FIG. 9A in the method of manufacturing the liquid crystal driver device 1 according to the above-described first embodiment of the present invention. After the step (13), as shown in FIG. 22A, the first-layer sidewall spacer mask is formed on the entire surface of the semiconductor substrate 30 on the gate electrodes 40 to 43 (actually, on the insulating film 45). The formation layer 71 is formed. This sidewall spacer mask forming layer 71 has a high withstand voltage.
The length of the n-channel IGFET Q _NH in the channel direction of the low impurity density region 61, that is, the LDD length, and the high breakdown voltage p-channel IGFET Q _PH
Of the low impurity density region 65 in the channel direction, that is,
This is for forming sidewall spacer masks (713 and 714) for determining each of the LDD lengths. In the second embodiment of the present invention, the side wall spacer mask forming layer 71 is formed to have a thickness of 100 nm or more, preferably 350 to 450 nm, formed by low pressure CVD.

(2) Etching corresponding to the thickness of the film formed on the entire surface of the sidewall spacer mask forming layer 71 is performed, and the insulating film 45 is interposed on the side wall of the gate electrode 40 as shown in FIG. A side wall spacer mask 711 is formed in self-alignment with the lever gate electrode 40, and an insulating film 45 is formed on the side wall of the gate electrode 41 in the same manufacturing process.
The sidewall spacer mask 712 is self-aligned with the gate electrode 41, and the sidewall spacer mask 713 is self-aligned with the gate electrode 42 with the insulating film 45 interposed on the side wall of the gate electrode 42.
An insulating film 45 is interposed on the side wall of the gate electrode 43, and side wall spacer masks 714 are formed in self alignment with the gate electrode 43. A highly anisotropic, highly selective CDE can be used for etching. Sidewall spacer mask length L2 (see FIG.
See 1 (B). ) In the second embodiment of the present invention
It is set to 100 nm or more, preferably 350 nm to 450 nm.

(3) The formation region of the high-breakdown-voltage n-channel IGFET Q _NH is opened, and the other formation regions (Q _NL , Q _PL , Q _PH
Are formed (see FIG. 23A). As the mask 910, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high-breakdown-voltage n-channel IGFET Q _NH , the mask 910, the gate electrode 42 and the sidewall spacer mask 713 are used as ion implantation masks, and a high impurity density n-type impurity is added to the main surface of the well region 304. As shown in FIG. 23A, an n ⁺ -type high impurity density region 62 is formed. The high impurity density region 62 is formed near the gate electrode 42 near the channel region separated by the sidewall spacer mask length L2.
Is formed in a self-aligned manner. High impurity density region 62
Are the same as the conditions for forming the high impurity density region 62 according to the above-described first embodiment.

By forming the high impurity density region 62, the length of the low impurity density region 61, that is, the LDD length LD2
(Refer to FIG. 21 (B) described above.)
The DD length LD2 is set to 100 nm or more, preferably about 400 nm to 600 nm. Further, by forming the high impurity density region 62, each of the source region and the drain region including the high impurity density region 62 and the low impurity density region 61 is almost completed, and the high breakdown voltage n-channel IGFET Q _NH can be almost completed. it can.

(4) After removing the mask 910, a mask in which the formation region of the high-breakdown-voltage p-channel IGFET Q _PH is opened and the other formation regions (the formation regions of Q _NL , Q _PL and Q _NH ) are covered 911 are formed (see FIG. 23B). As the mask 911, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high-breakdown-voltage p-channel IGFET Q _PH , the mask 911, the gate electrode 43, and the sidewall spacer mask 714 are used as ion implantation masks, and a high impurity density p-type impurity is As shown in FIG. 23B, a p ⁺ -type high impurity density region 66 is formed. The high impurity density region 66 is formed near the gate electrode 43 near the channel region separated by the sidewall spacer mask length L2.
Is formed in a self-aligned manner. High impurity density region 66
Are the same as those for forming the high impurity density region 66 according to the first embodiment.

By forming the high impurity density region 66, the length of the low impurity density region 65, that is, the LDD length LD2
(Refer to FIG. 21B described above.) The source region and the drain region including the high impurity density region 66 and the low impurity density region 65 are almost completed, and the high breakdown voltage p-channel IGFET Q _PH Can be almost completed.

(5) After removing the mask 911, for example, high-selection CDE is performed on the entire surface of the semiconductor substrate 30, and FIG.
As shown in FIG. 2A, all the sidewall spacer masks 711 to 714 are removed at one time in the same manufacturing process.

(6) As shown in FIG. 24B, the second side wall spacer mask forming layer 70 is formed on the entire surface of the semiconductor substrate 30 on the gate electrodes 40 to 43 (actually on the insulating film 45). To form This sidewall spacer mask forming layer 70 is formed of a low withstand voltage n-channel IGFET Q _NL
Of the low impurity density region 51 in the channel direction, that is,
LDD length, sidewall spacer mask (701 and 7) that determines the length of the low impurity density region 55 of the low breakdown voltage p-channel IGFET Q _PL in the channel direction, that is, the LDD length.
02). In the second embodiment of the present invention, the side wall spacer mask forming layer 70 is formed to a thickness of 100 nm or less, preferably 45 nm to 55 nm, formed by low pressure CVD. In the manufacturing method of the liquid crystal driver device 1 according to a second embodiment of the present invention, the low impurity density regions 51 of the low-voltage n-channel IGFETQ _NL, respective low impurity density regions 55 of the low voltage p-channel IGFETQ _PL Before the formation, a sidewall spacer mask forming layer 70 is formed.

(7) Etching corresponding to the thickness of the film formed on the entire surface of the sidewall spacer mask forming layer 70 is performed, and the insulating film 45 is interposed on the side wall of the gate electrode 40 as shown in FIG. A sidewall spacer mask 701 is formed in self-alignment with the lever electrode 40, and the insulating film 45 is formed on the side wall of the gate electrode 41 in the same manufacturing process.
The sidewall spacer mask 702 is self-aligned with the gate electrode 41, and the sidewall spacer mask 703 is self-aligned with the gate electrode 42 with the insulating film 45 interposed on the side wall of the gate electrode 42.
An insulating film 45 is interposed between the side walls of the gate electrode 43, and side wall spacer masks 704 are formed in self alignment with the gate electrode 43. A highly anisotropic, highly selective CDE can be used for etching. Sidewall spacer mask length L1 (see FIG.
See 1 (A). ) In the second embodiment of the present invention
It is set to 100 nm or less, preferably 45 nm to 55 nm.

(8) The formation region of the low-breakdown-voltage n-channel IGFET Q _NL is opened, and the other formation regions (Q _PL , Q _NH , Q _PH
Is formed (see FIG. 25B). As the mask 912, for example, a photoresist mask formed by a photolithography technique is used.

[0163] Subsequently, in the formation region of the low-breakdown-voltage n-channel IGFETQ _NL, mask 912, using the gate electrode 40 and the sidewall spacer mask 701 as an ion implantation mask, the main surface portion of the n-type impurity of high impurity concentration well region 303 To form an n ⁺ -type high impurity density region 53 as shown in FIG. The high impurity density region 53 has a sidewall spacer mask length L1 of the channel region (see FIG. 21A).
It is formed in a self-aligned manner with the gate electrode 40 in the vicinity of the separation. The condition for forming the high impurity density region 53 is the first condition described above.
This is the same as the condition for forming the high impurity density region 53 according to the embodiment.

(9) Subsequently, using the mask 912 as an etching mask, only the sidewall spacer mask 701 is selectively removed (see FIG. 26A). For the removal of the sidewall spacer mask 701, for example, a high selective CDE can be used.

[0165] Subsequently, in the formation region of the low-breakdown-voltage n-channel IGFETQ _NL, using a mask 912 and the gate electrode 40 as an ion implantation mask, a p-type impurity of high impurity concentration than the well region 303 in the main surface portion of the well region 303 By the introduction, a p-type semiconductor region (p pocket region) 51 is formed as shown in FIG. The semiconductor region 51 is formed in self-alignment with the gate electrode 40 only in the vicinity of the gate electrode 40 in contact with the channel region. The conditions for forming the semiconductor region 51 are the same as the conditions for forming the semiconductor region 51 according to the above-described first embodiment.

(10) Subsequently, a low breakdown voltage n-channel IGFET
In the formation region of Q _NL , the mask 912 and the gate electrode 40 are used as ion implantation masks, and a low impurity density
By introducing an n-type impurity into the main surface of the well region 303, an n-type low impurity density region 52 is formed as shown in FIG. This low impurity density region 52 is formed in self-alignment with the gate electrode 40 in contact with the channel region (in the second embodiment of the present invention, with the semiconductor region 51 interposed in the channel region). The conditions for forming the low impurity density region 52 are the same as the conditions for forming the low impurity density region 52 according to the above-described first embodiment.

By forming the low impurity density region 52 and the high impurity density region 53, the length of the low impurity density region 52, that is, the LDD length LD1 (see FIG. 21A).
Is effectively determined, and the LDD length LD1 is set to 100 nm or less, preferably about 70 nm to 90 nm. Further, each of the source region and the drain region including the high impurity density region 53 and the low impurity density region 52 is almost completed,
an n-channel IGFETQ _NL can be almost completed.

(11) After removing the mask 912, a mask in which the formation region of the low-breakdown-voltage p-channel IGFET Q _PL is opened and the other formation regions (the formation regions of Q _NL , Q _NH and Q _PH ) are covered 913 is formed (see FIG. 27A). As the mask 913, for example, a photoresist mask formed by a photolithography technique is used.

[0169] Subsequently, in the forming region of the low withstand voltage p-channel IGFETQ _PL, mask 913, using the gate electrode 41 and the sidewall spacer mask 702 as an ion implantation mask, the main surface portion of the well region 301 to p-type impurity of high impurity concentration , A p ⁺ -type high impurity density region 56 is formed as shown in FIG. The high impurity density region 56 has a sidewall spacer mask length L1 of the channel region (see FIG. 21A).
It is formed in a self-aligned manner with the gate electrode 41 in the vicinity of the separation. The condition for forming the high impurity density region 56 is the first condition described above.
This is the same as the condition for forming the high impurity density region 56 according to the embodiment.

(12) Subsequently, using the mask 913 as an etching mask, only the side wall spacer mask 702 is selectively removed (see FIG. 27B). For the removal of the sidewall spacer mask 702, for example, a highly selective CDE can be used.

[0171] Subsequently, in the forming region of the low withstand voltage p-channel IGFETQ _PL, by using the mask 913 and the gate electrode 41 as an ion implantation mask, an p-type impurity of low impurity concentration in the main surface portion of the well region 301,
As shown in FIG. 27B, the p-type low impurity density region 55
To form This low impurity density region 55 is formed in self-alignment with the gate electrode 41 in contact with the channel region. The conditions for forming the low impurity density region 55 are the same as the conditions for forming the low impurity density region 55 according to the above-described first embodiment.

By forming the low-impurity-density regions 55 and the high-impurity-density regions 56, the length of the low-impurity-density regions 55, ie, the LDD length LD1 (see FIG. 21A) is effectively determined. Further high impurity density region 5
6 and the low-impurity-density region 55, the source region and the drain region are almost completed.
ETQ _PL can be almost completed.

(13) After removing the mask 913, the formation region of the high-breakdown-voltage n-channel IGFET Q _{NH and} the formation region of the high-breakdown-voltage p-channel IGFET Q _PH are opened,
IGFETQ forming region and a low-voltage p-channel IGFETQ _PL forming region of _NL to form a mask 914 which is covered (see FIG. 28.). Then, as shown in FIG. 28, an unnecessary sidewall spacer mask 703 is
And 704 are removed.

(14) Next, the activation annealing shown in FIG. 16A of the method for manufacturing the liquid crystal driver device 1 according to the first embodiment is performed to activate each source region and drain region. The low breakdown voltage n-channel I
Each of the GFET Q _NL , the low-breakdown-voltage p-channel IGFET Q _PL , the high-breakdown-voltage n-channel IGFET Q _NH , and the high-breakdown-voltage p-channel IGFET Q _PH can be substantially completed.

(15) Thereafter, FIG. 16B of the method of manufacturing the liquid crystal driver device 1 according to the first embodiment described above.
By sequentially performing the steps shown in (1) and (2), the liquid crystal driver device 1 according to the second embodiment of the present invention can be completed.

As described above, in the liquid crystal driver device 1 according to the second embodiment of the present invention, the same operation and effect as those of the liquid crystal driver device 1 according to the first embodiment of the present invention can be obtained. Can be.

[0177] Further, the second in the production method of the liquid crystal driver device 1 according to the embodiment, by using one mask 912 low-voltage n-channel IGFETQ _NL of high impurity concentration regions 53 of the present invention, a low impurity Forming a density region 52 and a semiconductor region (p-pocket region) 51, and a sidewall spacer mask 70 on the side wall of the gate electrode 40.
Can be removed 1, further using a single mask 913, the high impurity concentration region 56 of the low-voltage p-channel IGFETQ _PL, to form a respective low impurity density regions 55, and the side walls of the gate electrode 41 Since the sidewall spacer mask 702 can be removed, the number of manufacturing steps can be reduced.

(Third Embodiment) A third embodiment of the present invention is directed to a method of manufacturing the liquid crystal driver device 1 according to the first embodiment, in which the formation of the side wall spacer mask forming layer is performed. This is for explaining an example in which the time is shortened.

(A) and (B) of FIGS. 29 to 34 and FIG. 35 are process cross-sectional views of a liquid crystal driver device for explaining the manufacturing method according to the third embodiment of the present invention. is there.

(1) Insulating film 45 covering the respective surfaces of gate electrodes 40 to 43 shown in FIG. 9A in the method of manufacturing liquid crystal driver device 1 according to the first embodiment of the present invention is formed. (Step (13)), the gate electrode 40
A first-layer sidewall spacer mask forming layer 73 is formed on the entire surface of the semiconductor substrate 30 on the layers 43 to 43 (actually on the insulating film 45) (see FIG. 29A). The sidewall spacer mask forming layer 73, the low-voltage n-channel IGFETQ low channel direction length or LDD length of the impurity density regions 51, the low withstand voltage p-channel IGFETQ the channel direction length of the low impurity concentration region 55 of the _PL in _NL Ie LD
For forming sidewall spacer masks (731 and 732) for determining each of the D lengths,
Further, the low impurity density region 6 of the high breakdown voltage n-channel IGFET Q _NH
Part of the sidewall spacer masks (743 and 744) for determining the length in the channel direction, ie, the LDD length, and the length in the channel direction, ie, the LDD length, of the low impurity density region 65 of the high breakdown voltage p-channel IGFET Q _PH It is for forming. In the third embodiment of the present invention, the low-voltage
Film thickness of 100 nm or less, preferably 45 nm to 55 nm formed by CVD
It is formed with a film thickness of. Note that, in the method of manufacturing the liquid crystal driver device 1 according to the third embodiment of the present invention, similarly to the method of manufacturing the liquid crystal driver device 1 according to the second embodiment, the low withstand voltage n-channel IGFET Q _NL is reduced. impurity density regions 51, sidewall spacer mask forming layer 73 before forming the respective low impurity density regions 55 of the low voltage p-channel IGFETQ _PL is formed.

(2) As shown in FIG. 29A, low breakdown voltage
n-channel IGFETQ _NL region formation and the low withstand voltage p-channel IGF
The formation region of the ETQ _PL is opened and the high breakdown voltage n-channel IGFET Q
A mask 915 covering the _NH formation region and the high breakdown voltage p-channel IGFET Q _PH formation region is formed on the sidewall spacer mask formation layer 73. As the mask 915, for example, a photoresist mask formed by a photolithography technique is used.

(3) The sidewall spacer mask forming layer 73 using the mask 915 as an etching mask
Etching corresponding to the thickness of the film formed in FIG.
As shown in (B), in the formation region of the low-breakdown-voltage n-channel IGFET Q _NL, a sidewall spacer mask 731 is formed by self-alignment with the gate electrode 40 with the insulating film 45 interposed on the side wall of the gate electrode 40. in the manufacturing process the low withstand voltage p-channel IGFETQ _PL the gate electrode 41 is interposed an insulating film 45 on the side walls of the gate electrode 41 in the formation region of the
Side wall spacer mask 73
Form 2 Sidewall spacer mask length L1
(See FIG. 21A described above.) In the third embodiment of the present invention, the thickness is set to 100 nm or less, preferably 45 nm to 55 nm.

(4) The formation region of the low breakdown voltage n-channel IGFET Q _NL is opened, and the other formation regions (Q _PL , Q _NH , Q _PH
Is formed (see FIG. 30A). As the mask 916, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the low-breakdown-voltage n-channel IGFET Q _NL , the mask 916, the gate electrode 40 and the sidewall spacer mask 731 are used as ion implantation masks, and an n-type impurity having a high impurity density is applied to the main surface of the well region 303. Then, an n ⁺ -type high impurity density region 53 is formed as shown in FIG. The high impurity density region 53 has a sidewall spacer mask length L1 of the channel region (see FIG. 21A).
It is formed in a self-aligned manner with respect to the gate electrode 40 in the vicinity of the separation. The condition for forming the high impurity density region 53 is the first condition described above.
This is the same as the condition for forming the high impurity density region 53 according to the embodiment.

(5) Subsequently, using the mask 916 as an etching mask, only the sidewall spacer mask 731 is selectively removed as shown in FIG. For the removal of the sidewall spacer mask 731, for example, a highly selective CDE can be used.

(6) Subsequently, the low breakdown voltage n-channel IGFET Q
_{In the NL} formation region, the mask 916 and the gate electrode 4
0 as an ion implantation mask and the well region 303
By introducing a p-type impurity having a higher impurity density into the main surface of the well region 303, a p-type semiconductor region (p pocket region) 51 is formed as shown in FIG. This semiconductor region 51 is in contact with the channel region
It is formed in self-alignment with the gate electrode 40 only in the vicinity of 0. The conditions for forming the semiconductor region 51 are the same as the conditions for forming the semiconductor region 51 according to the above-described first embodiment.

(7) Subsequently, the low-breakdown-voltage n-channel IGFET Q
_{In the NL} formation region, the mask 916 and the gate electrode 4
0 is used as an ion implantation mask and n of low impurity density is used.
By introducing the type impurity into the main surface of the well region 303, an n-type low impurity density region 52 is formed as shown in FIG. This low impurity density region 52 is formed in self-alignment with the gate electrode 40 in contact with the channel region (with the semiconductor region 51 interposed in the channel region in the third embodiment of the present invention). The conditions for forming the low impurity density region 52 are the same as the conditions for forming the low impurity density region 52 according to the above-described first embodiment.

By forming the low impurity density region 52 and the high impurity density region 53, the length of the low impurity density region 52, that is, the LDD length LD1 (see FIG. 21A).
Is effectively determined, and the LDD length LD1 is set to 100 nm or less, preferably about 70 nm to 90 nm. Further, each of the source region and the drain region including the high impurity density region 53 and the low impurity density region 52 is almost completed,
an n-channel IGFETQ _NL can be almost completed.

(8) After removing the mask 916, a mask in which the formation region of the low-breakdown-voltage p-channel IGFET Q _PL is opened and the other formation regions (the formation regions of Q _NL , Q _NH , and Q _PH ) are covered 917 is formed (see FIG. 32A). As the mask 917, for example, a photoresist mask formed by a photolithography technique is used.

[0190] Subsequently, in the forming region of the low withstand voltage p-channel IGFETQ _PL, mask 917, using the gate electrode 41 and the sidewall spacer mask 732 as an ion implantation mask, the main surface portion of the well region 301 to p-type impurity of high impurity concentration , A p ⁺ -type high impurity density region 56 is formed as shown in FIG. The high impurity density region 56 has a sidewall spacer mask length L1 of the channel region (see FIG. 21A).
It is formed in a self-aligned manner with the gate electrode 41 in the vicinity of the separation. The condition for forming the high impurity density region 56 is the first condition described above.
This is the same as the condition for forming the high impurity density region 56 according to the embodiment.

(9) Subsequently, using the mask 917 as an etching mask, only the side wall spacer mask 732 is selectively removed (see FIG. 32B). For the removal of the sidewall spacer mask 732, for example, a highly selective CDE can be used.

[0192] Subsequently, in the forming region of the low withstand voltage p-channel IGFETQ _PL, by using the mask 917 and the gate electrode 41 as an ion implantation mask, an p-type impurity of low impurity concentration in the main surface portion of the well region 301,
As shown in FIG. 32B, the p-type low impurity density region 55
To form This low impurity density region 55 is formed in self-alignment with the gate electrode 41 in contact with the channel region. The conditions for forming the low impurity density region 55 are the same as the conditions for forming the low impurity density region 55 according to the above-described first embodiment.

By forming the low-impurity-density regions 55 and the high-impurity-density regions 56, the length of the low-impurity-density regions 55, ie, the LDD length LD1 (see FIG. 21A) is effectively determined. Further high impurity density region 5
6 and the low-impurity-density region 55, the source region and the drain region are almost completed.
ETQ _PL can be almost completed.

(10) The mask 917 is removed, and FIG.
As shown in (A), the gate electrodes 40 and 41 (actually on the insulating film 45), the high-breakdown-voltage n-channel IGFET Q _NH formation region, and the high-breakdown-voltage p-channel IGFET Q _PH formation region are left, respectively. A second layer is formed on the entire surface of the semiconductor substrate 30 on the first-layer sidewall spacer mask forming layer 73.
A sidewall spacer mask forming layer 74 of the layer is formed. This sidewall spacer mask forming layer 74
Is the low impurity density region 61 of the high breakdown voltage n-channel IGFET Q _NH
Length in the channel direction, ie LDD length, high breakdown voltage p-channel
This is for forming sidewall spacer masks (743 and 744) for determining the length of the low impurity density region 65 of the IGFET Q _PH in the channel direction, that is, the LDD length. Sidewall spacer mask forming layer 74
In the third embodiment of the present invention, is formed with a thickness of 100 nm or more, preferably 300 nm to 400 nm, formed by low pressure CVD. The side wall spacer mask forming layer 74 can have a sufficient film thickness by using the first side wall spacer mask forming layer 73 and adding it to the upper layer, so that the formed film thickness is reduced. can do.

(11) Etching corresponding to the film thickness formed on the entire surface of the sidewall spacer mask forming layer 74 and the film thickness of the sidewall spacer mask forming layer 73 is performed, as shown in FIG. In particular, the gate electrode 42
The side wall spacer mask 743 is self-aligned with the gate electrode 42 with the insulating film 45
Is formed, and an insulating film 45 is interposed on the side wall of the gate electrode 43 in the same manufacturing process to form a sidewall spacer mask 744 by self-alignment with the gate electrode 43. Note that a sidewall spacer mask 741 is formed on the side wall of the gate electrode 40, and a sidewall spacer mask 742 is formed on the side wall of the gate electrode 41. A highly anisotropic, highly selective CDE can be used for etching. Sidewall spacer mask 74
The length L2 of each of the side wall spacers 3 and 744 (see FIG. 21B) is 100 nm or more in the third embodiment of the present invention, preferably 350 nm to 450 nm.
is set to m.

(12) The formation region of the high-breakdown-voltage n-channel IGFET Q _NH is opened, and the other formation regions (Q _NL , Q _PL , Q
A mask 918 covering the _PH formation regions is formed (see FIG. 34A). As the mask 918, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high-breakdown-voltage n-channel IGFET Q _NH , the mask 918, the gate electrode 42, and the sidewall spacer mask 743 are used as ion implantation masks, and an n-type impurity having a high impurity density is applied to the main surface of the well region 304. Then, an n ⁺ -type high impurity density region 62 is formed as shown in FIG. The high impurity density region 62 is formed near the gate electrode 42 near the channel region separated by the sidewall spacer mask length L2.
Is formed in a self-aligned manner. High impurity density region 62
Are the same as the conditions for forming the high impurity density region 62 according to the above-described first embodiment.

By forming the high impurity density region 62, the length of the low impurity density region 61, that is, the LDD length LD2
(Refer to FIG. 21 (B) described above.)
The DD length LD2 is set to 100 nm or more, preferably about 400 nm to 600 nm. Further, by forming the high impurity density region 62, each of the source region and the drain region including the high impurity density region 62 and the low impurity density region 61 is almost completed, and the high breakdown voltage n-channel IGFET Q _NH can be almost completed. it can.

(13) After removing the mask 918, the mask in which the formation region of the high-breakdown-voltage p-channel IGFET Q _PH is opened and the other formation regions (the formation regions of Q _NL , Q _PL , and Q _NH ) are covered 919 is formed (see FIG. 34B). As the mask 919, for example, a photoresist mask formed by a photolithography technique is used.

Subsequently, in the formation region of the high-breakdown-voltage p-channel IGFET Q _PH , the mask 919, the gate electrode 43, and the sidewall spacer mask 744 are used as ion implantation masks, and a high impurity density p-type impurity is added to the main surface of the well region 302. , A p ⁺ -type high impurity density region 66 is formed as shown in FIG. The high impurity density region 66 is formed near the gate electrode 43 near the channel region separated by the sidewall spacer mask length L2.
Is formed in a self-aligned manner. High impurity density region 66
Are the same as those for forming the high impurity density region 66 according to the first embodiment.

By forming the high impurity density region 66, the length of the low impurity density region 65, that is, the LDD length LD2
(Refer to FIG. 21B described above.) The source region and the drain region including the high impurity density region 66 and the low impurity density region 65 are almost completed, and the high breakdown voltage p-channel IGFET Q _PH Can be almost completed.

(14) After removing the mask 919, for example, high-selection CDE is performed on the entire surface of the semiconductor substrate 30, and as shown in FIG.
41 to 744 are removed at one time in the same manufacturing process.

(15) Next, the activation annealing shown in FIG. 16A of the method for manufacturing the liquid crystal driver device 1 according to the first embodiment is performed to activate each source region and drain region. The low breakdown voltage n-channel I
Each of the GFET Q _NL , the low-breakdown-voltage p-channel IGFET Q _PL , the high-breakdown-voltage n-channel IGFET Q _NH , and the high-breakdown-voltage p-channel IGFET Q _PH can be substantially completed.

(16) Thereafter, FIG. 16B of the method of manufacturing the liquid crystal driver device 1 according to the first embodiment described above.
The liquid crystal driver device 1 according to the third embodiment of the present invention can be completed by sequentially performing the steps shown in FIG.

As described above, in the liquid crystal driver 1 according to the third embodiment of the present invention, the same operation and effect as those of the liquid crystal driver 1 according to the first embodiment of the present invention are obtained. Can be.

Further, in the method for manufacturing the liquid crystal driver device 1 according to the third embodiment of the present invention, the low withstand voltage n
High impurity density regions 53 of the channels IGFETQ _NL, the low voltage p-channel IGFETQ first layer for forming a high-impurity density regions 56 of the _PL sidewall spacer mask forming layer 7
3 on the high withstand voltage n-channel IGFET Q _NH formation region and high withstand voltage
High breakdown voltage is left on the p-channel IGFET Q _PH formation region
Side wall spacer mask 743 for forming high impurity density region 62 of n-channel IGFET Q _NH and high breakdown voltage
a second side wall spacer mask forming layer 74 for stacking with a side wall spacer mask forming layer 73 which has left a side wall spacer mask 744 for forming the high impurity density region 66 of the p-channel IGFET Q _PH ; Therefore, the film thickness of the second-layer sidewall spacer mask forming layer 74 can be reduced, and the liquid crystal driver device 1 has an amount corresponding to the decrease in the film thickness. Manufacturing time can be reduced.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where the present invention is applied to the liquid crystal driver device has been described. However, the present invention can be widely applied to a semiconductor device in which a low-breakdown-voltage IGFET and a high-breakdown-voltage IGFET are mixed on the same substrate. .

[0208]

The present invention firstly reduces the variation in the amount of main current by making the LDD lengths (lengths of low impurity density regions) of a plurality of types of IGFETs formed on the same substrate uniform. And a semiconductor device with improved electrical characteristics can be provided. In particular, the present invention provides a liquid crystal driver device (or a semiconductor device) that can reduce variations in offset voltage of a differential amplifier circuit, prevent poor image quality of a liquid crystal display unit, and improve the performance of a liquid crystal display device. be able to. Further, it is possible to provide a liquid crystal driver device (or a semiconductor device) which does not need to mount an offset voltage correction circuit and can improve the degree of integration.

[0209] Second, the present invention can provide a liquid crystal display device capable of reducing the variation in the offset voltage of the differential amplifier circuit and improving the image quality of the liquid crystal display unit.

Third, the present invention can realize a high-performance liquid crystal display device having a liquid crystal driver device that does not require the mounting of an offset voltage correction circuit. As a result, it is possible to provide a personal computer that can reduce the power consumption of the liquid crystal driver device and extend the driving time.

Fourth, the present invention can eliminate variations in the LDD length (length of the low impurity density region) due to manufacturing misalignment in each of a plurality of types of IGFETs mounted on the same substrate, It is possible to provide a method for manufacturing a semiconductor device capable of making the LDD length uniform.

Fifth, the present invention provides, in addition to the fourth effect of the present invention, a low breakdown voltage IGFET having an LDD structure and a high breakdown voltage IGFET having an LDD structure.
In each of the GFETs, it is possible to provide a method of manufacturing a semiconductor device that can achieve optimization. In particular, the present invention can provide a method of manufacturing a semiconductor device that does not adversely affect the characteristics of a low-breakdown-voltage IGFET having an LDD structure when manufacturing a high-breakdown-voltage IGFET having an LDD structure.

Sixth, the present invention can provide a method of manufacturing a semiconductor device capable of reducing the number of manufacturing steps in addition to the fourth effect of the present invention. In particular, the present invention can provide a method of manufacturing a semiconductor device in which the number of manufacturing steps can be reduced by reducing the number of steps for removing the sidewall spacer mask.

Seventh, the present invention provides, in addition to the fourth effect of the present invention, a semiconductor in which the number of masks for forming impurity density regions can be reduced and the number of manufacturing steps can be reduced. A method for manufacturing the device can be provided.

Eighthly, in addition to the fourth effect of the present invention, the present invention provides a semiconductor device which can shorten the film formation time of the side wall spacer mask forming layer and can reduce the manufacturing time. A manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional structural view of a main part of a liquid crystal driver device (a semiconductor device for a liquid crystal driver) according to a first embodiment of the present invention.

FIG. 2A is a plan layout view of a liquid crystal driver device according to a first embodiment of the present invention, and FIG. 2B is a driver mounted on the liquid crystal driver device according to the first embodiment of the present invention; It is a block circuit diagram of a circuit unit.

FIG. 3 is a circuit diagram of a differential amplifier circuit of the liquid crystal driver device and a liquid crystal display unit of the liquid crystal display device according to the first embodiment of the present invention.

FIGS. 4A and 4B are process cross-sectional views for explaining a method of manufacturing the liquid crystal driver device according to the first embodiment of the present invention (part 1).

FIGS. 5A and 5B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 2).

FIGS. 6A and 6B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 3).

FIGS. 7A and 7B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 4).

FIGS. 8A and 8B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 5).

FIGS. 9A and 9B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 6).

FIGS. 10A and 10B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 7).

FIGS. 11A and 11B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 8).

FIGS. 12A and 12B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 9).

13A and 13B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 10).

FIGS. 14A and 14B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 11).

FIGS. 15A and 15B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 12).

16A and 16B are process cross-sectional views of the liquid crystal driver device according to the first embodiment of the present invention (part 13).

FIG. 17 is a process sectional view of the liquid crystal driver device according to the first embodiment of the present invention (part 14).

FIG. 18 is a process sectional view of the liquid crystal driver device according to the first embodiment of the present invention (part 15).

FIG. 19 is a process sectional view of the liquid crystal driver device according to the first embodiment of the present invention (part 16).

FIG. 20 is a process sectional view of the liquid crystal driver device according to the first embodiment of the present invention (part 17).

FIG. 21A is a cross-sectional view of a main part of a liquid crystal driver device according to a first embodiment of the present invention in the process of manufacturing a low-breakdown-voltage IGFET, and FIG. 21B is a sectional view of the first embodiment of the present invention; FIG. 8 is a cross-sectional structural view of a main part of the liquid crystal driver device during manufacture of the high breakdown voltage IGFET.

FIGS. 22A and 22B are process cross-sectional views for explaining a method of manufacturing a liquid crystal driver device according to the second embodiment of the present invention (part 1).

FIGS. 23A and 23B are process cross-sectional views of a liquid crystal driver device according to a second embodiment of the present invention (part 2).

FIGS. 24A and 24B are process cross-sectional views of a liquid crystal driver device according to a second embodiment of the present invention (part 3).

FIGS. 25A and 25B are process cross-sectional views of the liquid crystal driver device according to the second embodiment of the present invention (part 4).

FIGS. 26A and 26B are process cross-sectional views of the liquid crystal driver device according to the second embodiment of the present invention (part 5).

FIGS. 27A and 27B are process cross-sectional views of the liquid crystal driver device according to the second embodiment of the present invention (part 6).

FIG. 28 is a process sectional view of the liquid crystal driver device according to the second embodiment of the present invention (part 7).

FIGS. 29A and 29B are process cross-sectional views for explaining a method of manufacturing the liquid crystal driver device according to the third embodiment of the present invention (part 1).

FIGS. 30A and 30B are process cross-sectional views of the liquid crystal driver device according to the third embodiment of the present invention (part 2).

FIGS. 31A and 31B are process cross-sectional views of a liquid crystal driver device according to the third embodiment of the present invention (part 3).

FIGS. 32A and 32B are process cross-sectional views of the liquid crystal driver device according to the third embodiment of the present invention (part 4).

FIGS. 33A and 33B are process cross-sectional views of the liquid crystal driver device according to the third embodiment of the present invention (part 5).

FIGS. 34A and 34B are process cross-sectional views of a liquid crystal driver device according to the third embodiment of the present invention (part 6).

FIG. 35 is a process sectional view of the liquid crystal driver device according to the third embodiment of the present invention (part 7).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Liquid crystal driver device 2 Liquid crystal display part 10 Output pad area 11 Input pad area 12 Main decoder area 13 Driver circuit unit array 20 Pixel 21 Vertical scanning line 22 Video signal line 30 Semiconductor substrate 301-304 Well area 35-38 Gate insulating film 40 -43 gate electrode 52,55,61,65 low impurity density region 53,56,62,66 high impurity density region 51 semiconductor region 77,81 wiring 701-704,711-714,731-734,7
41 to 744 Sidewall spacer mask 70 to 74 Sidewall spacer mask formation layer 130 Driver circuit unit 131 Differential amplifier circuit 132 Decoder circuit Q _NL Low voltage n-channel IGFET Q _PL Low voltage p-channel IGFET Q _NH High voltage n-channel IGFET Q _PH high voltage p-channel IGFET Q _NL1 , Q _PL2 p-channel IGFET for bias Q _NL1 output n-channel IGFET, Q _PH1 , Q _PH2 p-channel IGFET for differential input Q _NH1 , Q _NH2 n-channel IGFET for active load Q _TFT thin film transistor LCD Liquid crystal display

Continued on the front page F term (reference) 2H089 QA11 QA16 TA07 5F048 AA00 AA01 AA09 AB07 AB10 AC03 AC06 AC10 BA01 BB05 BB08 BB11 BB12 BC05 BC06 BC07 BC19 BC20 BD04 BD10 BE03 BF02 BF07 BF12 BG12 BH07 DA17 DA17 FA06 HA29 KA33 KA67 MA21 ND01 ND14 ND22 ND23 PD01 QA02 SA08

Claims (8)

[Claims] A first high impurity density region formed near a first channel region in a self-alignment manner with a first gate electrode on the first channel region; and at least the first channel Low breakdown voltage insulation including a first main electrode region having a first low impurity density region formed in a self-aligned manner with respect to the first gate electrode between a region and a first high impurity density region An output-stage transistor formed of a gate-type field-effect transistor; and a second gate on the second channel region near a second channel region formed on the same substrate as the output-stage transistor. A second self-aligned electrode
A high impurity density region and at least between the second channel region and the second high impurity density region in a self-aligned manner with respect to the second gate electrode. And a differential amplifier transistor and an active load transistor on the input stage side, each of which is formed of a high-breakdown-voltage insulated gate field effect transistor having a second main electrode region having a second low impurity density region that is long in the channel length direction. A semiconductor device comprising a differential amplifier circuit comprising: 2. The semiconductor device according to claim 1, wherein the differential amplifier circuit forms a driver circuit unit that drives a video signal line of a liquid crystal display unit of the liquid crystal display device. 3. A first high impurity density region formed near the first channel region in a self-aligned manner with respect to a first gate electrode on the first channel region, and at least the first channel. An output stage transistor including a first main electrode region having a first low impurity density region formed in a self-aligned manner with respect to the first gate electrode between a region and a first high impurity density region A second high impurity density region formed near the second channel region in a self-alignment with a second gate electrode on the second channel region; A second low-impurity-density region formed in self-alignment with the second gate electrode between the second low-impurity-density region and a second low-impurity-density region longer in the channel length direction than the first low-impurity-density region; 2
A differential amplifier circuit having an input stage differential amplifier transistor and an active load transistor having a main electrode region of the following, a liquid crystal driver device including a driver circuit unit having the differential amplifier circuit, and the liquid crystal driver device And a liquid crystal display having a video signal line driven by the driver circuit unit. 4. A method for manufacturing a semiconductor device, comprising at least the following steps (1) to (3). (1) A first channel region is formed in a first region of a substrate, and a second channel region is formed in a second region different from the first region of the substrate.
(2) forming a first gate electrode on the first channel region via a first gate insulating film, and forming a second gate insulating film on the second channel region; Forming a second gate electrode through the first step (3) a first low impurity density region formed in self contact with the first gate electrode in contact with the first channel region in the first region A first sidewall spacer mask formed in self-alignment with the first gate electrode on a side wall of the first gate electrode, and a first low impurity density region interposed in the first channel region. The first
Forming a first insulated gate field effect transistor having a first high impurity density region formed in a self-aligned manner with respect to the side wall spacer mask, and contacting the second channel region in the second region. A second low-impurity-density region formed in self-alignment with the second gate electrode; and a first side formed in self-alignment with the second gate electrode on a side wall of the second gate electrode. A second sidewall spacer mask that is longer than the wall spacer mask length, and is formed in self-alignment with the second sidewall spacer mask with a second low impurity density region interposed in the second channel region. Forming second insulated gate field effect transistor having second doped region with high impurity density 5. A method for manufacturing a semiconductor device, comprising at least the following steps (1) to (8). (1) A first channel region is formed in a first region of a substrate, and a second channel region is formed in a second region different from the first region of the substrate.
(2) forming a first gate electrode on the first channel region via a first gate insulating film, and forming a second gate insulating film on the second channel region; (3) forming a first low-impurity-density region in self-alignment with the first gate electrode in contact with the first channel region in the first region; Forming a second low impurity density region in self contact with the second gate electrode in contact with a second channel region in the second region. (4) forming a second low impurity density region on a side wall of the first gate electrode; Step of forming a first sidewall spacer mask in a self-alignment manner with respect to one gate electrode (5) In the first region, a first sidewall spacer mask is used as the first sidewall spacer mask. for Forming a first high-impurity-density region by interposing a first low-impurity-density region in the first channel region by self-alignment to form a first insulated-gate field-effect transistor; Step of removing the first sidewall spacer mask (7) The second sidewall spacer mask is self-aligned with the second gate electrode on the side wall of the second gate electrode and is longer in the channel length direction than the first sidewall spacer mask. Forming a sidewall spacer mask of (8) using a second sidewall spacer mask in the second region, and forming a second sidewall spacer mask in the second channel region in self-alignment with the second sidewall spacer mask. Forming a second high-impurity-density region with the second low-impurity-density region therebetween to form a second insulated-gate field-effect transistor 6. A method for manufacturing a semiconductor device, comprising at least the following steps (1) to (9). (1) A first channel region is formed in a first region of a substrate, and a second channel region is formed in a second region different from the first region of the substrate.
(2) forming a first gate electrode on the first channel region via a first gate insulating film, and forming a second gate insulating film on the second channel region; (3) forming a first low-impurity-density region in self-alignment with the first gate electrode in contact with the first channel region in the first region; Forming a second low impurity density region in self contact with the second gate electrode in contact with a second channel region in the second region. (4) forming a second low impurity density region on a side wall of the first gate electrode; Forming a first sidewall spacer mask in self-alignment with the first gate electrode, and forming the first sidewall spacer on the side wall of the second gate electrode in the same manufacturing process by self-alignment with the second gate electrode; Form a spacer mask Step (5): In the first region, a first sidewall spacer mask is used, and a first low impurity density region is formed in the first channel region by self-alignment with the first sidewall spacer mask. Forming a first high-impurity-density region with the interposition therebetween to form a first insulated-gate field-effect transistor; (6) forming a first insulated gate field-effect transistor on each of the side walls of the first gate electrode and the second gate electrode; Removing the first sidewall spacer mask in the same manufacturing process. (7) The side wall of the second gate electrode is self-aligned with the second gate electrode in the channel length direction more than the first sidewall spacer mask. A second sidewall spacer mask is formed to be longer than the first gate electrode, and is formed on the side wall of the first gate electrode in the same manufacturing process in a self-aligned manner with respect to the first gate electrode. Step of forming a wall spacer mask (8) A second sidewall spacer mask is used in the second region, and a second sidewall spacer mask is self-aligned with the second sidewall spacer mask in the second channel region. Forming a second high-impurity-density region with the low-impurity-density region interposed therebetween to form a second insulated-gate field-effect transistor; (9) sidewalls of the second gate electrode and a first gate electrode Removing the second sidewall spacer mask of each side wall in the same manufacturing process; 7. A method for manufacturing a semiconductor device, comprising at least the following steps (1) to (7). (1) A first channel region is formed in a first region of a substrate, and a second channel region is formed in a second region different from the first region of the substrate.
(2) forming a first gate electrode on the first channel region via a first gate insulating film, and forming a second gate insulating film on the second channel region; (3) forming a sidewall spacer mask on the side wall of the first gate electrode and the side wall of the second gate electrode by the same manufacturing process; Forming a first mask in which a region is opened and a second region is covered. (5) In the first region, a first mask and a sidewall spacer mask are used to form the first channel region. A first high-impurity-density region of the first conductivity type is formed in the vicinity by self-alignment with the sidewall spacer mask, and thereafter, using the first mask, the sidewall spacer on the side wall of the first gate electrode is formed. The mask is removed, and then a first low impurity density region of the first conductivity type is self-aligned with the first gate electrode between at least the first channel region and the first high impurity density region. Forming and forming a first insulated gate field effect transistor (6) removing the first mask to form a second mask in which the second region is opened and the first region is covered (7) using a second mask and a sidewall spacer mask in the second region, and forming a first conductive type in the vicinity of the second channel region by self-alignment with the sidewall spacer mask. Forms a second high-impurity-density region of the second conductivity type of the opposite conductivity type, and thereafter uses the second mask to remove the sidewall spacer mask on the side wall of the second gate electrode; At least the second Forming a second low impurity density region of a second conductivity type between the channel region and the second high impurity density region in self-alignment with the second gate electrode; Step of forming transistor 8. A method for manufacturing a semiconductor device, comprising at least the following steps (1) to (7). (1) A first channel region is formed in a first region of a substrate, and a second channel region is formed in a second region different from the first region of the substrate.
(2) forming a first gate electrode on the first channel region via a first gate insulating film, and forming a second gate insulating film on the second channel region; (3) forming a first low-impurity-density region in self-alignment with the first gate electrode in contact with the first channel region in the first region; Forming a second low-impurity-density region in self-alignment with a second gate electrode in contact with a second channel region in the second region. (4) On the first region and in the second region Forming a first sidewall spacer mask forming layer on the region, and covering the second region with the first sidewall spacer mask forming layer, forming a first sidewall spacer on the first region; From the mask forming layer, the first Forming a first sidewall spacer mask on the side wall of the gate electrode in a self-aligned manner with respect to the first gate electrode; (5) using the first sidewall spacer mask in the first region; A first high-impurity-density region formed in the first channel region by interposing a first low-impurity-density region in self-alignment with the first sidewall spacer mask; (6) forming a second sidewall spacer mask formation layer on the first sidewall spacer mask formation layer in the second region and on the first region; 1
And from the second sidewall spacer mask forming layer,
Forming a second sidewall spacer mask on the side wall of the second gate electrode in self-alignment with the second gate electrode; (7) using a second sidewall spacer mask in the second region A second high impurity density region is formed in the second channel region with a second low impurity density region interposed therebetween in a self-alignment manner with respect to a second sidewall spacer mask; Step of forming a field effect transistor