JP3025385B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a liquid crystal display panel provided with an n-channel insulated gate field effect transistor (hereinafter referred to as an FET) and a p-channel insulated gate FET, a contact type image sensor, and a three-dimensional IC. Related to the device.

[0002]

2. Description of the Related Art A thin film transistor (hereinafter referred to as TFT) is known as the above-mentioned insulated gate FET. One of the basic circuits of a CMOS circuit using a p-channel TFT and an n-channel TFT is a CMOS inverter.

FIG. 6A shows an equivalent circuit of a CMOS inverter, and FIG. 6B shows its transfer characteristics. This C
The threshold voltage VTHC of the MOS inverter is expressed as follows.

[0004]

(Equation 1)

Here, in order to obtain a high-performance CMOS circuit, it is necessary to satisfy the following two conditions.

One of them is to make the high level voltage and the low level voltage of the power supply voltage completely symmetrical and to make the rise time and the fall time equal.

[0007]

(Equation 2)

Is to be set so that

Another is to reduce the power supply voltage.
The purpose is to make the absolute values of both Vthp and Vthn sufficiently small.

In order to satisfy the above two conditions, V
It is necessary to control thp independently of Vthn.

Conventionally, in order to control Vthp independently of Vthn, for example, CHARACTERIZATION OF N-CHANNEL AND P-
CHANNEL LPCVD POLYSILICON MOSFETS H. Shichijo et.a
As shown in I., IEDM 83, p202-p205 (1983), so-called channel doping is performed in which a channel region is doped with an impurity. A method for manufacturing a TFT using this channel doping will be described with reference to FIGS.

First, the Si wafer 101 is thermally oxidized to
An insulating layer 102 made of iO ₂ is formed to a thickness of about 5000 Å. On this, a polycrystalline silicon (p-Si) semiconductor layer 103 is laminated to a thickness of 1500 angstroms by LPCVD (low pressure chemical vapor deposition). Next, boron (B) or arsenic (As) is doped into the channel region 103a through a dummy oxide film having a thickness of 500 angstroms by an ion implantation method. The dose is set to 2 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻² . After removing the dummy oxide film, the semiconductor layer 103 is thermally oxidized to form a gate insulating film 104 having a thickness of 500 Å. Thereafter, a 5000 angstrom thick gate electrode 10 made of phosphorus-doped p-Si is formed.
5 is formed. The source / drain regions 103 are formed in the semiconductor layer 103 by ion implantation using the gate electrode as a mask.
b is formed. Thus, a TFT is manufactured.

[0013]

However, in the p-channel TFT manufactured by the above-mentioned method, as described in the above-mentioned document, the channel doping with a p-type impurity significantly increases the leak current, and Therefore, channel doping is not a practical method because the characteristics of the channel doping are impaired.

Generally, the absolute value of Vthp is considered to be considerably larger than the absolute value of Vthn. This means
For example, Processing and Device Performance of Low-T
emperature CMOS Poly-TFTs on 18.4-in.-Diagonal Sub
strater for AMLCD Application I.-W.Wu et.al., SID
92 DIGEST, p-615-p-618. In this document, Vthn = 3.6V and Vthp = -12.5V. Therefore, it is necessary to reduce the absolute value of Vthp independently of the absolute value of Vthn.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to determine the absolute value of the threshold voltage of a p-channel insulated-gate FET without impairing the characteristics of the n-channel insulated-gate FET. It is an object of the present invention to provide a high-performance semiconductor device which can be reduced independently of the absolute value of the threshold voltage of an FET.

[0016]

According to the present invention, there is provided a semiconductor device comprising:
An n-channel having a first gate insulating film on an insulating substrate
Having a polysilicon gate TFT and a second gate insulating film
C-channel polysilicon TFT
An S inverter, and a unit of the second gate insulating film.
The capacitance per area corresponds to the unit area of the first gate insulating film.
The capacity is set to be larger than the above capacity, thereby achieving the above object.

[0017] The second gate insulating film may be thinner than the first gate insulating film.

At least a part of the second gate insulating film may be made of a material having a higher dielectric constant than the first gate insulating film.

[0019]

The threshold voltage Vth of a TFT is generally expressed by the following equation.

[0020]

(Equation 3)

As can be understood from this equation, one of the methods for reducing the absolute value of Vth is to increase Cox.

In the present invention, Cox of the p-channel insulated gate FET is replaced by C of the n-channel insulated gate FET.
It is larger than ox. p-channel insulated gate type F
The gate insulating film of the ET is made thinner than that of the n-channel insulated gate FET, or the gate insulating film of the p-channel insulated gate FET is changed to the n-channel insulated gate FE.
By forming from a material having a dielectric constant higher than that of T, the Vth of the p-channel insulated gate FET can be controlled independently of the Vth of the n-channel insulated gate FET.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 (g) shows an embodiment of a semiconductor device according to the present invention. This semiconductor device has a p-channel TFT and an n-channel TFT formed on an insulating substrate 1. In a p-channel TFT, a semiconductor layer 2p having a source region / drain region and an active region is formed on an insulating substrate 1, and an insulating film 4 is formed on the semiconductor layer 2p so as to cover almost the entire surface of the substrate. It has become. A gate electrode 8p is formed thereon so as to face the active region, and an interlayer insulating film 10 is formed to cover the gate electrode 8p. Further, a source electrode / drain electrode 12p is formed, and is electrically connected to the source region / drain region via a contact hole 11p formed in the gate insulating film 4 and the interlayer insulating film 10. In the case of an n-channel TFT, the insulating substrate 1
A semiconductor layer 2n having a source region / drain region and an active region is formed thereon. N channel T
An insulating film 3 is formed on the FT portion, and an insulating film 4 is formed so as to cover almost the entire surface of the substrate.
The gate insulating film is made of A gate electrode 8n is formed thereon so as to face the active region, and an interlayer insulating film 10 is formed to cover the gate electrode 8n. Further, a source electrode / drain electrode 12n is formed, and is electrically connected to the source region / drain region via a contact hole 11n formed in the gate insulating film 4 and the interlayer insulating film 10.

The semiconductor device having such a configuration is, for example,
It can be manufactured by the manufacturing steps as shown in FIGS.

First, as shown in FIG. 1A, an 800 .ANG.-thick amorphous silicon (a-Si) film is deposited on an insulating substrate 1 by an LPCVD method, and is subjected to a heat treatment. A p-Si film is used. This is etched to make the semiconductor layers 2p and 2n respectively p-channel TF
It is formed in a T region and an n-channel TFT region. next,
An insulating film 3 made of SiO ₂ having a thickness of 500 Å is formed on almost the entire surface of the substrate under the conditions of source gases SiH ₄ and N ₂ O, a pressure of 50 Pa, and a substrate temperature of 850 ° C. by LPCVD.

Thereafter, as shown in FIG. 1B, only the p-channel TFT region of the insulating film 3 is removed.

Further, as shown in FIG.
According to the VD method, source gases SiH ₄ and N ₂ O, pressure 50
Under the conditions of Pa and a substrate temperature of 850 ° C., an insulating film 4 of 500 angstrom thick SiO _{2 is} formed on almost the entire surface of the substrate.
To form

Next, as shown in FIG. 1D, gate electrodes 8p and 8n made of a Si film doped with phosphorus are formed in a p-channel TFT region and an n-channel TFT region, respectively.

Thereafter, as shown in FIG. 1E, a photoresist 9p is formed on the p-channel TFT. In this state, phosphorus ( ³¹ P ⁺ ) is ion-implanted into the semiconductor layer 2 n under the conditions of an acceleration voltage of 100 keV and an impurity density of 1 × 10 ¹⁵ cm ⁻² to form a source region and a drain region of the n-channel TFT. At this time, impurities are not implanted into the active region of the TFT due to the shielding effect of the gate electrode 8n.

Further, as shown in FIG. 1F, a photoresist 9n is formed on the n-channel TFT. In this state, an acceleration voltage 30keV to the semiconductor layer 2p, boron under the conditions of impurity concentration ^{1 × 10 15 cm -2 (11} B +) and is ion-implanted to form a source region and a drain region of the p-channel TFT. At this time, impurities are not ion-implanted into the active region of the TFT due to the shielding effect of the gate electrode 8p.

Subsequently, an interlayer insulating film 10 of 5000 angstrom thick SiO ₂ is formed by CVD so as to cover the gate electrodes 8p and 8n. The substrate in this state is subjected to a heat treatment at a temperature of 950 ° C. for 30 minutes in an N ₂ atmosphere to inactivate impurities.

Further, as shown in FIG. 1G, predetermined portions of the insulating films 3, 4 and the interlayer insulating film 10 are removed, and contact holes 11p and 11n are respectively formed to reach the source region and the drain region. It is formed in a channel TFT region and an n-channel TFT region. Next, using Al, source and drain electrodes 12p and 12n reaching the source and drain regions are formed in the p-channel TFT region and the n-channel TFT region, respectively.

Through the above steps, a semiconductor device having a p-channel TFT and an n-channel TFT can be obtained.

In this embodiment, a p-channel TFT
Is an insulating film 3 having a thickness of 500 angstroms. The gate insulating film of the n-channel TFT is composed of insulating films 3 and 4, and has a thickness of 1000 Å. Therefore, the gate insulating film of the p-channel TFT is changed to n
It could be formed thinner than the gate insulating film of the channel TFT. For a TFT having a gate length of 5 μm,
Vthp = -3.5V, Vthn = 3.5V, CMOS
In order to improve the performance of the circuit, the absolute value could be made sufficiently small.

Although the insulating films 3 and 4 are formed using SiO ₂ in the above embodiment, they may be formed using Si ₃ N ₄ or Ta ₂ O ₅ .

Embodiment 2 FIG. 2F shows another embodiment of the semiconductor device of the present invention. In this semiconductor device, insulating films 6 and 7 made of SiO ₂ are formed as gate insulating films of an n-channel TFT, and insulating films 3 and 7 made of SiO ₂ and Si ₃ N as a gate insulating film of a p-channel TFT. ₄ , a high dielectric constant insulating film 5 is formed.

The semiconductor device having such a configuration is, for example,
It can be manufactured by the manufacturing steps as shown in FIGS.

First, as shown in FIG. 2A, an 800 .ANG.-thick amorphous silicon (a-Si) film is deposited on the insulating substrate 1 by LPCVD, and is subjected to a heat treatment. A p-Si film is used. This is etched to make the semiconductor layers 2p and 2n respectively p-channel TF
It is formed in a T region and an n-channel TFT region. next,
An insulating film 3 made of SiO ₂ having a thickness of 150 Å is formed on almost the entire surface of the substrate under the conditions of the source gases SiH ₄ and N ₂ O, the pressure of 50 Pa, and the substrate temperature of 850 ° C. by the LPCVD method. Subsequently, a high dielectric constant made of Si ₃ N ₄ having a thickness of 300 angstroms is formed on almost the entire surface of the substrate under the conditions of a source gas SiH ₂ Cl ₂ (dichlorosilane), NH ₃ , a pressure of 50 Pa and a substrate temperature of 850 ° C. by LPCVD. An insulating film 5 is formed.

Thereafter, as shown in FIG. 2B, only the n-channel TFT region of the insulating film 3 and the high dielectric constant insulating film 5 is removed.

Further, as shown in FIG.
According to the VD method, source gases SiH ₄ and N ₂ O, pressure 50
Under the conditions of Pa and a substrate temperature of 850 ° C., an insulating film 6 of 800 angstrom thick SiO _{2 is} formed on almost the entire surface of the substrate.
To form

Thereafter, as shown in FIG. 2D, only the p-channel TFT region of the insulating film 6 is removed. Since the high dielectric constant insulating film 5 made using the Si ₃ N ₄ with dilute HF solution is not etched, SiO p-channel TFT region ₂
Can be etched only.

Next, as shown in FIG.
According to Method D, source gases SiH ₄ and N ₂ O, pressure 50P
a, At a substrate temperature of 850 ° C., an insulating film 7 made of SiO ₂ having a thickness of 200 Å is formed on almost the entire surface of the substrate.

Next, as shown in FIG. 2F, gate electrodes 8p and 8n made of a Si film doped with phosphorus are formed in a p-channel TFT region and an n-channel TFT region, respectively.

Thereafter, the photoresist is replaced with a p-channel TF
Formed in the T portion. In this state, phosphorus ( ³¹ P ⁺ ) is ion-implanted into the semiconductor layer 2 n under the conditions of an acceleration voltage of 100 keV and an impurity density of 1 × 10 ¹⁵ cm ⁻² to form a source region and a drain region of the n-channel TFT. At this time, impurities are not implanted into the active region of the TFT due to the shielding effect of the gate electrode 8n.

Further, the photoresist is replaced with an n-channel TF
Formed in the T portion. In this state, an acceleration voltage 60keV to the semiconductor layer 2p, boron under the conditions of impurity concentration ^{1 × 10 15 cm -2 (11} B +) and is ion-implanted to form a source region and a drain region of the p-channel TFT. At this time, impurities are not ion-implanted into the active region of the TFT due to the shielding effect of the gate electrode 8p.

Subsequently, an interlayer insulating film 10 made of SiO ₂ and having a thickness of 5000 Å is formed by CVD so as to cover the gate electrodes 8p and 8n. The substrate in this state is subjected to a heat treatment at a temperature of 950 ° C. for 30 minutes in an N ₂ atmosphere to inactivate impurities.

Further, predetermined portions of the insulating films 3, 5, 6, 7 and the interlayer insulating film 10 are removed, and the contact holes 11p and 1p are extended to reach the source region and the drain region.
1n are formed in the p-channel TFT region and the n-channel TFT region, respectively. Next, using Al, the source electrode / drain electrode 1 reaching the source region / drain region.
2p and 12n are formed in a p-channel TFT region and an n-channel TFT region, respectively.

Through the above steps, a semiconductor device having a p-channel TFT and an n-channel TFT can be obtained.

In this embodiment, a p-channel TFT
The gate insulating film made of a high dielectric constant insulating film 5 made of an insulating film 3, 7 and Si ₃ N ₄ consisting of SiO _2, SiO ₂
The thickness is 500 Å in conversion. The gate insulating film of the n-channel TFT is made of insulating films 6 and 7 made of SiO ₂ and has a thickness of 1000 Å. The relative dielectric constant ε of SiO ₂ is about 3.9 and that of Si ₃ N
₄ is about 7.8. Therefore, p-channel TFT
Was able to be configured to include a material having a higher ε than the gate insulating film of the n-channel TFT. For a TFT having a gate length of 5 μm, Vthp = −2.
9 V and Vthn = 3.5 V, and the absolute value was sufficiently small to improve the performance of the CMOS circuit.

In the above embodiment, the high dielectric constant insulating film 5 is formed by using Si ₃ N ₄ , but may be formed by using Ta ₂ O ₅ or the like.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications are possible.

For example, a microcrystalline silicon semiconductor layer or an amorphous silicon semiconductor layer can be used other than the semiconductor layer made of p-Si. The configuration of the TFT is not limited to the above, and for example, an inverted staggered TFT as shown in FIGS. 3 and 4 can be used. Further, as long as it is an insulated gate field effect transistor, it can be applied even if it is not a TFT. Further, the present invention can be applied to circuits other than the CMOS circuit.

In the above, the n-channel insulated gate type F
By changing the thickness and material of the gate insulating film of the ET and p-channel insulated gate FETs,
It is possible to independently control th, and to obtain a high-performance semiconductor device by optimizing circuit characteristics.

[0055]

As is apparent from the above description, according to the present invention, it is possible to control the Vth of an n-channel insulated gate FET and a p-channel insulated gate FET independently to reduce their absolute values. Therefore, a high-performance semiconductor device can be obtained. Therefore, a high-resolution liquid crystal display panel, a high-speed and high-resolution contact image sensor, a three-dimensional IC, and the like can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing another embodiment of the semiconductor device of the present invention.

FIG. 4 is a sectional view showing another embodiment of the semiconductor device of the present invention.

FIG. 5 is a sectional view showing a conventional semiconductor device.

FIG. 6 is a diagram illustrating an equivalent circuit and a transfer characteristic of a CMOS inverter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2p, 2n Semiconductor layer 3, 4, 6, 7 Insulating film 5 High dielectric constant insulating film 8p, 8n Gate electrode 9 Photoresist 10p, 10n Interlayer insulating film 11p, 11n Contact hole 12p, 12n Source electrode / drain electrode

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/136 G02F 1/1343 H01L 29/78 H01L 27/08 H01L 27/12

Claims (3)

(57) [Claims] 1. A first gate insulating film is formed on an insulating substrate.
An n-channel polysilicon TFT and a second gate
A p-channel polysilicon TFT having a gate insulating film;
Constitutes a CMOS inverter, and the second gate
The capacitance per unit area of the gate insulating film depends on the first gate insulation.
A semiconductor device having a larger capacity per unit area of the film . Wherein said second gate insulating film, a semiconductor device according to claim 1 which is thinner than the first gate insulating film. Wherein said at least a portion of the second gate insulating film, a semiconductor device according to claim 1 which is a material having a higher dielectric constant than the first gate insulating film.