JP2001095141A - Fusible link unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a fusible link unit with a function which can cope with an incomplete short circuit. SOLUTION: A thermal FET QA is in an on-state for a certain lapse of time after a load is connected. If the state is a complete short circuit state, an FL(fusible link) 1 is fused to protect a circuit. If the state is an incomplete short circuit state, as the FL is not fused in the incomplete short circuit period, the thermal FET QA is repeatedly turned on and off in a certain period and the number of on/off times is accumulated. If the number of on/off times accumulated in the certain period reaches a predetermined number, the thermal FET QA is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fusible link unit for interrupting an overcurrent flowing in an electric circuit.

[0002]

2. Description of the Related Art Conventionally, electric circuits of vehicles such as automobiles include:
A cassette-type large-current fuse called a fusible link (FL) that melts when an overcurrent flows is used. FIG. 4 is a perspective view showing the configuration of the FL. FL1 is a fuse element 2 having terminals 3 attached to both ends thereof, a housing 4 made of an insulating resin for accommodating the fuse element 2, and a housing 4. And a cap 5 for fixing the fuse element 2. This type of FL1 has a fusing characteristic as shown in FIG. FIG. 6 shows an example of a fusible link circuit for a vehicle using FL1, in which power from a battery 10 is supplied to each of a plurality of loads 11 through FL1. Each load 11 is provided with a fuse 12 in series therewith.

[0003]

However, in the above-mentioned conventional FL1, the fuse is immediately blown at a current of 200% or more of the rated value, but has a durability against an inrush current at a current of 200% or less. The fusing time is relatively long,
There is a problem that the circuit cannot be protected during that time. Further, for an intermittent current of 110% to 200% of the rating (that is, a current due to an incomplete short circuit), the FL1 repeats heat generation and heat dissipation, so that the fusing time tends to be long, and in the worst case, The circuit may break down without fusing.

[0004] An object of the present invention is to solve the above-mentioned conventional problems, and to provide a fusible link unit capable of interrupting even a current in an incomplete short-circuit region of 110% to 200% or less of the FL rating. Is to do.

[0005]

In order to solve the above-mentioned object, a fusible link unit of the present invention is provided on a power supply path connected to a load via a power supply and a fusible link. A semiconductor switch that is switched and controlled in response to supply power from the power supply to the load;
A reference voltage generating means for generating a reference voltage having a voltage characteristic substantially equivalent to a voltage characteristic of a voltage between terminals of the semiconductor switch; and turning on the semiconductor switch according to a difference between a voltage between terminals of the semiconductor switch and the reference voltage. Control means for turning on / off the semiconductor switch for a certain period of time after the semiconductor switch is first turned on, and the control means further turns off the semiconductor switch immediately after a certain time has elapsed. The on / off count of the semiconductor switch is integrated for a predetermined time, and the semiconductor switch is turned off when the on / off count reaches a predetermined count within the period.

In the fusible link unit according to the first aspect of the present invention, as shown in FIG. 2, the ON / OFF control of the semiconductor switch is inhibited for a certain period (for example, 100 msec) from the time when the load is connected. Control only. At this time, if a complete short circuit (dead short circuit) in which a current of 200% or more of the FL rating occurs on the load side, the FL is immediately blown, but 110% to 2% of the FL rating.
In the case of an incomplete short circuit (rare short circuit) in which a current of 00% or less flows, the FL takes a long time to melt, and in some cases, may damage equipment to be protected.

After prohibiting the ON / OFF control of the semiconductor switch for a certain period, the ON / OFF control of the semiconductor switch is made effective. At this time, if an incomplete short circuit has occurred, the semiconductor switch is turned on and off according to the state. That is, when a current in an incomplete short-circuit region of 110% to 200% or less of the FL rating flows, the semiconductor switch is turned off, and is turned on at a current of 110% or less of the FL rating.
After a period during which the on / off control of the semiconductor switch is prohibited, the number of times the semiconductor switch is turned on / off is integrated within a certain period (1 sec), and when the number reaches a predetermined number within the period, the semiconductor switch is turned off. . That is, the supply of power to the load is stopped assuming that an incomplete short circuit has occurred. If the ON / OFF count of the semiconductor switch does not reach the predetermined count within the period, the ON / OFF control of the semiconductor switch is continued. Thus, 110% to 20% of the FL rating
Since a current in an incomplete short circuit region of 0% or less can be cut off, the circuit can be protected even when an incomplete short circuit occurs.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a fusible link unit according to the present invention will be described below in detail with reference to the drawings. Here, FIG. 1 is a configuration diagram according to an embodiment of the fusible link unit according to the present invention, FIG. 2 is a waveform diagram illustrating an operation when an incomplete short circuit occurs in the fusible link unit, and FIG. It is a block diagram of the switching device used.

Before giving a detailed description of the embodiment, first,
A switching device used in the dome lamp unit of the embodiment will be described with reference to FIG. FIG.
In the switching device 110f, the power supply 10
1 is connected to the path for supplying the output voltage VB to the load 102 through the drain D- of the thermal FET QA as a semiconductor switch.
A source S is connected in series to control power supply by switching control of the thermal FET QA. The integrated circuit is a one-chip integrated circuit including a driving unit, a protection unit, a load current detecting unit, and the like, combined with the thermal FET QA. .

The switching device 110f includes a charge pump 305 and a drive circuit 111 as drive means for the thermal FET QA. The driving circuit 111
A source transistor whose collector side is connected to the output of the charge pump 305 and a sink transistor whose emitter side is connected to the ground potential (both not shown) are connected in series to provide a switching signal by switching on / off of the switch SW1. On / off control of the source transistor and the sink transistor based on the
A signal for driving and controlling the ETQA is output. Power supply 1
When the output voltage VB of 01 is 12 [V], for example, the output voltage of the charge pump 305 is set to VB + 10 [V], for example.

Next, as protection means for the thermal FET QA, the switching device 110 f
06. The cutoff latch circuit 306 realizes an overheat cutoff protection function that is also added to a general thermal FET. When the built-in temperature sensor detects that the temperature of the thermal FET QA has risen to a temperature equal to or higher than a specified value, The detection information to that effect is held in the latch circuit, and the thermal FET QA is forcibly turned off by shifting the overheat cutoff FET (not shown) connected between the gate and the source of the thermal FET QA to the ON state. . The information held by the cutoff latch circuit 306 is output via the terminal T14 and can be used as diagnostic (diagnosis) information.

Next, as a load current detecting means of the thermal FET QA, the switching device 110f has an overcurrent detecting function 301 and an undercurrent detecting function. First,
The overcurrent detection function 301 is specifically realized by the FET QB, the resistors R1, R2, R5, Rr1, the diode D1, and the comparator CMP1. That is, the FET QB and the resistor Rr1 are means for generating a first reference voltage in overcurrent detection, and the source SB potential of the FET QB is set to the inverting terminal (-) of the comparator CMP1.
Supplied to Further, a voltage obtained by dividing the voltage VDSA between the drain D and the source S of the thermal FET QA by the resistors R1 and R2 is supplied to the non-inverting terminal (+) of the comparator CMP1 via the resistor R5.

That is, the drain D of the thermal FET QA
A first reference voltage having a voltage characteristic substantially equivalent to the voltage SDS between the source S is generated by the FET QB on the same chip as the switching device 110f and a resistor Rr1 outside the chip, and the first reference voltage and the thermal Voltage V between drain D and source S of FET QA
Overcurrent detection is performed by detecting a difference from DSA.

Therefore, when a complete short circuit (dead short circuit) occurs on the load 102 side, the comparator CM
The output of P1 becomes valid (“H” level), and the drive circuit 111 controls the thermal FET QA to be turned off. When the thermal FET QA transitions from the off state to the on state when a complete short circuit (dead short) has occurred, the drain current flows rapidly, but the thermal FET QA continues the on state to keep the thermal FET QA.
Is overheated, and the thermal
ETQA is overheated. Further, when an incomplete short circuit (rare short) having a certain short-circuit resistance occurs, the on / off control of the thermal FET QA is repeatedly performed to overheat the thermal FET QA by a periodic heating action, and the above-mentioned overheat interruption is performed. Thermal FET Q by protection function
A is designed to accelerate the overheating cutoff.

The setting of the first reference voltage, that is, the setting of the resistor Rr1 is performed as follows. That is, usually, thermal F
Since the ETQA is configured by connecting n FETs (having the same characteristics as the FET QB) in parallel, the resistor Rr1 may be set to (the resistance value of the load 102 × n).
It is desirable to use the short-circuit resistance at the time of incomplete short-circuit (rare short) as the resistance value of 2. Although FIG. 3 shows a configuration in which the output of the comparator CMP1 is supplied only to the drive circuit 111, the output may be output to the outside via a terminal and used for other control or the like.

Next, the undercurrent detection function is, specifically,
This is realized by the FET QC, the resistor Rr2, and the comparator CMP2. That is, the FET QC and the resistor Rr2 are means for generating a second reference voltage in detecting an undercurrent, and the source SC potential of the FET QC is supplied to the inverting terminal (-) of the comparator CMP2. The non-inverting terminal (+) of the comparator CMP2 is supplied with the source SA potential of the thermal FET QA.

That is, the drain D of the thermal FET QA
A second reference voltage having a voltage characteristic substantially equivalent to the source-to-source voltage VDSA is generated by the FET QC on the same chip as the switching device 110f and a resistor Rr2 outside the chip; Voltage V between drain D and source S of FET QA
Undercurrent detection is performed by detecting a difference from DSA. Therefore, when an interruption failure or the like occurs on the load 102 side, the output of the comparator CMP2 becomes valid (“L” level) and is output to the outside of the chip via the terminal T15. Here, the setting of the second reference voltage, that is, the setting of the resistor Rr2 is performed as follows. Similarly to the first reference voltage (resistance Rr1), the resistance Rr2 is
2), but it is desirable to use the load resistance at the time of disconnection failure as the resistance value of the load 102.

In addition to the driving means, protection means and load current detecting means described above, a switching device 110f
Includes a power supply Enable 302, masking (rush current mask circuit) 303 to avoid overcurrent determination of the rush current,
ON / O that performs cutoff control by integrating the ON / OFF circuit
Although the FF count integration circuit 304 is also described,
The description is omitted because it is not directly related to the present invention.

Finally, the characteristics of the switching device 110f are summarized as follows. First, since a shunt resistor for current detection is not required, power consumption in a current supply path can be suppressed, which is advantageous for a large current circuit. Second, high current sensitivity and high current detection accuracy. Third, the thermal FET QA can be turned on / off by simple drive control, and the overheat cutoff function and ON / OF
High-speed processing is possible by the F-count integration circuit 304 as compared with program processing of a microcomputer or the like. Fourth, the circuit configuration can be downsized by using one chip, the mounting space can be reduced, and the device cost can be reduced. Fifth,
Since the current detection is performed by detecting the difference between the drain-source voltage VDSA of the thermal FET QA and the first reference voltage and the second reference voltage, the FE is mounted on the same chip.
By forming the TQB and QC and the thermal FET QA, it is possible to eliminate a common-mode error factor in current detection, that is, an influence of a power supply voltage, a temperature drift, and a variation between lots.

Next, a fusible link unit according to an embodiment of the present invention will be described with reference to FIGS. As described above, FIG. 1 is a configuration diagram of the fusible link unit of the embodiment, and FIG. 2 is a waveform diagram illustrating an operation of the fusible link unit of the embodiment when an incomplete short circuit occurs. In FIG. 1, the fusible link unit of the present embodiment includes an FL (fusible link) 1 and a switching device 16 including a microcomputer 15. Note that the microcomputer 15 corresponds to the control means in the present invention.

The circuit configuration of the switching device 16 shown in FIG. 2 shows only those portions of the circuit configuration of the switching device 110f that are relevant to the present invention.
The microcomputer 15 includes a CPU (not shown), a ROM in which a program for controlling the CPU is written,
And a RAM used in the above operation. The reference resistor Rr1 is for setting a reference voltage, and has a value for setting a current of 110% of the rating of FL1. By setting the reference voltage, when the current in the incomplete short-circuit region of 110% to 200% or less of the rating of FL1 flows when the thermal FET QA is turned on, the current flowing to the load 11 becomes the reference resistor Rr1. Is larger than the current flowing through the comparator CM
The output of P1 becomes valid (“H” level). Thus, the microcomputer 15 controls the drive circuit 111 to turn off the thermal FET QA.

The details of the operation of the microcomputer 15 are shown in FIG.
This will be described with reference to the waveform diagram of FIG. After connecting the load, the microcomputer 15 controls the drive circuit 111 to control the thermal FET QA
Is turned on for a certain period (for example, 100 msec).
At this time, when a current of 200% or more of the rating of the FL1 flows to the load 11, the FL1 is immediately blown and the supply of power to the load 11 is cut off. On the other hand, when a current in the incomplete short-circuit region of 110% to 200% or less of the rating of FL1 flows, the drive circuit 1 responds to the intermittent short-circuit at that time.
11 to turn on and off the thermal FET QA. Then, the number of times the thermal FET QA is turned on and off is integrated for a certain period of time (for example, 1 sec), and when the number of times reaches a predetermined number, the thermal FET QA is turned off and the supply of power to the load 11 is cut off. If the number of times the thermal FET QA is turned on and off does not reach the predetermined number, the on / off control of the thermal FET QA is continued.

As described above, in this embodiment, the thermal FE is fixed for a certain period (for example, 100 msec) after the load is connected.
When the TQA is turned on and the circuit is completely short-circuited, the circuit is protected by fusing FL1. If the circuit is in an incompletely short-circuited state, the FL1 does not blow within that period. The number of times the thermal FET QA is turned on and off is integrated. Then, when the number of times integrated during the period reaches a predetermined number, the thermal FET QA is turned off to protect the circuit. Therefore, 110% of FL1 rating
Since the current in the incomplete short circuit region of 200% or less can be cut off, the circuit can be protected even when the incomplete short circuit occurs.

[0024]

As described above, in the fusible link unit of the present invention, the semiconductor switch is turned on for a predetermined period after the load is connected, and if a short circuit occurs, the FL is blown to protect the circuit. If in an incomplete short circuit state, the number of times the semiconductor switch is turned on and off within a certain period is further integrated, and when the integrated number reaches a predetermined number,
The semiconductor switch is turned off. Therefore,
Since a current in an incomplete short circuit region of 110% to 200% or less of the FL rating can be cut off, the circuit can be protected even if an incomplete short circuit occurs. Further, since the microcomputer can accurately define a certain period after the connection of the load, the blowing time can be reduced as compared with the conventional fuse.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a fusible link unit according to the present invention.

FIG. 2 is a waveform diagram illustrating an operation of the fusible link unit of the embodiment when an incomplete short circuit occurs.

FIG. 3 is a configuration diagram of a switching device used in the fusible link unit of the embodiment.

FIG. 4 is a configuration diagram of a conventional fusible link.

FIG. 5 is a view showing a fusing characteristic of a conventional fusible link.

FIG. 6 is a conventional fusible link circuit diagram.

[Explanation of symbols]

 1 FL (Fusible Link) 10 Battery 11 Load 12 Fuse 15 Microcomputer 16 Switching Device 111 Drive Circuit CMP1 Comparator Rr1 Reference Resistance QA Thermal FET QB FET

Claims (1)

[Claims] A semiconductor switch that is interposed in a power supply path connected to a load via a power supply and a fusible link, and is switching-controlled in accordance with a load current to supply power from the power supply to the load; Reference voltage generating means for generating a reference voltage having a voltage characteristic substantially equivalent to the voltage characteristic of the voltage between the terminals of the switch; and turning on / off the semiconductor switch according to a difference between the voltage between the terminals of the semiconductor switch and the reference voltage. Control means, wherein the control means inhibits on / off control of the semiconductor switch for a certain period after the semiconductor switch is first turned on, and further for a certain period immediately after a certain period has elapsed. And turning off the semiconductor switch when the number of on / off times reaches a predetermined number within the period and integrating the number of on / off times of the semiconductor switch. Fusible link unit.