JP2001085518A - Manufacture of multilayer wiring structure and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoresist with an edge cut region so as to prevent metal constituting a wiring from diffusing into a transistor, when a wiring trench or a connection hole is etched in an insulating film, in the multilayer wiring formation of a semiconductor device. SOLUTION: When a wiring trench 113 or a wiring trench and a connection hole are formed in an insulating film, in a forming process of a multilayer wiring having a metal wiring of copper or copper alloy, an edge cut region formed in a photoresist 105 for etching an upper layer insulating film 104 is shifted to the outer side of the insulating film 104. Copper or copper alloy is embedded in the wring trench 113. A diffusion preventing film preventing diffusion of copper is formed on the insulating film 104. In a process for forming a multilayer wiring on a semiconductor substrate, copper constituting a wiring can be prevented effectively from diffusing into a transistor. Exfoliation between the diffusion preventing film and the insulating film can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device using a metal such as copper for wiring, which has a high diffusion rate in an insulating film such as copper and adversely affects transistor characteristics, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit (LSI) formed by integrating a large number of transistors and resistors into an important part of a computer or a communication device so as to form an electric circuit and integrating them on one chip. Are often used. Therefore, the performance of the entire device is greatly affected by the performance of the LSI alone. The performance improvement of the LSI alone is realized by increasing the degree of integration, that is, by miniaturizing elements. However, as the miniaturization of elements and the progress of miniaturization and multi-layering of wiring have progressed, the following problems have become apparent.
That is, the signal delay due to the resistance of the wiring itself and the parasitic capacitance between the wirings (such as the line capacitance and the interlayer capacitance) poses a problem. As a method of reducing the parasitic capacitance between the wirings, there is a method of lowering the relative dielectric constant of the interlayer insulating film. However, there is a limit in reducing the relative dielectric constant of the material due to its physical properties. Therefore,
There is a method of reducing the area between the wirings facing each other while reducing the relative dielectric constant of the interlayer insulating film, that is, reducing the wiring film thickness. According to this method, although the parasitic capacitance can be reduced, an increase in wiring resistance due to a decrease in the wiring film thickness poses a problem. Therefore, recently, instead of the conventionally used aluminum (Al) wiring, a copper (Cu) wiring having a resistance value about 40% lower than that of the conventional Al has come to be used.

[0003]

However, Cu has a high diffusion rate in an insulating film such as a silicon oxide film.
It easily diffuses to the transistor and adversely affects the transistor characteristics. For this reason, the current situation is to wrap the Cu wiring with a barrier metal that prevents the diffusion of Cu. In general, the barrier metal has a higher resistance than Cu, and when the film thickness is large, the resistance of the wiring is high. For this reason, an edge cut (an insulating film or a photoresist is formed on the entire surface of the wafer) on the semiconductor substrate (wafer), but a predetermined distance from the peripheral edge of the wafer is required to prevent unnecessary formation on the side and back surfaces of the wafer. In the region where the insulating film or the photoresist is not formed on the edge-cut portion, the peripheral edge portion of the edge-cut insulating film or the photoresist is referred to as an edge-cut portion. There is a problem that Cu diffuses into the insulating film. This is remarkable when the barrier metal layer is formed by sputtering. The barrier metal layer formed by sputtering has the same film thickness per unit area, that is, the volume of the barrier metal layer is the same. Therefore, although a sufficient thickness for preventing diffusion can be secured on shallow sidewalls such as wiring trenches,
This is because a sufficient film thickness cannot be secured on a deep side wall such as an edge cut region.

The prior art will be described with reference to FIGS. 9 and 10. FIG. On a semiconductor substrate 1 such as a silicon wafer, CV
A first insulating film 2 made of DSiO ₂ or the like is formed. An impurity diffusion region 11 is formed in a surface region of the semiconductor substrate 1. The first insulating film 2 has an impurity diffusion region 1
1 is formed as a connection hole, in which a connection wiring composed of a barrier metal layer 21 such as a Ti film and a Cu film 22 embedded thereon, that is, a Cu film 22 embedded in the connection hole is formed. . On the first insulating film 2 and the connection wiring, for example, a first silicon nitride film (SiN)
Is formed. First diffusion prevention film 3
A second insulating film 4 made of CVD SiO ₂ or the like is formed on the second insulating film. On this second insulating film 4, a photoresist film 8 patterned in a predetermined shape is formed. Using the patterned photoresist film 8 as a mask, the second insulating film 4 is etched to form the wiring groove 4.
1 is formed (FIG. 9A). Next, after removing the photoresist film 8, a barrier metal layer 42 is formed on the side wall and the bottom surface of the wiring groove 41 and on the second insulating film 4, and further, Cu
A film 43 is deposited inside the wiring groove 41 and on the second insulating film 4 (FIG. 9B).

After that, the Cu film 43 is formed by chemical mechanical polishing (CMP) or CDE.
The Cu film 43 on the second insulating film 4 is removed by (Chemical Dry Etching) or the like, and a buried wiring composed of the Cu film 43 is formed in the wiring groove 41. Next, plasma CV
A second diffusion prevention film 5 made of a silicon nitride film (SiN) or the like is formed by a method D or the like. In the subsequent process,
A plurality of upper insulating films are formed, and a wiring layer is formed on each layer to form a multilayer wiring structure on the semiconductor substrate (FIG. 9C).
During the manufacturing process of such a semiconductor device, a diffusion prevention film for preventing diffusion of Cu or the like is formed on the surface of each insulating film, but the edge cut region at the end is not covered with the diffusion prevention film. Therefore, in this state, when passing through the Cu process step, Cu may diffuse into the semiconductor substrate from the outer periphery of the semiconductor substrate, and may change the characteristics of the transistor formed on the semiconductor substrate (FIG. 9B). )reference).
As described above, in the conventional edge cut region, since the diffusion of Cu from the lateral direction of the edge cut region is prevented only by the thin barrier metal layer on the deep side wall portion, the problem that Cu diffuses into the insulating film occurs. ing.

[0009] Further, on the semiconductor substrate 1, FIG.
A third insulating film 6 is formed on the second diffusion preventing film 5 shown in FIG.
Then, the third diffusion prevention film 7 is sequentially laminated to form a multilayer wiring structure. During this manufacturing process, there is a problem that the diffusion prevention film and the insulating film may be separated from the edge cut region (FIG. 10). The present invention has been made in view of such circumstances, and when a wiring groove or a connection hole is formed in an insulating film by etching in forming a multilayer wiring of a semiconductor device, diffusion of a metal constituting the wiring to a transistor is prevented. Provided is a method of manufacturing a semiconductor device having an edge cut region of a photoresist having a structure capable of performing the same.

[0007]

According to the present invention, in a step of forming a multilayer wiring having at least one metal wiring made of copper or a copper alloy of a semiconductor device, a wiring groove or a connection hole or a wiring groove or a connection hole is formed in an insulating film. When etching is formed, the edge cut region of the photoresist used for etching the insulating film is shifted outward toward the upper layer, and a diffusion prevention film for preventing diffusion of copper is extended to the side wall of the insulating film. Is characterized in that the insulating film is covered with a diffusion preventing film for each layer. During the step of forming a multilayer wiring on a semiconductor substrate, it is possible to effectively prevent copper constituting the wiring from diffusing into a transistor. Further, peeling between the diffusion prevention film and the insulating film can be reduced.

That is, the multilayer wiring structure of the present invention has a multilayer wiring structure in which metal wiring or metal connection wiring or a metal wiring and a metal connection wiring are embedded and a plurality of insulating films having an edge cut region are laminated. Comprising a semiconductor substrate having, the edge cut region of the upper insulating film extends to outside the edge cut region of the lower insulating film,
A first feature is that at least one layer of the laminated insulating film is embedded with a metal wiring made of copper or a copper alloy, a metal connection wiring, or a metal wiring and a metal connection wiring. Further, the multilayer wiring structure of the present invention is a semiconductor substrate having a multilayer wiring structure in which metal wiring or metal connection wiring or metal wiring and metal connection wiring are embedded and a plurality of insulating films having edge cut regions are laminated. Wherein at least one layer of the laminated insulating film is formed by embedding metal wiring or metal connection wiring or metal wiring and metal connection wiring made of copper or copper alloy, and metal wiring or metal made of copper or copper alloy The connection wiring or the metal wiring and the insulating film in which the metal connection wiring is buried, the edge cut region of the upper insulating film extends to the outside of the edge cut region of the lower insulating film.
The feature is. The surface of each layer of the laminated insulating film may be covered with a diffusion prevention film for preventing diffusion of copper, including a side wall portion of the edge cut region.

In a method of manufacturing a semiconductor device according to the present invention, a lower insulating film having an edge cut region is formed on a main surface of a semiconductor substrate, and a wiring groove or a connection hole or a wiring groove and a connection are formed in the lower insulating film. Forming a hole, embedding a lower metal wiring or a metal connection wiring or a metal wiring and a metal connection wiring in the wiring groove or the connection hole or the wiring groove and the connection hole; and covering the side wall portion of the edge cut region. Forming a lower diffusion prevention film on the lower insulation film; and forming an upper insulation film having an edge cut region on the first diffusion prevention film, wherein the edge cut region has an edge of the lower insulation film. Forming a pattern so as to extend to the outside of the cut region; and forming a predetermined pattern on the upper insulating film, wherein the edge cut region has an edge cut of the upper insulating film. Forming a photoresist film extending outside of the region, etching the upper insulating film using the photoresist film as a mask to form a wiring groove or a connection hole or a wiring groove and a connection hole; After removing the photoresist film, depositing a metal film on the upper insulating film and inside the wiring groove or the connection hole or the wiring groove and the connection hole; and forming a metal film on the wiring groove or the connection hole or the wiring groove and the connection hole. Removing a metal film other than the buried metal film to make the buried portion of the metal film an upper metal wiring or a metal connection wiring or a metal wiring and a metal connection wiring; and covering a side wall portion of the edge cut region. Forming an upper diffusion prevention film on the upper insulating film so that the edge cut region of the upper insulating film is formed by etching of the lower insulating film. It is characterized by configured to extend to the outside of Jikatto region.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. 1 to 3 are cross-sectional views showing a manufacturing process for forming a multilayer wiring formed on a semiconductor substrate.
Is a plan view of the manufacturing process. In this embodiment, the description of the element isolation forming step and the transistor forming step is omitted, and only the two-layer wiring of the multilayer wiring structure will be described. In the formation of the wiring, formation of a Cu wiring by a dual-damascene process will be described. As shown in FIG. 1A, a semiconductor substrate 101 such as a silicon wafer
A first interlayer insulating film 102 made of CVD SiO ₂ or the like is formed thereon. In the surface region of the semiconductor substrate 101, an element isolation region and a transistor such as a MOSFET are formed. The first interlayer insulating film 102 has a 5.0 mm long edge cut from the peripheral end of the semiconductor substrate 101. The region from the peripheral end to the edge cut portion is called an edge cut region of the interlayer insulating film.

Next, a first metal wiring is formed. For this purpose, first, an etching stopper film 103 made of a silicon nitride film for etching a wiring groove is formed on the semiconductor substrate 1.
01, on the upper surface and the side wall of the first interlayer insulating film 102. Then, a second interlayer insulating film 104 having a low relative dielectric constant is deposited on the etching stopper film 103 as an insulating film between wirings. Several materials and forming methods can be considered for the second interlayer insulating film. For example, there is a silicon oxide film to which fluorine (F) or boron (B) is added by a low pressure plasma CVD (Chemical Vapor Deposition) method, and a silicate film or a polymer film by a spin-coat coating method. Silicate-based films include those containing an organic component and those containing no organic component. As another film formation method, there is an organic film formed by a vapor deposition polymerization method. Here, the low dielectric constant film is mainly described. However, since there is a product that does not require a low dielectric constant of an insulating film depending on a device, a silicon oxide film formed by a generally used CVD method is used for these product groups. (Boron-doped Phospho-Silic) containing boron, phosphorus and phosphorus (P)
ate glass) film and PSG (Phospho-Silicate Glass) film can also be used. In this embodiment, low pressure plasma CVD
A fluorine-added silicon oxide film formed by the method is used. Next, a photoresist film 105 is formed on the second interlayer insulating film 104 of the semiconductor substrate 101.

This photoresist film 105 is patterned into a first wiring pattern shape, and an edge cut is set at 4.5 mm from the peripheral end of the semiconductor substrate 1. Thereby, the edge cut of the photoresist film 105 at the time of forming the first wiring is performed by the first interlayer insulating film 10.
That is, it is set to be 0.5 mm outside of the edge cut of No. 2. That is, the patterned and edge-cut photoresist film 105 becomes the second interlayer insulating film 104.
Of the first interlayer insulating film 102 (FIG. 1A). FIG. 4 illustrates a planar state of the semiconductor substrate. The semiconductor substrate 101 is made of a silicon wafer, and a chip forming region where a plurality of chips are finally formed by dicing the semiconductor substrate 101 is formed. An edge-cut second interlayer insulating film 104 is formed on the semiconductor substrate 101 (FIG. 4A). An edge-cut photoresist film 105 is formed thereon (FIG. 4B).
This photoresist film 105 is patterned. Next, using the patterned photoresist film 105 as a mask, a wiring groove 113 in which the first wiring is buried is formed by RIE (Reactive Ion Etching) or the like.
At this time, the second interlayer insulating film 104 is edge-cut (FIGS. 1B and 4).

Next, after the photoresist film 105 is removed, a metal film 106 serving as a first wiring material is formed in the wiring groove 11.
3 and on the semiconductor substrate 101 and the second interlayer insulating film 104. As this deposition method, for example, a titanium nitride film (TiN) as a Cu diffusion preventing film is deposited to a thickness of 10 nm by a sputtering method, and then a Cu film having a thickness of about 100 nm is deposited. Further, a Cu film is formed on the sputtering Cu film by an electroplating method to a thickness of 800 nm.
Deposit to a degree. As described above, the metal film 106 is composed of the titanium nitride film, the sputtering Cu film, and the electroplated Cu film (FIG. 1C). Next, the Cu film forming the metal film 106 is flattened by a CMP method or the like, and the Cu film is left only in the wiring groove 113. The metal film 106 in the wiring groove 113 forms the first wiring 106. Thereafter, a diffusion prevention film 107 for Cu is deposited on the entire surface of the second interlayer insulating film 104 including the first wiring 106. As the diffusion prevention film 107, there is a thin silicon nitride film (SiN) formed by a plasma CVD method (FIG. 2).
(A)).

Next, a diffusion prevention film 1 is formed on the semiconductor substrate 101.
A third interlayer insulating film 108 made of a fluorine-doped silicon oxide film is deposited by, for example, a low-pressure plasma CVD method so as to cover layer 07 (FIG. 2B). On the third interlayer insulating film 108, a photoresist film 114 is formed.
The photoresist film 114 is patterned so as to form a wiring groove and a connection hole, and the third interlayer insulating film 10 is formed.
8 is cut so as to cover the side surface of FIG.
(C)). Lithography and RIE (Reactive Io
n Etching) or the like, the second wiring groove 115 and the first wiring 106 are formed in the third interlayer insulating film 108.
Is formed to reach the first connection hole 116. At this time, the edge cut area of the photoresist film 114 serving as a mask for pattern processing is set to be 4 mm from the end of the semiconductor substrate 101, which is 0.5 mm outside the edge cut area of the photoresist film 105 (FIG. a)).

Next, after removing the photoresist film 114,
A metal film 109 serving as a second wiring and a first connection wiring is deposited on the semiconductor substrate 101. In this step, the metal film 1
This is the same as the step of depositing 06. As this deposition method, for example, a titanium nitride film (TiN) as a Cu diffusion preventing film is deposited to a thickness of 20 nm by a sputtering method, and then a Cu film having a thickness of about 100 nm is deposited. Further, a Cu film is deposited to a thickness of about 800 nm on the sputtering Cu film by electroplating. As described above, the metal film 109 is composed of the titanium nitride film, the sputtering Cu film, and the electroplated Cu film. Next, CMP
The Cu film forming the metal film 109 is flattened by a method or the like, so that C is formed only in the wiring groove 115 and the connection hole 116.
The u film is left. The metal film 109 in the wiring groove 115 is
The second wiring is formed. Metal film 109 in connection hole 116
Constitutes a first connection wiring electrically connected to the first wiring 106. After that, the diffusion prevention film 11 for Cu
0 is deposited on the entire surface of the third interlayer insulating film 108 including on the second wiring. Plasma CV as the diffusion prevention film 110
There is a thin silicon nitride film (SiN) formed by the D method (FIG. 3B).

Next, a diffusion prevention film 1 is formed on the semiconductor substrate 101.
A fourth interlayer insulating film 111 made of a fluorine-added silicon oxide film is deposited by, for example, a low-pressure plasma CVD method so as to cover 10 (FIG. 3C). By repeating the above method, third, fourth,... Multilayer wirings are sequentially formed. As described above, in this embodiment, in the step of forming a multilayer wiring, when forming a wiring groove or a wiring groove and a connection hole in an insulating film by etching, the edge cut region of the photoresist film used for the insulating film etching is increased as the upper layer is formed. During the step of forming a multilayer wiring on a semiconductor substrate, a combination of shifting to the outside and extending a diffusion prevention film for preventing diffusion of a metal such as Cu into the insulating film up to the side wall of the insulating film is provided. In this case, it is possible to prevent the metal constituting the wiring from diffusing into the transistor. Further, since the diffusion preventing film extends to the side wall of the insulating film, the diffusion preventing film and the insulating film are hardly peeled off, and the bonding strength between the two is improved.

Next, a second embodiment will be described with reference to FIGS. 5 to 7 are cross-sectional views showing a manufacturing process for forming a multilayer wiring formed on a semiconductor substrate. In this embodiment, the description of the element isolation forming step and the transistor forming step is omitted, and only the two-layer wiring of the multilayer wiring structure will be described. In this embodiment, a multilayer wiring having a buried Cu wiring by a single damascene process will be described. As shown in FIG. 5A, a first interlayer insulating film 202 made of CVD SiO ₂ or the like is formed on a semiconductor substrate 201 such as a silicon semiconductor. An element isolation region and a transistor such as a MOSFET are formed in a surface region of the semiconductor substrate 201 (not shown). First
Of the interlayer insulating film 202 is 5.0 mm long from the terminal end of the semiconductor substrate 201. The region from the terminal end to the edge cut portion is called an edge cut region of the interlayer insulating film.

Next, a first metal wiring is formed. For this purpose, first, an etching stopper film 203 made of a silicon nitride film or the like for etching a wiring groove is formed on the semiconductor substrate 201, on the upper surface and the side wall of the first interlayer insulating film 202. Then, a second interlayer insulating film 204 having a low relative dielectric constant is deposited on the etching stopper film 203 as an insulating film between wirings. Several materials and forming methods can be considered for the second interlayer insulating film. For example,
There is a silicon oxide film to which fluorine (F) or boron (B) is added by a low-pressure plasma CVD method, and a silicate film or a polymer film by a spin coating method. Silicate-based films include those containing an organic component and those containing no organic component. As another film formation method, there is an organic film formed by a vapor deposition polymerization method. Here, the low dielectric constant film is mainly described. However, since there is a product that does not require a low dielectric constant of an insulating film depending on a device, a silicon oxide film formed by a generally used CVD method is used for these product groups. A BPSG film or a PSG film containing boron, boron, or phosphorus (P) can also be used. In this embodiment, the reduced pressure plasma C
A fluorine-added silicon oxide film formed by the VD method is used.

Next, a photoresist film 205 is formed on the second interlayer insulating film 204 of the semiconductor substrate 201. This photoresist film 205 is patterned into a first wiring pattern shape, and an edge cut is set at 4.5 mm from the peripheral end of the semiconductor substrate 2. As a result, the edge cut of the photoresist film 205 at the time of forming the first wiring is set to be 0.5 mm outside the edge cut of the first interlayer insulating film 202. That is,
The patterned and edge-cut photoresist film 205 covers a portion of the second interlayer insulating film 204 that covers the edge cut region of the first interlayer insulating film 202 (FIG. 5A). Next, using the patterned photoresist film 205 as a mask, a wiring groove 217 in which the first wiring is buried is formed by RIE or the like. At this time, the second interlayer insulating film 204 is edge-cut (FIG. 5B).

Next, a metal film serving as a first wiring material is formed in the wiring groove 217, the semiconductor substrate 201, and the second interlayer insulating film 2.
04. As this deposition method, for example,
A titanium nitride film (TiN) which is a Cu diffusion prevention film
deposited by sputtering with a thickness of nm, then
A Cu film having a thickness of about 100 nm is deposited. Further, a Cu film is formed on the sputtered Cu film by electroplating.
Deposit about 0 nm. As described above, the metal film is composed of the titanium nitride film, the sputtering Cu film, and the electroplated Cu film. Next, the Cu film forming the metal film is flattened by a CMP method or the like, and the Cu film is left only in the wiring groove 217. The metal film in the wiring groove 217 is
The first wiring 206 is formed. After that, a diffusion prevention film 207 for Cu is deposited on the entire surface of the second interlayer insulating film 204 including the first wiring 206. As the diffusion prevention film 207, there is a thin silicon nitride film (SiN) formed by a plasma CVD method (FIG. 5C).

Next, the diffusion preventing film 2 is formed on the semiconductor substrate 201.
07, a third interlayer insulating film 208 made of a fluorine-added silicon oxide film is deposited by, for example, a low pressure plasma CVD method. A photoresist film 209 is formed on third interlayer insulating film 208, and this photoresist film 209 is patterned so as to form a connection hole, and edge cut so as to cover the side surface of third interlayer insulating film 208. Is done. Then, a first connection hole 218 reaching the first wiring 206 is formed in the third interlayer insulating film 208 by lithography and dry etching such as RIE. At this time, the edge cut region of the photoresist film 209 serving as a mask for pattern processing is
6 is set to 4 mm from the end of the semiconductor substrate 201, which is 0.5 mm outside the edge cut area of FIG.
(A)).

Next, after removing the photoresist film 209,
A metal film serving as a first connection wiring is deposited on the semiconductor substrate 201. As this deposition method, for example, a titanium nitride film (TiN) of a high melting point metal is deposited to a thickness of 300 nm by a sputtering method, and then a tungsten (W) film is deposited on the entire surface of the TiN film. Thus, the metal film is composed of the TiN film and the W film. Next, C
The W film constituting the metal film is flattened by the MP method or the like, and the metal film is left only in the first connection hole 218. The metal film in the first connection hole 218 is
The first connection wiring 210 electrically connected to the first connection wiring 210 is formed. After that, the stopper film 211 serving as an etching stopper at the time of processing the second wiring groove is formed on the first connection wiring 210.
It is deposited on the entire surface of the third interlayer insulating film 208 including the upper portion.
The stopper film 211 has a thin silicon nitride film (Si) formed by a plasma CVD method which also has an effect of preventing Cu diffusion.
N) or the like (FIG. 6B).

Next, for example, low pressure plasma CVD is performed so as to cover the stopper film 211 on the semiconductor substrate 201.
A fourth interlayer insulating film 212 made of a fluorine-added silicon oxide film is deposited by a method. Then, the fourth interlayer insulating film 2
12, a photoresist film 213 is formed. The photoresist film 213 is patterned so as to form a wiring groove, and edge-cut so as to cover the side surface of the fourth interlayer insulating film 212. Then, a second wiring groove 219 reaching the first connection wiring 210 is formed in the fourth interlayer insulating film 212 by lithography and dry etching such as RIE. At this time, the edge cut area of the photoresist film 213 serving as a mask for pattern processing is 0.5 mm from the edge cut area of the photoresist film 209.
The distance is set to 3.5 mm from the end of the outer semiconductor substrate 201 (FIG. 6C).

Next, after removing the photoresist film 213,
A metal film serving as a second wiring is deposited on the semiconductor substrate 201. As this deposition method, for example, a titanium nitride film (TiN), which is a Cu diffusion prevention film, is deposited to a thickness of 10 nm by a sputtering method, and then a film thickness of about 100 n
An m-th Cu film is deposited. Further, a Cu film is deposited to a thickness of about 800 nm on the sputtering Cu film by electroplating. As described above, the metal film is composed of the TiN film, the sputtering Cu film, and the electroplated Cu film. Next, the Cu film constituting the metal film is planarized by a CMP method or the like, and the Cu film is left only in the second wiring groove 219. The metal film in the second wiring groove 219 is a second wiring 214 electrically connected to the first connection wiring 210.
Is configured. After that, a diffusion preventing film 215 for preventing diffusion of Cu into the insulating film is deposited on the entire surface of the fourth interlayer insulating film 212 including the second wiring 214. As the diffusion preventing film 215, a thin silicon nitride film (SiN) or the like formed by a plasma CVD method is used (FIG. 7A). Next, so as to cover the diffusion preventing film 215 on the semiconductor substrate 201,
For example, a fifth interlayer insulating film 216 made of a fluorine-added silicon oxide film is deposited by a low pressure plasma CVD method (FIG. 7B).

By repeating the above method, the third,
Fourth,... Multilayer wirings are sequentially formed. FIG.
It is sectional drawing of the semiconductor substrate which illustrated four wiring layers. On a semiconductor substrate (wafer) 301, a first insulating film 302, a second insulating film 304,
Insulating film 306, a fourth insulating film 308, and a fifth insulating film 310 are stacked, each of which is a first diffusion preventing film 303, a second diffusion preventing film 305, and a third diffusion preventing film 3.
07, fourth anti-diffusion film 309 and fifth anti-diffusion film 3
11 coated. Further, the first insulating film 302
The first connection wiring 312 for connecting the semiconductor substrate 301 and the wiring in the upper layer is formed in the substrate. A first wiring 314 is formed in the second insulating film 304. Third insulating film 3
In 06, a second wiring 316 and a second connection wiring 315 are formed. The third wiring 3 is formed on the fourth insulating film 308.
17 and a third connection wiring 318 are formed. The fifth wiring 320 and the fourth wiring 320 are formed on the fifth insulating film 310.
Connection wiring 319 is formed. Thus, in the present invention, the upper insulating film is formed so as to cover the edge cut portion of the lower insulating film. Cu or a Cu alloy is used for the wiring and the connection wiring. For example, when the material of the second wiring 316 and the second connection wiring 315 is aluminum (Al), the third insulating film 306 is
Since it is not necessary to cover the edge cut portion of the second insulating film 304, the edge cut portion of the third insulating film 306 is
May be formed on the inner side of the edge cut portion of the first insulating film 304 (however, the third insulating film must cover the edge cut portion of the first insulating film).

As described above, in this embodiment, in the step of forming the multilayer wiring, when the wiring groove or the connection hole is formed in the insulating film by etching, the edge cut region of the photoresist film used for the etching of the insulating film is formed in the upper layer. During the step of forming a multilayer wiring on a semiconductor substrate, a combination of shifting to the outside and extending a diffusion prevention film for preventing diffusion of a metal such as Cu into the insulating film up to the side wall of the insulating film is provided. In this case, it is possible to prevent the metal constituting the wiring from diffusing into the transistor. Further, since the diffusion preventing film extends to the side wall of the insulating film, the diffusion preventing film and the insulating film are hardly peeled off, and the bonding strength between the two is improved.

[0027]

According to the present invention, when a wiring groove or a connection hole or a wiring groove and a connection hole is formed in an insulating film by etching, the edge cut region of the photoresist used for the etching of the insulating film is shifted outward toward the upper layer. In addition, the insulating film is covered with the diffusion preventing film for each layer in combination with extending the diffusion preventing film for preventing the diffusion of copper to the side wall of the insulating film. In this case, it is possible to effectively prevent copper constituting the wiring from diffusing into the transistor. Further, peeling between the diffusion prevention film and the insulating film can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process according to a first embodiment.

FIG. 2 is a sectional view showing a manufacturing process of the first embodiment.

FIG. 3 is a sectional view showing a manufacturing process of the first embodiment.

FIG. 4 is a plan view of the semiconductor substrate according to the first embodiment.

FIG. 5 is a sectional view of a manufacturing process according to a second embodiment.

FIG. 6 is a sectional view of a manufacturing process according to a second embodiment.

FIG. 7 is a sectional view of a manufacturing process according to a second embodiment.

FIG. 8 is a cross-sectional view of the semiconductor substrate of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

FIG. 10 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1, 101, 201, 301 ... semiconductor substrate (wafer), 2, 4, 6, 102, 104, 108, 111,
202, 204, 208, 212, 216, 302, 3
04, 306, 308, 310 ... insulating films, 3, 5,
7, 103, 107, 110, 203, 207, 21
1, 215, 303, 305, 307, 309, 311
... Diffusion-preventing film for preventing copper diffusion, 8, 105, 1
14, 205, 209, 213: photoresist film, 11: impurity diffusion region, 21, 42 ...
Barrier metal layer, 22, 43 ... Cu film, 41, 11
3, 115, 217, 219 ... wiring groove, 106, 1
09 ... metal film (wiring), 116, 218 ...
Connection holes, 206, 314, 316, 318, 320 ...
. Wiring 210, 214, 312, 315, 317, 319
・ Connection wiring.

Claims (4)

[Claims] A semiconductor substrate having a multilayer wiring structure in which metal wiring or metal connection wiring or a metal wiring and metal connection wiring are embedded and a plurality of insulating films each having an edge cut region are laminated; The edge cut region of the insulating film extends to the outside of the edge cut region of the lower insulating film, and at least one of the stacked insulating films.
A multilayer wiring structure, wherein the layer is embedded with a metal wiring made of copper or a copper alloy, a metal connection wiring, or a metal wiring and a metal connection wiring. 2. A semiconductor substrate having a multilayer wiring structure in which a plurality of insulating films each having a metal wiring or a metal connection wiring or a metal wiring and a metal connection wiring embedded therein and having an edge cut region are stacked. At least one layer of the insulating film is embedded with metal wiring or metal connection wiring or metal wiring and metal connection wiring made of copper or copper alloy, and the metal wiring or metal connection wiring or metal wiring made of copper or copper alloy and A multilayer wiring structure, wherein the insulating film in which the metal connection wiring is embedded has an edge cut region of an upper insulating film extending to an outside of an edge cut region of a lower insulating film. 3. The method according to claim 1, wherein the surface of each layer of the laminated insulating film is covered with a diffusion prevention film for preventing copper diffusion including a side wall portion of an edge cut region. 3. The multilayer wiring structure according to 2. 4. A step of forming a lower insulating film having an edge cut region on the main surface of the semiconductor substrate, and forming a wiring groove or a connecting hole or a wiring groove and a connecting hole in the lower insulating film. Or embedding a lower metal wiring or a metal connection wiring or a metal wiring and a metal connection wiring in the connection hole or the wiring groove and the connection hole; and forming a lower layer on the lower insulating film so as to cover a side wall portion of the edge cut region. Forming an anti-diffusion film, and an upper insulating film having an edge cut region on the first anti-diffusion film, the edge cut region extending to outside the edge cut region of the lower insulating film. And forming a photo-resist having a predetermined pattern on the upper insulating film, the edge cut region of which extends outside the edge cut region of the upper insulating film. Forming a resist film, forming a wiring groove or a connection hole or a wiring groove and a connection hole by etching the upper insulating film using the photoresist film as a mask, and removing the photoresist film; Depositing a metal film on the upper insulating film and inside the wiring groove or the connection hole or the wiring groove and the connection hole; and forming a metal other than the metal film embedded in the wiring groove or the connection hole or the wiring groove and the connection hole. Removing the film to make the buried portion of the metal film an upper metal wiring or a metal connection wiring or a metal wiring and a metal connection wiring; and forming the upper insulating film so as to cover a side wall portion of an edge cut region. Forming an upper diffusion prevention film thereon, wherein the edge cut region of the upper insulation film extends to outside the edge cut region of the lower insulation film. The method of manufacturing a semiconductor device, characterized by configuring urchin.