JP2001060515A - Laminated chip inductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated chip inductor, in which the difference in total thickness is relaxed in a laminated body formed by laminating a magnetic layer, internal stress does not concentrate at a specific point during lamination, and the reliability is high, without producing delamination. SOLUTION: In this inductor, a spiral conductor pattern 12 is formed on a first magnetic layer 11, and a spiral conductor pattern 15 is formed on a second magnetic layer 13, the magnetic layers 11 and 13 are laminated, and the conductor patterns 12 and 15 are electrically connected with each other by a through-hole 14. In this case, by making small the amount of the conductor patterns 12 and 15 overlapping with each other, the difference in total thickness is relaxed. Thus, an internal stress hardly concentrates at a specific point during lamination, and delamination is not produced, thus a highly reliable laminated chip inductor can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer chip inductor used for electronic equipment.

[0002]

2. Description of the Related Art As disclosed in Japanese Patent Application Laid-Open No. 3-278506, this kind of multilayer chip inductor having a conductor pattern for a coil of one or more turns is conventionally known as "a plurality of sheets made of an insulator or a magnetic material. A laminated body obtained by laminating and firing the sheets, and a laminated coil component having a winding line disposed in the sintered body and configured to advance in the thickness direction of the sintered body, At least a part of the winding line is wound at least one turn or more in a plane of the same height of the sintered body "(first conventional technique) and Japanese Patent Application Laid-Open No. 4-93006. "A laminated bead inductor in which a magnetic layer and a conductor layer are laminated by a thick film technology, the number of turns per layer is one or more turns, and a through hole is formed in the magnetic layer between the adjacent conductor layers. Forming Through the through-holes are formed in the conductive ends comrades adjacent pair of conductive layers "(second prior art).

Hereinafter, a multilayer chip inductor according to a first prior art will be described with reference to the drawings.

FIGS. 7A to 7F are plan views for explaining a method of manufacturing a multilayer chip inductor according to the prior art.

First, a first sheet 31 is obtained by printing a ferrite paste in a rectangular shape. Next, FIG.
As shown in (a), the end 32 pulled out to the one edge 31a side of the sheet 31 by printing the conductive paste.
A first line 32 having a is formed. This track 32
Are spirally configured to have more than about two turns.

Next, as shown in FIG. 7B, a second sheet 33 is laminated by printing a ferrite paste so as to cover a half area of the first sheet 31. The second sheet 33 is laminated so as not to cover the inner end 32b of the line 32.

[0007] Next, as shown in FIG.
The second line 34 is formed by printing a conductive paste so as to be connected to the inner end 32b of the second sheet 33 and the end 34a is located on the second sheet 33.

Further, as shown in FIG. 7D, a third sheet 35 is laminated on the exposed area of the first sheet 31 to cover the remaining exposed area of the line 32.

Next, as shown in FIG.
The line 36 is printed by printing a conductive paste so as to be connected to the end 34a of the line. This line 36
It is spirally wound about 1.75 turns from the portion connected to the end 34 a of the line 34 to the outside, and is drawn out to the edge 33 a of the sheet 33.

Finally, as shown in FIG. 7F, a sheet 38 is laminated by printing a ferrite paste in the same shape as the first sheet 31.

The laminate obtained as described above is pressed and fired in the thickness direction, and external electrodes are applied to obtain a multilayer chip inductor.

[0012]

However, in the above-mentioned conventional configuration, since the conductor patterns overlap each other, the thickness of the conductor pattern is particularly increased at portions where the conductor patterns overlap and at portions where the conductor patterns do not overlap. About
There is a problem that a large difference occurs in the overall thickness, and when the layers are laminated, a partial internal stress is concentrated on an overlapping portion of the conductor pattern, and the strain of the magnetic layer increases, thereby causing delamination. Was.

The present invention solves the above-mentioned conventional problems. In a laminated body obtained by laminating magnetic layers, the difference in overall thickness is reduced, and the internal stress is not concentrated on a specific portion during lamination. It is an object of the present invention to provide a multilayer chip inductor in which delamination does not occur.

[0014]

In order to achieve the above object, the present invention comprises a method of forming a plurality of magnetic layers having a coil conductor pattern of one or more turns on an upper side of the coil conductor pattern of one or more turns. The present invention is characterized in that most of the coil conductor pattern located on the lower side and the coil conductor pattern located on the lower side are laminated so as not to overlap each other at positions facing each other in the laminating direction.

[0015] At least one magnetic layer on which one or more turns of the coil conductor pattern is formed and at least one magnetic layer on which one or less turns of the coil conductor pattern are formed are combined with each other for one or more turns. The coil conductor pattern and the majority of the coil conductor pattern of one turn or less are laminated so that they do not overlap each other at positions facing each other in the laminating direction.

Thus, the difference in the overall thickness is reduced,
It is possible to obtain a multilayer chip inductor in which internal stress does not concentrate on a specific portion during lamination and delamination does not occur.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a plurality of magnetic layers having a coil conductor pattern of one or more turns are positioned on the upper side of the coil conductor pattern of one or more turns. By laminating so that most of the coil conductor pattern located on the lower side and the coil conductor pattern located below do not overlap each other in the laminating direction, the difference in overall thickness is reduced, and internal stress during lamination is reduced. It has an effect that it does not concentrate on a specific location and no delamination occurs.

According to a second aspect of the present invention, there is provided at least one magnetic layer having a coil conductor pattern of at least one turn and at least one magnetic layer having a coil conductor pattern of one turn or less. By laminating the layers so that most of the coil conductor pattern of one or more turns and the coil conductor pattern of one or less turns do not overlap at a position facing each other in the laminating direction, the difference in overall thickness is reduced. This has the effect of preventing internal stress from concentrating on a specific portion during lamination and preventing delamination.

Embodiment 1 Hereinafter, a multilayer chip inductor according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an exploded plan view of each layer of the multilayer chip inductor according to the first embodiment of the present invention. FIG.
FIG. 3 is a plan view of the inside of a laminated body in which the respective layers are laminated. FIG. 3 is a sectional view taken along the line AA of FIG.

In FIGS. 1, 2, and 3, reference numeral 11 denotes a first magnetic layer made of ferrite. Reference numeral 12 denotes a line provided on the first magnetic layer 11 and formed in a spiral shape so as to spread from the center to the outside and having an end 12a and an inner end 12b extended to one end. It is a conductor pattern. Reference numeral 13 denotes a second magnetic layer having a conductive through hole 14 filled with a conductive material such as Ag. Reference numeral 15 denotes an end portion 15a provided on the second magnetic layer 13 and formed in a spiral shape so as to expand from the center to the outside, and is drawn to one edge and an inner end portion 15a.
This is a conductor pattern to be a line having b. 16 is the first
A third magnetic layer disposed on a surface facing the first magnetic layer 11 and the second magnetic layer 13, and the first, second, and third magnetic layers 11, 13, and 16 are disposed at inner end portions. The laminated body 17 is formed by laminating the layers 12b and 15b so as to conduct through the conductive through holes 14. Reference numeral 18 denotes an external base electrode provided on both opposing side surfaces of the laminate 17.

The manufacturing method of the multilayer chip inductor configured as described above will be described below.

First, a plurality of magnetic sheets are prepared from a ferrite slurry by a green sheet method.

Next, as shown in FIG. 1A, the first magnetic material layer 11 is spirally drawn from the center to the outside so as to spread from the center to one side in the width direction. The conductor pattern 12 to be a line having the end 12a and the inner end 12b is printed using an Ag paste.

Next, as shown in FIG. 1B, a hole is formed in the center of the second magnetic layer 13 and then filled with a conductive material such as Ag to form a conductive through hole 14. An end portion 15a which is spirally extended from the center to the outside so as to spread out from the center so that most of the conductor patterns 12 formed on the first magnetic layer 11 do not overlap with each other, and is drawn out to one edge in the width direction. A conductor pattern 1 serving as a line having an inner end 15b connected to the conductive through hole 14;
5 is printed using an Ag paste.

Next, as shown in FIG. 2, the second magnetic sheet 13 is placed on the first magnetic layer 11 through the through-holes 14 at the inner end 12 of the conductor pattern 12.
b and the inside end 15b of the conductor pattern 15 are connected to each other.

Next, the third magnetic layer 16 is laminated to a predetermined thickness, and after applying a pressure of about 70 kg / cm ² , the binder is burned and removed by heating in air to obtain 85%.
Baking is performed at a high temperature of about 0 to 1000 ° C. to form the laminate 17 shown in FIG. At this time, the first,
The end portions 12a and 15a of the conductor pattern formed on the second magnetic layers 11 and 13 are exposed. As shown in the cross-sectional view of FIG. 3, most of the conductor pattern 12 formed on the first magnetic layer 11 and the conductor pattern 15 formed on the second magnetic layer 13 do not overlap.

Next, as shown in FIG. 4, the opposing side surfaces of the laminated body 17 are electrically connected to the end portions 12a and 15a of the conductor pattern exposed from the end face of the laminated body 17.
The external base electrode 18 is formed by applying an Ag-based conductive paste and baking it at 550 to 900 ° C.

Finally, N is applied so as to cover the external base electrode 18.
The i-plating is performed, and the Sn plating is performed so as to cover the Ni plating to form external electrodes, thereby manufacturing a multilayer chip inductor component.

The method of forming the magnetic layers 11, 13 and 16 may be a printing method other than the green sheet method. Ag is used as the material of the conductor patterns 12 and 15, but Ag-Pd is used. The method for forming the conductor patterns 12 and 15 may be plating transfer, coating, sputtering, or the like. Although Ag was used as the material of the external base electrode 18, Ag-Pd, Ni, Cu, or an alloy thereof including Ag may be used. The method of forming the external base electrode 18 is printing, vapor deposition, sputtering, or the like. Alternatively, the individual magnetic material sheets may be overlapped, the external base electrode 18 may be formed in a state before firing with a certain pressure applied, and firing may be performed simultaneously.

In the present embodiment, the spiral conductor pattern 12 and the conductor pattern 15 do not overlap with each other except for the portion where the spiral conductor pattern 12 and the conductor pattern 15 are orthogonally overlapped with each other and the inner end 12b and the inner end 15b. In other words, the coil conductor pattern located on the upper side and the coil conductor pattern located on the lower side are orthogonally overlapped with each other, and overlapped with each other to electrically connect the two (the inner end 12b and the inner end 12b). 1
5b).

With this configuration, the overlap between the two coil patterns can be further reduced, the internal stress can be prevented from being concentrated on a specific portion, and a laminated chip with less delamination can be obtained.

Further, in the present embodiment, the conductor pattern 1
2 and the width of the conductor of the conductor pattern 15 is equalized, and the width of the conductor of the conductor pattern 12 and the distance of the conductor of the conductor pattern 15 formed in a spiral are made equal. Equal.

With this configuration, the overlap between the two coil patterns can be reduced, the concentration of the internal stress at a specific location can be prevented, and a laminated chip in which delamination does not occur can be obtained. This has the effect that the area of the magnetic layer can be reduced while forming a coil with a wide conductor.

(Embodiment 2) FIG. 5 is an exploded plan view of each layer of a multilayer chip inductor according to Embodiment 2 of the present invention. FIG. 6 is a plan view of the inside of a laminated body in which the respective layers are laminated.

5 and 6, reference numeral 21 denotes a first magnetic layer made of ferrite. 22 is the first magnetic layer 2
1 is a conductor pattern which is formed in a spiral shape so as to expand outward from the center and has an end 22a and an inner end 22b drawn out at one end. Reference numeral 23 denotes a second magnetic layer having a conductive through hole 24 filled with a conductive material such as Ag. 25
Is a conductor pattern provided on the second magnetic layer 23, which is formed linearly from the center to the outside, and has an end 25a and an inside end 25b drawn to one end, and becomes a line. . Reference numeral 26 denotes a third magnetic layer disposed on a surface facing the first magnetic layer 21 and the second magnetic layer 23. The first, second, and third magnetic layers 21, 23, 26 Are laminated so that the inner end portions 22b and 25b are electrically connected via the conductive through holes 24 to form a laminate.

In the multilayer chip inductor configured as described above, a plurality of magnetic layers on which a conductor pattern for a coil of one or more turns and a conductor pattern for a coil of one or less turns are formed include a conductor for a coil of one or more turns. At least one magnetic layer on which a pattern is formed, and at least one magnetic layer on which a conductor pattern for a coil of one turn or less is formed by combining the conductor pattern for a coil of one or more turns and the coil for one turn or less. The conductor patterns are laminated so that most of the conductor patterns do not overlap at positions facing each other in the laminating direction.

[0038]

As described above, according to the present invention, by laminating so that most of the coil conductor patterns do not overlap each other in the opposing position in the laminating direction, the difference in the overall thickness is reduced, and the internal This is advantageous in that a multilayer chip inductor in which stress is not concentrated on a specific portion and delamination does not occur can be obtained.

[Brief description of the drawings]

FIGS. 1A to 1C are exploded plan views of respective layers of a multilayer chip inductor according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the inside of a multilayer body in which each layer of the multilayer chip inductor component according to the first embodiment of the present invention is stacked.

FIG. 3 is a cross-sectional view of the multilayer chip inductor according to the first embodiment of the present invention taken along line AA.

FIG. 4 is an external perspective view of the multilayer chip inductor according to the first embodiment of the present invention.

5 (a) to 5 (c) are plan views of exploded layers of the multilayer chip inductor according to the second embodiment of the present invention.

FIG. 6 is a plan view showing the inside of a multilayer body in which respective layers of the multilayer chip inductor component according to the second embodiment of the present invention are stacked.

FIGS. 7A to 7F are plan views illustrating a method for manufacturing a conventional multilayer chip inductor. FIGS.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 first magnetic layer 12 conductive pattern 12 a end of conductive pattern 12 b inner end of conductive pattern 12 second magnetic layer 14 conductive through hole 15 conductive pattern 15 a end of conductive pattern 15 b conductive pattern 15 Of the conductor pattern 16 Third magnetic layer 17 Stack 18 External base electrode 21 First magnetic layer 22 Conductor pattern 22a End of conductor pattern 22b Inner end of conductor pattern 22 23 Second magnetic layer DESCRIPTION OF SYMBOLS 24 Conductive through hole 25 Conductor pattern 25a End of conductor pattern 25 25b Inner end of conductor pattern 25 26 Third magnetic layer

Claims (2)

[Claims] A plurality of coil conductor patterns are buried in a laminate obtained by laminating a plurality of magnetic layers, and the plurality of coil conductor patterns are arranged in a laminating direction of the laminate to be electrically connected. And a plurality of magnetic layers on which one or more turns of the conductor pattern for the coil are formed, wherein the plurality of magnetic layers having one or more turns of the conductor pattern are connected to the external conductor. A laminated chip characterized in that most of the coil conductor pattern located on the upper side and the coil conductor pattern located on the lower side of the coil conductor pattern having more than one turn are laminated so that they do not overlap at positions facing each other in the laminating direction. Inductor. 2. A plurality of coil conductor patterns are buried in a laminate obtained by laminating a plurality of magnetic layers, and the plurality of coil conductor patterns are arranged in a laminating direction of the laminate to be electrically connected. At least one magnetic layer on which a coil conductor pattern of one or more turns is formed in a multilayer chip inductor in which the first and second ends of the coil conductor pattern are connected to separate external electrodes. At least one magnetic layer on which a coil conductor pattern of one or less turns is formed is placed at a position where the coil conductor pattern of one or more turns and most of the coil conductor pattern of one or less turns oppose each other in the stacking direction. A multilayer chip inductor characterized by being stacked so as not to overlap.