JP2000216760A - Data transmission system and method for transmitting clock in the same system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit consecutive data of infinite lengths by transmitting a CLK of a primary side to a secondary side and operating a data transmission system synchronously with the CLK, so as to conduct the transmission causing neither slips nor re-transmission. SOLUTION: In the primary side, an Ir transmission timing generating section 13 counts a CLK of an I.430 interface 11 for generating an interrupt timing. Furthermore, an Ir-DA interface 12 transmits/receives data with a period of I.430 frame CLK set in advance by the interrupt timing. In the secondary side, when an Ir interface 20 detects a valid reception interrupt, a CPU 22 reads the count of a CLK counter 25, controls a VCO 24 in response to the difference from a set value to match the CLK of an I.430 interface 21 with the primary side CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transmission system and a clock transmission method in the system, and more particularly to a data transmission system for transmitting synchronous data via an asynchronous data transmission unit and a clock transmission method in the system.

[0002]

2. Description of the Related Art Conventionally, this type of data transmission system has been disclosed in Japanese Patent Application Laid-Open No. 61-9059 and Japanese Patent Application Laid-Open No. 5-3276.
No. 76 is described.

First, the reproduction repeater disclosed in Japanese Patent Application Laid-Open No. 61-9059 is premised on transmitting a finite data length. Then, an elastic store corresponding to the amount of data slip generated in one transmission is prepared, and data is transmitted without falling off.

In the asynchronous signal synchronizing circuit disclosed in Japanese Patent Application Laid-Open No. 5-327676, transmission data is sampled with an asynchronous clock to detect a phase difference of CLK, and data bits are skipped by changing data sampling timing. Receive without. However, a frame whose sampling timing has been changed is received as normal data by retransmission.

[0005]

In the above-described conventional data transmission system, data is transmitted between devices using transmission clocks whose speeds are not synchronized with each other, so that a data slip occurs. . In addition, since the data slip is compensated for by retransmission or the data is temporarily stored in a buffer and then transmitted, there is a disadvantage that continuous infinite length data such as voice and image cannot be transmitted and received. In other words, such data of infinite length is transmitted and received in a continuous time, and if the transmission rate (transmission clock) is different between the transmission side and the reception side, missing or doubled data occurs, There is a disadvantage that it becomes noise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to provide a data transmission system capable of transmitting and receiving data of continuous infinite length without causing data slip. It is to provide a clock transmission method in the system.

[0007]

A data transmission system according to the present invention is a data transmission system including a primary device and a secondary device, wherein a clock of the primary device is transmitted to the secondary device. It is characterized by having done. The clock of the primary device is transmitted by performing data transmission from the primary device to the secondary device at predetermined intervals.

Another data transmission system according to the present invention is a data transmission system including a primary device and a secondary device, wherein the primary device has a predetermined period based on a predetermined clock. The secondary-side device includes a clock correction unit that corrects a clock in its own device according to an error between a timing of the notification and a clock value in its own device in response to the notification. It is characterized by the following. The notification is performed by data transmission from the primary device to the secondary device. The notifying means includes a first counter, and performs the data transmission when the count value reaches a predetermined value, and the clock correcting means includes a second counter, and determines the count value and the occurrence time of the data transmission. The clock in the own device is corrected in accordance with an error with respect to the reference count value. The clock correction unit includes a D / A conversion unit that converts error data corresponding to the error into a voltage value, and a voltage control oscillator that uses the converted voltage value as a control voltage and changes an oscillation frequency according to the control voltage. And generating a clock in the own device according to the oscillation frequency of the voltage controlled oscillator.

Still further, in another data transmission system according to the present invention, the secondary device further includes storage means for sequentially holding the error data corresponding to each of the data transmissions, and the secondary device transmits the error data from the primary device to the secondary device. When the data transmission to is stopped, the average value of the error data held in the storage means is converted into a voltage value by the D / A conversion means.

A clock transmission method according to the present invention is a clock transmission method in a data transmission system including a primary device and a secondary device, wherein the data transmission is performed from the primary device to the secondary device at predetermined intervals. Is performed to transmit the clock of the primary-side device. In addition, the primary device performs the data transmission at a predetermined cycle based on a predetermined clock, and the secondary device responds to the data transmission with the timing of the data transmission and time measurement within its own device. It is characterized in that the clock in the own device is corrected according to the difference from the value. Further, the primary device performs the data transmission when the count value of the first counter reaches a predetermined value, and the secondary device determines the count value of the second counter and a reference count at the time of occurrence of the data transmission. It is characterized in that the clock in the own device is corrected according to the difference from the value. In this case, the clock correction in the secondary device is
Converting error data corresponding to the error into a voltage value by a D / A converter, and generating a clock in the own device according to the oscillation frequency of a voltage controlled oscillator that uses the converted voltage value as a control voltage It is characterized by. Further, the secondary device sequentially holds the error data corresponding to each of the data transmissions, and when the data transmission from the primary device to the secondary device is interrupted, the average value of the held error data. Is converted into a voltage value by the D / A converter.

[0011] In short, this system is based on Ir (Infra).
red) When transmitting frame data, the following operation is performed. That is, the I.I. 430 on the secondary side. Transmitted as 430 clocks. More specifically, the primary-side Ir frame transmitting / receiving means (I.430 interface 11, Ir in FIG. 1)
A DA interface 12, an Ir transmission timing generating unit 13 and a CPU 14, a secondary Ir frame transmitting / receiving unit (the Ir-DA interface 20 and the CPU 22 in FIG. 1), and a clock synchronizing unit (I.43 in FIG. 1).
0 interface 21, CPU 22, D / A converter 23, VCO 24, CLK counter 25, and frame C
LK generation unit 26). And the primary side I
r frame transmission / reception means is the I.R. 430 is counted, and an interrupt is generated when a predetermined number of times are reached, and I.R. 4
30 data are transmitted and received.

On the other hand, when an Ir valid reception interrupt occurs, the secondary-side Ir frame transmission / reception means interrupts the CPU and simultaneously sets a specified number of I.S. 430 data is transmitted and received. The clock synchronizing means, upon receiving an Ir valid reception interrupt, outputs the I.D. signal on the secondary side. 430, the value of the CLK counter is read, and it is determined whether the number is larger or smaller than a specified number.
By controlling the value of CO, the secondary side I.O. 430 clock to the primary I.D. 430 clock.

That is, by transmitting data at a predetermined cycle, the transmission clock on the primary side is used as the transmission clock on the secondary side, whereby continuous infinite serial data can be transmitted between the primary and secondary via the asynchronous transmission unit. It is.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing a first embodiment of a data transmission system according to the present invention. Referring to FIG. 1, a primary-side data transmission device 1 transmits an I.O. 430 interface for transmitting and receiving data to and from the primary side 430 interface 11 and a primary Ir-DA (Data Associate) that transmits and receives data to and from a secondary Ir interface.
n) interface 12; 430, an Ir transmission timing generation unit 13 that counts the frame clock of the I. 430 and sends an interrupt timing to the CPU; It includes a 430 interface and a primary CPU 14 that controls transmission of Ir data. This primary-side data transmission device 1
I. Terminal device (TE; Termina) in the 430 network
l Equipment).

On the other hand, the secondary data transmission device 2
Secondary side I that transmits and receives Ir data to and from the primary side
r-DA interface 20 and the secondary I.D. 43
0 which transmits and receives data to and from the I / O interface 430 interface 21; a secondary CPU 22 which is activated by an Ir valid reception interrupt and performs secondary side CLK control and data transmission control; VCO 24 (V
old Controlled Oscilat
or), the D / A converter 23 for controlling the VCO 24, and the secondary side I.O. 430 interface 21 generates frame CLK
Generating unit 26 and C for counting the clock of VCO 24
An LK counter 25 is included. This secondary-side data transmission device 2 has I.I. Network Terminating Equipment (NT; Network Terminati)
on).

Next, the circuit operation of FIG. 1 will be described with reference to FIG. FIG. 9 is a flowchart showing the operation of the primary-side data transmission device.

First, on the primary side I.I. The 430 interface 11 is an I.430 interface. 43
0 and lower layers are set. Primary Ir-DA
The interface 12 is a data transmission device 2 on the secondary side.
Secondary-side Ir-DA interface 20 and Ir-
Negotiation is performed according to the procedure of the DA to determine the data transmission speed. At this time, I.D. 430 frames are determined (step S2).
1).

In this case, for example, 64 to 128 frames are set in consideration of the processing capability of the CPU. Here, it should be noted that if the number of frames is increased, the time required to correct the transmission rate on the secondary side becomes longer.

Next, the I.D. determined at this time. The number of transmitted 430 frames is set in the Ir transmission timing generator 13 (step S22). The above is the initial setting operation on the primary side.

The Ir transmission timing generation unit 13 outputs the I.I. I.430 coming from the I.430 interface 11 43
When the frame CLK of 0 is counted and the count value reaches a preset count value, an interrupt is issued to the primary CPU 14 (step S23). Primary side CP
Upon receiving the interrupt, U14 makes a request for Ir data transmission / reception to the primary-side Ir-DA interface 12 (step S24). The above is the constant control operation on the primary side.

Primary-side Ir-DA interface 1
2 receives the data transmission / reception request and receives the data transmission / reception request. 4
The data from the I.30 interface 11 is set in advance by negotiation. 430 frames CLK are transmitted. At the same time, the secondary Ir-DA
Received from the interface 20 and 430
It is passed to the interface 11 as received data.

FIG. 3 is a flowchart showing the operation of the secondary-side data transmission device in FIG.

On the secondary side of the secondary-side data transmission device 2, 430 interface 21 is connected to the secondary I.430 interface.
A lower layer is provided for the 430 network. I.1 determined by negotiation with the primary-side data transmission device 1
430 (step S3).
1) The secondary CPU 22 recognizes the value of the CLK counter 25 to be counted in one Ir frame transmission (step S32). At the same time, D / A
Data is set to converter 23 so as to have the value. The above is the initial setting operation on the secondary side.

The D / A converter 23 is connected to the secondary side CP.
The control voltage is output to the VCO 24 based on the data from U22. The frame CLK generation unit 26 includes the VCO 24
On the secondary side I.C. The frame CLK is generated and supplied to the 430 interface 21.

Upon receiving the Ir data from the primary data transmission device 1, the secondary Ir-DA interface 20 issues a valid reception interrupt to the secondary CPU 2.
When the number is incremented by 2 (step S33 → S34), the secondary CPU 22 reads the value of the CLK counter 25. Further, the secondary-side Ir-DA interface 20 receives the data received from the primary-side data transmission device 1 and transmits the data to the secondary-side I.D. 430 interface 21. At the same time, the secondary I.I. 4
The transmission data from the interface 30 is transmitted to the primary Ir-DA interface 12.

Next, it is determined whether or not the value of the CLK counter matches the set value (step S34). When the read value is the same as the set value, the secondary CPU 22 writes the same value as the value previously written to the D / A converter 23 to the D / A converter 23 (step S3).
7).

When the value of the CLK counter 25 is larger than the set value, it means that the CLK is fast. Therefore, the D / A converter 23 controls the D / A converter 23 so that the CLK value of the VCO 24 is delayed by the deviation. The data is written (step S36). Similarly, when the value of the CLK counter 25 is small, it means that the CLK is slow.
Data is written to the / A converter 23 (step S35). The above is the constant control operation on the secondary side.

The above operation is repeated, and the I.I.
The operation CLK of the 430 interface is matched. As a result, no data slip occurs between the primary and the secondary. Further, the data is not slipped due to the synchronization of the clock, and the accumulation and retransmission in the buffer are eliminated, so that continuous infinite data can be transmitted.

Here, as shown in FIG. 4, the D / A converter 23 has a latch 23a for holding data sent from the CPU 22, and a D / A converter for converting the output of the latch 23a to an analog voltage. And an A conversion unit 23b. In this case, for example, if an analog voltage of 0 to 5 V is represented by 12 bits, CP
The 12-bit data output from U22 is temporarily held in the latch 23a, and the held output data is stored in the D / A converter 2
In 3b, it is converted into an analog voltage.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 5, the secondary-side data transmission device 2 includes a secondary-side Ir-DA interface 20 for transmitting and receiving Ir data to and from the primary-side, and a secondary-side I.D. 430 interface that transmits and receives data to and from the I.430 interface 430 interface 21 and Ir
Is activated by the valid reception interrupt of
Secondary CPU 22 that performs control and data transmission control
And the secondary side I. V which is the oscillation source of CLK at 430
CO / 24 and D / A converter 23 for controlling VCO
And from the VCO CLK to the secondary I. A frame CLK generator 26 for generating a clock for the 430 interface 21; a CLK counter 25 for counting the clock of the VCO;
7 and an interrupt timing monitoring timer 28 for monitoring whether the valid reception interrupt has come normally.

Next, the operation of the secondary data transmission device 2 in FIG. 5 will be described with reference to the flowchart in FIG.

On the secondary side of the secondary-side data transmission device 2, 430 interface 21 is connected to the secondary I.430 interface.
A lower layer is provided for the 430 network. I.1 determined by negotiation with the primary-side data transmission device 1
430 (step S5).
1) The secondary CPU 22 recognizes the value of the CLK counter 25 to be counted in one Ir frame transmission (step S52). At the same time, data for setting data to the D / A converter 23 to have the value is written to the memory 27. The above is the initial setting operation on the secondary side.

The D / A converter 23 outputs a control voltage to the VCO 24 based on the data in the memory 27. The frame CLK generator 26 receives the CLK from the VCO 24 and outputs the I.F. 430 interface 21 with frame C
Generate and supply LK.

Upon receiving the Ir data from the primary data transmission device 1, the secondary Ir-DA interface 20 issues a valid reception interrupt to the secondary CPU 2.
When the number is incremented by 2 (step S53 → S54), the secondary CPU 22 reads the value of the CLK counter 25 (step S53). The secondary-side Ir-DA interface 20 receives data from the primary-side data transmission device 1 and transmits the data to the secondary-side I.D. 430 interface 21. At the same time, the secondary I.I. The transmission data from the 430 interface 21 is transmitted to the primary-side Ir-DA interface 12 (step S55).

Next, it is determined whether the value of the CLK counter matches the set value (step S56). When the read value is the same as the set value, the secondary CPU 22 writes the same value as the value previously written to the memory 27 (step S61).

When the value of the CLK counter 25 is larger than the set value, it means that the CLK is fast. Therefore, data is written to the memory 27 so that the CLK value of the VCO 24 is delayed by the amount of the shift. The D / A converter 23 is controlled (step S60). Similarly, CLK
When the value of the counter 25 is small, it means that the CLK is slow, so that the data is written to the memory 27 so that the value of the CLK of the VCO 24 becomes faster by the deviation.
/ A converter 23 is controlled (step S59). The above is the constant control operation on the secondary side. The above is the constant control operation on the secondary side.

The above operation is repeated, and the I.I. The operation CLK of the 430 interface is matched.

Here, when a transmission failure occurs due to interruption or the like in Ir transmission between the primary data transmission device 1 and the secondary data transmission device 2, the interrupt timing monitoring timer 28 of the secondary data transmission device 2 sets the Ir Timeout occurs because no valid reception interrupt is received (steps S53 → S57). Interrupt timing monitoring timer 2
8 informs the secondary CPU 22 that the time-out has occurred. The secondary CPU 22 reads the past data held in the memory 27 and writes the average value into the memory 27 as control data of the D / A converter 23 (step S57 → S58).

Thus, even if the data is interrupted, the secondary side I.D. 430CLK is prevented from being largely shifted.

In each of the above embodiments, I
Although the case of performing r transmission has been described, it is apparent that the present invention can be applied to transmission in which the transmission unit is constant in data communication in which frame transmission is not limited to this transmission. However, in the case of Ir transmission, since the number of frames to be transmitted on negotiations is determined before starting communication between the primary and secondary, it is not necessary to add a procedure for determining the number of frames. There are benefits.

By the way, in this system, a clock is transmitted between the primary device and the secondary device. That is, the clock of the primary device is transmitted by performing data transmission from the primary device to the secondary device at predetermined intervals. Then, the primary device performs data transmission at a predetermined cycle based on a predetermined clock, and the secondary device responds to the data transmission by calculating an error between the timing of the data transmission and a clock value in the device. The clock in the own device is corrected according to the above. Further, the primary device performs data transmission when the count value of the counter in the device has reached a predetermined value, and the secondary device has determined the difference between the count value of the counter in the device and the reference count value at the time of data transmission. The clock in the own device is corrected according to the error.

In this case, the correction of the clock in the secondary device is performed by converting the error data corresponding to the error into a voltage value by a D / A converter, and oscillating a voltage-controlled oscillator using the converted voltage value as a control voltage. It generates a clock in its own device according to the frequency. In the second embodiment,
The secondary device sequentially holds the error data corresponding to each data transmission, and when the data transmission from the primary device to the secondary device is stopped, the average value of the held error data is converted by the D / A converter. They are converted to voltage values.

As described above, when synchronous data is transmitted via the asynchronous data transmission unit, the conventional apparatus provides a buffer for data slips or retransmits data for slipped frames to transfer the data. On the other hand, in the present invention, the primary side CLK is transmitted to the secondary side, and by operating in synchronization with the CLK, the transmission without slipping or retransmission is performed. As a result, continuous infinite data transmission can be performed.

[0046]

As described above, according to the present invention, the I.I. Synchronizing the 430 transmission clock has the effect that data slip does not occur between the primary and secondary. In addition, there is an effect that continuous infinite-length data can be transmitted by preventing the data from slipping due to the synchronization of the clock and eliminating accumulation and retransmission in the buffer.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transmission system according to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the primary-side transmission device in FIG.

FIG. 3 is a flowchart for explaining an operation of a secondary transmission device in FIG. 1;

FIG. 4 is a block diagram showing an example of the internal configuration of the D / A converter in FIG.

FIG. 5 is a block diagram illustrating a configuration of a data transmission system according to a second embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation of the secondary transmission device in FIG. 5;

[Explanation of symbols]

 1 Primary data transmission device 2 Secondary data transmission device 11 Primary data transmission device 430 interface 12 Primary-side Ir-DA interface 13 Ir transmission timing generator 14 Primary-side CPU 20 Secondary-side Ir-DA interface 21 Secondary-side I.D. 430 interface 22 Secondary side CPU 23 D / A converter 24 VCO 25 CLK counter 26 Frame CLK generator 27 Memory 28 Interrupt timing monitoring timer

Claims (14)

[Claims] 1. A data transmission system including a primary device and a secondary device, wherein the clock of the primary device is transmitted to the secondary device. 2. The data transmission according to claim 1, wherein the clock of the primary device is transmitted by performing data transmission from the primary device to the secondary device at predetermined intervals. system. 3. A data transmission system including a primary device and a secondary device, wherein the primary device includes a notifying unit for notifying at a predetermined cycle based on a predetermined clock, A data transmission system, wherein the secondary device includes a clock correction unit that corrects a clock in the device in response to an error between a timing of the notification and a time value in the device in response to the notification. 4. The data transmission system according to claim 3, wherein the notification is performed by data transmission from the primary device to the secondary device. 5. The notifying means includes a first counter,
When the count value reaches a predetermined value, the data transmission is performed. The clock correction means includes a second counter, and the clock correction means automatically performs the data transmission according to an error between the count value and a reference count value at the time of the data transmission. The data transmission system according to claim 4, wherein a clock in the device is corrected. 6. The D / A conversion means for converting error data corresponding to the error into a voltage value, the clock correction means using the converted voltage value as a control voltage, and adjusting the oscillation frequency according to the control voltage. 6. The data transmission system according to claim 5, further comprising: a voltage-controlled oscillator that changes, and generating a clock in said own device according to an oscillation frequency of said voltage-controlled oscillator. 7. The secondary device further includes storage means for sequentially holding the error data corresponding to each of the data transmissions, and the data is stored in the storage means when data transmission from the primary device to the secondary device is interrupted. 7. The data transmission system according to claim 6, wherein an average value of the held error data is converted into a voltage value by said D / A conversion means. 8. The clock according to claim 1, wherein: The data transmission system according to any one of claims 1 to 7, wherein the clock is 430 clocks. 9. A clock transmission method in a data transmission system including a primary device and a secondary device, wherein data is transmitted from the primary device to the secondary device at predetermined intervals.
A clock transmission method comprising transmitting a clock of the primary device. 10. The primary device performs the data transmission at a predetermined cycle based on a predetermined clock, and the secondary device responds to the data transmission with the timing of the data transmission and its own device. 10. The clock transmission method according to claim 9, wherein the clock in the own device is corrected according to an error from the clock value inside the device. 11. The primary device performs the data transmission when the count value of the first counter reaches a predetermined value, and the secondary device determines the count value of the second counter and the time of occurrence of the data transmission. 11. The clock transmission method according to claim 10, wherein the clock in the own device is corrected in accordance with an error with respect to the reference count value. 12. The clock correction in the secondary-side device includes the steps of: converting error data corresponding to the error into a voltage value using a D / A converter; and using the converted voltage value as a control voltage. The clock transmission method according to claim 10, wherein a clock in the own device is generated according to an oscillation frequency. 13. The secondary device sequentially holds the error data corresponding to each of the data transmissions,
13. The D / A converter converts an average value of the held error data into a voltage value when data transmission from the primary device to the secondary device is interrupted. Clock transmission method as described. 14. The clock according to claim 1, wherein: 14. The data transmission system according to claim 9, wherein the clock is 430 clocks.