JP2000287131A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a picture from bleckening due to the incidence of a very strong light without deteriorating the luminous sensitivity. SOLUTION: The voltage of a signal line 13 for a non-signal period is sampled by means of a timing pulse DSP to discriminate whether or not it is a pixel with an ultrahigh luminous quantity based on whether or not the sampled voltage is within a prescribed voltage range by a comparator 18. A pulse synthesizer 19 receives a timing pulse DRP for replacing level for the non-signal period, generates a signal replaced pulse RP that is positive with respect to the pixel with an ultrahigh luminous quantity and gives it to a selector 20. The selector 20 usually outputs a voltage SIG on the signal line but outputs a voltage Vr from a voltage generator 21 in the pixel of the ultrahigh luminous quantity and replaces a reset voltage with the voltage Vr.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device used for a video camera, an electronic still camera, and the like.
In particular, the present invention relates to an amplification type solid-state imaging device having an amplifier structure in an imaging region, that is, a solid-state imaging device using an active pixel sensor.

[0002]

2. Description of the Related Art In recent years, amplifying type solid-state imaging devices, especially CM
OS (Complementary Metal Oxi)
A de-Semiconductor image sensor has attracted attention.

This type of image sensor has low power consumption and can operate with a single power supply.
This is because a high SN ratio as high as that of the D (Charge Coupled Device) type can be obtained. Further, in this type of image sensor, necessary signal processing circuits can be configured on a chip. There is a CMOS image sensor called a photogate type having a very low noise.

In this photogate type CMOS image sensor, when a very large amount of light enters, the output signal suddenly disappears, so that a phenomenon that the portion appears black as if no light enters at all is apparent. It has become. That is, as shown in FIG. 21, when the amount of incident light becomes very large, the output signal amount sharply decreases. This phenomenon is referred to herein as a blackening phenomenon.

The operation and problems of the conventional photogate type image sensor will be described below with reference to the drawings.
FIG. 22 shows a semiconductor structure and an output circuit for one pixel, FIG. 23 shows an equivalent circuit thereof, and FIG. 24 shows a signal waveform in each part of the circuit.

In FIG. 24, a period a shows a signal waveform when normal light is incident, and a period b shows a waveform when very large light is incident (when a very large amount of light is incident).

First, the operation in the period a will be described. The reset pulse RS is the reset transistor Q3
From the time (t1) when the signal is applied to the gate of the read transistor Q4 to the time (t2) when the read pulse TG is applied to the gate of the read transistor Q4.
ST). The time when the next reset pulse RS is applied to the gate of the reset transistor Q3 from the time t2
Until (t3), it is a signal period (BST) in which a signal is input.

In the no-signal period (NST), when the reset pulse RS is applied to the gate of the transistor Q3 in FIG. 23 to turn on Q3, the thermal noise (Tn1) due to the on-resistance of the transistor Q3 turns off Q3.
The voltage of the thermal noise Tn2 described later is held at the gate of the transistor Q1 to generate a noise voltage. As a result, that voltage is generated at the output SIG. This voltage corresponds to the non-signal period NS.
At the end of T, it is clamped by the clamp circuit 251. In the signal period BST, the photodiode Q2
Then, electric charges are stored according to the intensity of light.

When the read pulse TG is applied to the read transistor Q4, this charge is
1 to the gate node Gn, and a voltage change due to the capacitance C occurs. With this voltage change, the output signal SIG of the transistor Q1 changes, and the voltage is sampled and held by the sample and hold circuit 252 by the sample pulse SP, and is taken out as the output signal OUT.

This operation will be described in more detail. In the photogate type, the capacitance C of the gate node Gn of the amplifier (amplifying transistor) Q1 can be made smaller than the capacitance C2 of the photodiode Q2. The reset transistor Q3 is turned on by applying a reset pulse RS generated every horizontal period, and the gate node G
The voltage of n is initialized to the voltage of the voltage source Vdd.

At this time, the thermal noise Tn1 generated per bandwidth B due to the conduction resistance of the transistor Q3 is obtained by the following equation.

(Equation 1) Here, k is a Boltzmann constant,
T is the absolute temperature, and R is the value of the conduction resistance of the transistor Q3.

The thermal noise Tn1 is caused by the noise bandwidth 1 / (4) due to the capacitance C and the conduction resistance R of the transistor Q3.
CR). Therefore,
Regardless of the conduction resistance of the transistor Q3, the capacitance C is always
, A thermal noise Tn2 depending only on.

The thermal noise Tn2 is as follows when converted into a charge amount.

(Equation 2) As a result, lower noise can be detected as the capacitance C is smaller.

The thermal noise charge Tn2 is determined by the transistor Q
3 is kept off when it is turned off, and is output as a voltage during the non-signal period by the transistor Q1. Thereafter, a read pulse TG is applied to the read transistor Q4, and the charge stored in the photodiode Q2 is transferred to the gate node Gn of the transistor Q1, and a voltage change is caused by the capacitance C. This voltage change is caused by the signal voltage SlG added from the source of the transistor Q1 to the voltage during the no-signal period.
And input to the clamp circuit 251.

Therefore, by detecting the voltage change at the time of reading the signal of the transistor Q1, it is possible to detect only the voltage of the signal component, and the signal from the output terminal OUT to SN
A signal with a good ratio can be obtained.

This is a so-called correlated double sampling process in which a clamp circuit 251 clamps a voltage in a no-signal period based on a clamp pulse CP, and a sample-and-hold circuit 252 extracts a signal voltage in a signal period based on a sample pulse SP. It can be realized by applying.

However, when strong light such as the reflected light of the sun enters the above-described circuit, the blackening phenomenon occurs in which the portion looks black. Therefore, an output signal with respect to the amount of light incident on the photodiode Q2 was measured. As a result, when the amount of incident light becomes tens of thousands of times the amount of saturated light, FIG.
As shown in FIG. 1, it was found that when the output signal was extremely reduced and no light entered, the result was the same, and as a result, it appeared black.

In pursuit of the cause, the n-type semiconductor regions 253 and 255 and the p-type semiconductor substrate 2 shown in FIG.
It has been found that the cause is the parasitic NPN transistor Q5 generated during the period 54.

That is, in FIG. 22, the photodiode Q2 is formed between the n-type semiconductor region 253 and the p-type semiconductor substrate 254. At this time, the n-type semiconductor region 253 and p
The parasitic NPN transistor Q5 is formed between the semiconductor substrate 254 of the type and the n-type semiconductor region 255 of the gate node Gn. Therefore, when the photodiode Q2 is irradiated with an extremely large amount of light, power is generated similarly to the solar cell, and a negative voltage is generated in the n-type semiconductor region 253 from the p-type semiconductor substrate 254. Then, the parasitic NPN shown in FIG.
A forward bias is applied between the base and the emitter of the transistor Q5, and a state occurs in which a collector current flows.

Due to the above reasons, the period a in FIG.
In the non-signal period NST, the output signal SIG of the amplifying transistor Q1 should be constant after initialization. However, actually, the non-signal period NST of the period b
Has an amplifying transistor (buffer transistor) Q1
The signal SlG, which should be obtained by being amplified by the transistor Q1, gradually decreases the voltage of the gate node Gn of
As shown by a waveform 241 in FIG. Therefore, it has been found that when the voltage clamped by the clamp circuit 251 decreases and the correlated double sampling processing is performed to reduce noise, a phenomenon occurs in which a signal suddenly disappears at a certain very large light amount. That is, as shown in FIG. 21, when the amount of incident light becomes very large, the output signal sharply drops, and a phenomenon that the portion appears black on the screen occurs.

This phenomenon is caused by the parasitic NPN transistor Q5
Of the transistor Q,
This can be prevented by adding an element for voltage clipping to the photodiode Q2 so that 5 does not conduct. However, when such an element is provided in each of the pixels having a limited area, the area of the photodiode Q2 must be reduced, and the light sensitivity which is the most basic characteristic of the solid-state imaging device is reduced. Occurs.

[0022]

As described above, in a solid-state image pickup device using a conventional amplifying type image element, a blackening phenomenon in which a pixel that receives extremely intense light such as reflected light of the sun appears black. There was a problem that occurred. Further, if an element for that purpose is provided in the pixel region in order to prevent this phenomenon, there is a problem that the light sensitivity is reduced.

Therefore, a main object of the present invention is to provide a solid-state imaging device using an active pixel sensor which does not cause the output signal to drop even when light exceeding the saturation light quantity is incident and the portion on the screen does not become black. It is to provide a device.

Another main object of the present invention is to provide a solid-state imaging device using an active pixel sensor whose light sensitivity does not decrease.

[0025]

According to a basic feature of the present invention, there is provided a photodetector for converting incident light into an electric signal, and an electric signal converted by the photodetector. A solid-state imaging device having a plurality of active pixel sensors for outputting a signal voltage to a common signal line, each of which has an amplifier for reading out a pixel, and a voltage output to the signal line after the active pixel sensor is reset. Voltage detecting means for detecting that the voltage drops more rapidly than in a normal case, and reset voltage setting means for using a predetermined voltage as a reset voltage when the voltage detecting means detects a drop in voltage. Become.

According to the present invention, first, it is detected whether or not the voltage during the non-signal period, that is, the voltage at the time of resetting falls more rapidly than in the normal case. Next, when the reset voltage drops rapidly, it is determined that an extremely large amount of light has entered, and the reset voltage is replaced with another voltage or the reset voltage is clipped, and these voltages are replaced with the actual reset voltage. Use instead of Since the replacement reset voltage is not so small as compared with the actual reset voltage at the time of incidence of a very large amount of light, it is possible to prevent the occurrence of a blackening phenomenon of an image which has conventionally occurred at the time of a very large amount of light.

According to another basic feature of the present invention, a photodetector for converting incident light into an electric signal and an amplifier for reading out the electric signal converted by the photodetector are provided for each pixel. In a solid-state imaging device equipped with a plurality of active pixel sensors that output a signal voltage to a signal line, detecting whether a reset voltage output to the signal line is within a predetermined range after the active pixel sensor is reset. Provided is a solid-state imaging device comprising: voltage detecting means; and voltage replacing means for replacing the reset voltage with a predetermined voltage when the reset voltage is detected to be within a predetermined range.

According to the present invention, when the reset voltage when the active pixel sensor is reset is within a predetermined range, it is determined that a very large amount of light is incident and the reset voltage is replaced with a predetermined voltage.

According to still another feature of the present invention, each pixel has a photodetector for converting incident light into an electric signal and an amplifier for reading out the electric signal converted by the photodetector,
In a solid-state imaging device equipped with a plurality of active pixel sensors that output a signal voltage to a common signal line, a reset replacement voltage connected to the signal line, including a structure having a transistor instead of a photodetector of the active pixel sensor Provided is a solid-state imaging device comprising: a generation circuit; a current source connected to the signal line; clamp means for clamping a voltage of the signal line; and sample and hold means for sampling and holding an output of the clamp circuit. I do.

According to still another feature of the present invention, each pixel has a photodetector for converting incident light into an electric signal and an amplifier for reading out the electric signal converted by the photodetector,
In a solid-state imaging device equipped with a plurality of active pixel sensors that output a signal voltage to a common signal line, the voltage output to the signal line after the active pixel sensor is reset drops more sharply than usual. Voltage detecting means for detecting a voltage drop, a voltage clipping means for clipping the voltage when the voltage detecting means detects a drop in voltage, and a reset voltage replacement using the voltage clipped by the voltage clipping means as a reset voltage. And a solid-state imaging device comprising:

According to the present invention, the clipped voltage is used as a reset voltage when an extremely large amount of light is incident.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a solid-state imaging device for explaining the principle of the present invention in which a reset voltage is replaced with a predetermined voltage. A plurality of active pixel sensors 1a, 1b,.
, The amplifiers 3a, 3b,... And the switches 4a, 4b,.
Consisting of These active pixel sensors 1a, 1b,.
The signal lines 5 are commonly connected to the terminals of the switches 4a, 4b,.

The signal line 5 is connected to the voltage detector 6 and one terminal of the changeover switch 7. A predetermined voltage Vref is applied to the other terminal of the changeover switch 7.
The output terminal 8 of the changeover switch 7 normally outputs the voltage of the signal line 5.

Each of the switches 4a, 4b,... Of the active pixel sensors 1a, 1b,. For example, when the switch 4a is closed, first, in the first half, the amplifier 3a is reset, and a reset voltage is taken out to the signal line 5 which is commonly connected. This period is called a non-signal period.

Next, a voltage corresponding to the light incident on each photodiode 2a appears on the signal line 5. This period is called a signal period. During the no-signal period, the active pixel sensor 1
The signal component of the image sensor is obtained by a change in the voltage extracted from the active pixel sensor 1a to the signal line 5 during the signal period with respect to the voltage extracted from the signal line 5 to the signal line 5.

In the no-signal period, since the reset voltage is used, almost the same voltage should appear in any active pixel sensor. However, in an active pixel sensor in which large light enters the photodiode, the voltage appearing on the signal line 5 drops rapidly as described above.

The voltage detector 6 receives the voltage output to the signal line 5 during the non-signal period, and when the voltage is very small unlike the normal reset voltage,
The changeover switch 7 is controlled so that the voltage Vr is applied to the output terminal 8.
ef is output. During the signal period, the output terminal 8 is connected to the signal line 5 again.

In this case, the voltage during the no-signal period becomes Vref, and the voltage change between the no-signal period and the signal period increases. Therefore, even if strong light enters, the output voltage becomes very low, and the image at that point does not appear black.

In addition, the replacement of the voltage when strong light is incident is performed after reading the signal from each active pixel sensor, and an additional circuit is not provided for each active pixel sensor. Therefore, the solid-state imaging device according to the present invention can maintain light sensitivity. (Embodiment 1) A first embodiment of the present invention to be described hereinafter has a circuit for generating a normal no-signal potential, and when an incident light is determined to be a very large light amount, a signal is output from this circuit. Is a replacement for FIG. 2 is a block diagram for explaining the first embodiment of the present invention, and FIG. 3 is a timing chart for explaining its operation.

Referring to FIG. 2, an active pixel sensor PE comprising a photodiode 11, an amplifier 12, and a switch 14.
Corresponds to each pixel, and the signal output via the switch 14 flows to the signal line 13. FIG. 2 shows only the active pixel sensors PE1 and PE2 corresponding to two pixels, but other active pixel sensors are similarly provided. Each electrical component is written by adding the numbers of these active pixel sensors to the above numbers.

The amplifier 12 corresponds to a circuit including transistors Q3 to Q5 in addition to the amplifying transistor Q1 in FIG. Switch 14 corresponds to transistor Q6 to which the line switching signal is applied in FIG.

The solid-state imaging device shown in FIG. 2 has a plurality of active pixel sensors PE, a signal line 13 commonly connected to switches of the active pixel sensors PE, and a timing signal for supplying a timing signal to each circuit. A reset pulse RS and a readout pulse TG are applied to the amplifier 12 of the active pixel sensor PE in response to a control signal from the generator 15 and the timing signal generator 15.
A driver 16 for applying a line switching signal LS to the switch 14 of the first embodiment, and a signal appearing on the signal line 13 are converted by a timing pulse DSP output from the timing signal generator 15.
A sample and hold circuit 17 for sampling and holding, and a comparator 1 for comparing whether the held voltage is within a predetermined voltage range
8, a pulse synthesizer 19 that receives a timing pulse DRP output from the timing signal generator 15 and generates a signal replacement pulse RP during a non-signal period when a very large amount of light is incident;
A selector 20 for switching between outputting the actual signal voltage on the signal line 13 or outputting a predetermined voltage at the time of incidence of a very large amount of light, and a voltage generator 21 for generating a predetermined voltage to be replaced at the time of incidence of a very large amount of light. , The voltage selected by the selector 20 and the timing signal generator 15
A clamp circuit 22 that clamps at the timing of the clamp pulse CP from
It comprises a sample and hold circuit 23 which samples and holds at the timing of the sample pulse SP from the timing signal generator 15.

The light detected by each photodiode 111, 112,... Of each active pixel sensor PE is amplified by the corresponding amplifier 121, 122,. Each switch 141, 142,... Of each image sensor PE
Indicates a line switching signal LS generated by the driver 16 driven by the output of the timing signal generator 15
, LS2,..., On / off control.
When these switches are closed, the signal voltage SIG detected by the photodiode of the active pixel sensor PE and amplified by the amplifier is output to the signal line 13.

The switch 141 of the active pixel sensor PE1 in FIG. 2 is closed from the time (t10) to the time (t11) by the line switching signal LS1 in FIG. Accordingly, during this time, the output of the amplifier 121 of the active pixel sensor PE1 appears on the signal line 13 as SIG. The switch 142 of the active pixel sensor PE2 is closed from time (t12) to time (t19) by the line switching signal LS2 in FIG. During this time, the amplifier 1 of the active pixel sensor PE2
22 only appears on signal line 13 as signal SIG,
The switches of the other active pixel sensors are in the off state and do not affect the output of the signal line 13.

Therefore, only the operation of the active pixel sensor PE2 will be described in the period from (t12) to (t19).
There is no signal period from time (t12) to time (t17), and there is a signal period from time (t17) to time (t19). The reset pulse RS output from the driver 16 is applied to the amplifier 122 at time (t13) to reset the amplifier, and the reset voltage when there is no signal appears on the signal line 13 as the signal SIG.

The signal SIG appearing on the signal line 13 is sampled and held in the sample and hold circuit 17 at the time (t14) based on the timing pulse DSP for sampling shown in FIG. Assuming that a sampled voltage of the signal SIG is Vs2, this voltage Vs2 means a voltage at the time of reset, that is, during a no-signal period. The sampled and held voltage Vs2 is checked by the comparator 18 to see if it is within a predetermined voltage range.

The predetermined voltage range is a voltage at which it is determined that an extremely large amount of light has entered, and is set as a low voltage that cannot be obtained during a normal reset.

If the voltage of the sampled voltage Vs2 in the non-signal period is within the predetermined range, it is determined that an extremely large amount of light has entered the photodiode 112 of the active pixel sensor PE2 selected at that time. The pulse synthesizer 19
In response to the comparison result of the comparator 18, the signal replacement pulse R
P is supplied to the selector 20. That is, when it is determined that the voltage Vs2 (reset voltage) sampled in the comparator 18 is within the predetermined range and that an extremely large amount of light has entered, the pulse synthesizer 19 returns to the time t15 during the no signal period of the timing signal generator 15 at the time t15. Upon receiving the timing pulse DRP for replacing the level, it generates a signal replacement pulse RP during a no-signal period when the light intensity is extremely large, and supplies the signal replacement pulse RP to the selector 20. In the selector 20, the correction signal CS for outputting the voltage Vr of the voltage generator 21 during the non-signal period of the pixel receiving the super-large light amount.
Is output.

At the time point (t15) during which the correction signal CS is output from the selector 20, the clamp circuit 22
The voltage Vr is clamped by the clamp pulse CP. Therefore, in a pixel where an extremely large amount of light enters,
The actual sampled voltage Vs when the predetermined voltage Vr is no signal
2 will be used instead.

In the signal period, a read pulse TG2 is applied to the amplifier 122 at time (t17), and a signal corresponding to the amount of light received by the photodiode 112 is read out to the signal line 13 via the amplifier 122. The voltage of this signal level passes through the selector 20 and passes through the clamp circuit 2.
At 2, it is clamped by the clamp pulse CP.
The clamped voltage is sampled and held by the sample pulse SP in the sample and hold circuit 23 at the time (t18). Therefore, the clamp circuit 22 and the sample-and-hold circuit 23 detect the signal voltage based on the voltage difference between the non-signal period and the signal period of the original signal line 13 in the pixel at the time of the normal light amount, so that low noise can be maintained. In a pixel where an extremely large amount of light is incident, the voltage Vr is clamped by the clamp pulse CP, and is switched to the voltage SIG of the signal line 13 during a signal period, and a signal output equivalent to a saturation signal voltage is obtained.

Further, since this signal correction block functions with one circuit per signal line, the area of the photodiode is not reduced, so that the basic characteristics of the solid-state imaging device are not deteriorated and the chip area is slightly increased. Only needs to be done. (Embodiment 2) In the above embodiment, a voltage to be replaced when an extremely large amount of light enters is determined in advance, and a circuit for generating the voltage is separately provided. However, it is also possible to hold a reset voltage in the case of a normal light quantity, and to replace this voltage in the case of a very large light quantity. Such an embodiment of the present invention will be described below.

FIG. 4 is a block diagram for explaining the solid-state imaging device 40 of this embodiment, and FIG. 5 is a timing chart for explaining the operation thereof. The same components as those in the above embodiment are denoted by the same reference numerals. FIG. 5 also shows the waveform of each part in the case of the above embodiment.
And almost the same.

The circuit characteristic of the embodiment shown in FIG. The sample-and-hold circuit 31 samples and holds the voltage Vs0 appearing on the signal line 13 during the non-signal period when the normal light amount is applied at the timing of the replacement sampling pulse RSP in FIG. For example, attention is paid to the no-signal period in the first half when the active pixel sensor PE1 in FIG. 4 is selected by the line switching signal LS1.

At this time, when the timing pulse DSP is applied to the sample and hold circuit 17, the voltage appearing on the signal line 13 is sampled and held, and the voltage at this time is set to Vs1. The voltage Vs1 at this time is usually a voltage in a non-signal period when the amplifier of the active pixel sensor is reset. The comparator 18 determines that the voltage Vs1 is not within the predetermined voltage range.

Next, the active pixel sensor PE2 is selected by the line switching signal LS2. At time (t12), the line switching signal LS2 is applied to each switch, and the switch 142 is closed. At time (t13), the reset pulse RS is applied to the amplifier 122 to be reset. At this time, the reset voltage appearing on the signal line 13 is supplied to the sample and hold circuit 31 by the replacement sampling pulse RS.
It is held when P is applied.

From the waveform SIG and the replacement sampling pulse RSP shown in FIG. 5, it can be seen that the reset voltage in this case is Vs0.

At time (t14), the timing pulse D
SP is applied to the sample-and-hold circuit 17, and the signal on the signal line 13 is taken out. The voltage at this time is Vs0
From Vs2. The voltage Vs2 is recognized by the comparator 18 as a low voltage falling within a predetermined range, and the signal replacement pulse RP is applied from the pulse synthesizer 19 to the selector 20 at time (t15). The selector 20 selects the output of the sample and hold circuit 31,
The output voltage Vs0 of the sample hold circuit 31 is the signal CS
Is sent to the clamp circuit 22.

As a result, as shown by the waveform CS in FIG. 5, the output signal CS of the clamp circuit normally outputs the voltage of the signal line 13 and the output voltage Vs of the sample and hold circuit 17.
Only when the timing pulse DR becomes extremely small.
The voltage is replaced with the voltage Vs0 in the range of P and output. The signal CS is clamped by the clamp pulse CP in the clamp circuit 22, sampled and held by the sample pulse SP in the sample and hold circuit 23, and is output from the output terminal OU.
Output to T. In this case, the difference between the voltage Vs0 and the voltage at the time of the signal is extracted as a true signal, so that the signal is sufficiently large.

In this embodiment, the amplifiers 121, 122,
Are supplied to the sample-and-hold circuit 31 during the initialization voltage output period from..., And are sampled based on the replacement sampling pulse RSP from the timing signal generator 15, and the output thereof is output. Voltage Vs0
Is a voltage corresponding to the no-signal voltage Vr in the embodiment of FIG.

Instead of providing the sample-and-hold circuit 31 in the embodiment of the present invention, an amplifier having no photodiode in the pixel is simultaneously formed in the process of forming the active pixel sensor, and the output voltage of this amplifier is extremely large. It can also be used as the non-signal voltage Vr at the time of light quantity incidence. (Embodiment 3) In the above embodiment, when an extremely large amount of light enters, the actual reset voltage at the time of no signal is replaced with a predetermined voltage by using a selector. However, the problem at the time of incidence of a very large amount of light can be solved by the pulse amplitude modulation circuit and the maximum value circuit without using a selector.

FIG. 6 is a block diagram of the present invention relating to such an embodiment, and FIG. 7 is a timing chart for explaining the operation. The same circuit components as those shown in FIG. 4 are denoted by the same reference numerals and symbols in the block diagram of FIG.

A feature of the solid-state imaging device 60 of this embodiment is that the signal replacement pulse RP output from the pulse synthesizer 19 during the no-signal period when the light intensity is extremely large is changed by the pulse amplitude modulation circuit 5.
1 is modulated, its output DRK and the voltage SIG of the signal line 13 are output.
In the maximum value circuit 52, and supplies the maximum value to the clamp circuit 22.

The pulse amplitude modulation circuit 51 generates a signal replacement pulse DRK shown in FIG. This signal replacement pulse D
RK is a signal having a value of a non-signal period voltage when a normal light amount enters only during a non-signal period of a pixel having an extremely large light amount. The maximum value circuit 52 includes a signal replacement pulse DRK output from the pulse amplitude modulation circuit 51 and a signal SI appearing on the signal line 13.
G is input.

Since the maximum value circuit 52 outputs the higher voltage of these two inputs, as shown in FIG. 7, the output of the pulse amplitude modulation circuit 51 is only between time (t15) and time (t17). The signal CS replaced by Va is output.

Therefore, the non-signal period voltage can be replaced with the predetermined voltage only in the pixel having a very large light quantity, the low noise property can be maintained in the normal pixel, and a signal output equivalent to the saturation signal voltage can be obtained in the pixel with a very large light quantity. Can be Fourth Embodiment In the third embodiment, the pulse amplitude modulation circuit and the maximum value circuit are provided outside the active pixel sensor. However, these circuits can be omitted by wired OR connection.

Such an embodiment will be described with reference to FIGS. FIG. 8 is a block diagram showing the overall configuration of the solid-state imaging device of this embodiment, and FIG. 9 is a waveform diagram of each part of the solid-state imaging device. This solid-state imaging device 80 has a plurality of active pixel sensors CIS1, CIS2,.

Each of these active pixel sensors has a photodiode PH and an amplifying transistor Q for amplifying a signal.
81, a reset transistor Q82 for resetting the amplification transistor Q81, a reading transistor Q83 for reading a signal, and a switch transistor Q84 for turning on and off the output of the amplification transistor Q81.

When referring to the code of each component of each active pixel sensor, the number of the active pixel sensor is added after the code of each component. For example, the sign of the switch transistor of the active pixel sensor CIS1 is Q841.

In this embodiment, in addition to these active pixel sensors, a reset reference voltage circuit CISV having substantially the same configuration as the active pixel sensor is provided. The reset reference voltage circuit CISV has the same configuration as the active pixel sensor except that the photodiode is replaced by a series connection of a transistor Q80 and a voltage source V80. The gate of transistor Q80 is connected to signal line 83. The transistors of the reset reference voltage circuit CISV corresponding to the transistors Q81 to Q84 in the active pixel sensor are denoted by Q810 to Q840.

The signal line 83 is connected to each switch transistor of the active pixel sensor and the reset transistor Q840 of the reset reference voltage circuit CISV. A current source I80 is connected between the signal line 83 and the ground.

The solid-state imaging circuit 80 includes the reset reference voltage circuit CISV and the active pixel sensors CIS1 and CIS.
2, a signal line 83, a current source I80, a timing signal generation circuit 81 for outputting timing pulses DRP and DSP, a reset pulse RS, a read pulse TGn controlled by the timing signal generation circuit 81, and line switching. It comprises a driver 82 for generating a signal LSn, a clamp circuit 85, and a sample and hold circuit 87.

Line switching signals LS1, LS shown in FIG.
2 is applied to the switch transistors Q841 and Q842 of the active pixel sensors CIS1 and CIS2, and these switches are sequentially closed. The reset pulse RS is generated by the reset reference voltage circuit CISV and the reset transistors Q820, Q821, Q822,... Of each active pixel sensor.
At the same time. Therefore, all these circuits are reset.

The read pulses TG1, TG2,...
Is the readout transistor Q83 of each active pixel sensor.
1, Q832,... A timing pulse DSP for sampling is applied to the read transistor Q830 of the reset reference voltage circuit CISV, and a timing pulse DRP is applied to the switch transistor Q840.

Between time (t10) and time (t11), switch transistor Q841 is turned on by line switching signal LS1. During this time, the reset transistor Q821 is turned on and reset, the readout transistor Q831 is turned on and the voltage when there is no signal is buffered by the amplifying transistor Q811 and the buffered voltage is read out to the signal line 83.

Here, the operation of the reset reference voltage circuit CISV will be described. It is assumed that, for example, a high voltage of the output of the active pixel sensor CIS1 is output to the signal line 83. At this time, the potential of the base of transistor Q80 increases, and this transistor is turned on. In this state, the transistor Q830
When a positive timing pulse DSP is input to this transistor, this transistor also conducts, and the base of the transistor Q820 becomes low potential. Next, when the timing pulse DRP enters the switch transistor Q840, the output potential of the active pixel sensor CIS1 appears on the signal line 83 and is clamped by the clamp circuit.

On the other hand, if the potential of the signal line 83 is low,
The gate potential of transistor Q80 decreases, and this transistor is turned off. In this state, the transistor Q8
The gate potential of the amplifying transistor Q810 remains high even when the timing pulse DSP is input to the transistor 30, and this high potential appears on the signal line 83 when the timing pulse DRP is applied to the transistor Q840. As a result, when the timing pulse DRP is applied, the output potential of the selected active pixel sensor and the reset reference voltage circuit CISV
The output potentials are compared, and the signal line 83 becomes the higher potential.

Next, from time (t12) to time (t19)
Up to the case where the active pixel sensor CIS2 is selected. In this state, the reset pulse R at time (t13)
By S, the active pixel sensor CIS2 and the reset reference voltage circuit CISV are reset. Active pixel sensor C
When an extremely large amount of light enters IS2, the potential appearing on the signal line 83 decreases rapidly. Therefore, transistor Q8
The gate potential of 0 becomes low, and this transistor is turned off. Therefore, the transistor Q810 becomes conductive, and a high voltage appears on the signal line 83 at the time (t15) to (t17) when the timing pulse DRP is applied to the transistor Q840. This is the signal CS.

As shown in FIG. 9, the timing pulse DR
Only during the period when P is added, the reset reference voltage circuit CISV
, I.e., the normal active pixel sensor when there is no signal. This signal CS
Is clamped by a clamp pulse in a clamp circuit 85 and sampled by a sampling pulse SP in a sample and hold circuit 87.

In this embodiment, in the case of a source follower using an N-type MOS transistor as an amplifying transistor, the supply of signal current is automatically stopped when a high voltage is applied to its output. Therefore, in this embodiment, it can be considered that the functions of the amplitude modulation circuit and the maximum value circuit are realized by the wired OR connection having the open source structure. (Embodiment 5) In the above-described embodiment, when the output at the time of no signal becomes extremely small due to the input of an extremely large amount of light, the output is replaced with a predetermined voltage. But in such a case,
Before the output voltage decreases, the voltage can be clipped and the voltage can be used as a no-signal voltage. FIG.
0 is a block diagram of the solid-state imaging device of this embodiment, and FIG. 11 is a timing chart for explaining the operation.

In the solid-state imaging device 100, the active pixel sensors DE1, DE2,..., The photodiodes PD1, PD2,. , And switch transistors QS1, QS2,...

The amplification transistors QM1, QM2,.
Are connected to a power supply 1010. One end of each of the switch transistors QS1, QS2,.
012, and a current source 1015 is connected to the signal line 1012. Further, to reduce fixed pattern noise, the coupling capacitor 101
6 and a switch 1017 and a clamp circuit 1019
Is connected to a current source 1015 and this output has an amplifier 1018
Is connected.

Further, a clip circuit 1020 which is a feature of this embodiment is provided. Clip circuit 1020
Are connected in series to a resistor 1031 connected to the power supply 1010, a current source 1032 connected to the power source 1010, one end of which is connected, a clip transistor 1033 having a gate connected thereto, and a current path of the clip transistor. It consists of a clip control transistor 1034.

In the solid-state imaging device having such a structure, a difference signal corresponding to the light amount can be obtained by comparing the integrated voltage corresponding to the amount of incident light and the black reference voltage at the time of reset as described below. Even when the amount of incident light exceeds a predetermined amount, a constant reset potential is guaranteed by the clip circuit. First, an integrated voltage according to the amount of incident light is obtained.

That is, when a positive voltage is applied to the line switching signal SEL1, the source of the amplification transistor QM1 is connected to the signal line 1012 via the switching transistor QS1. At this time, since the clip control signal SELD is at a low potential, the clip control transistor 1034 is cut off. Accordingly, a signal of the photodiode PD1 corresponding to the amount of incident light is output to the signal line 1012. This signal voltage is connected to the capacitor 1016 and the switch 1
By clamping with the clamp circuit 1019 of 017, an integrated voltage corresponding to the amount of incident light is held.

Next, a reset pulse RS1 is applied to reset the photodiode PD1 to a predetermined potential in order to obtain a black reference signal, and the reset transistor QR
Turn 1 on. In the non-signal period, the clip control signal SE
When the LD becomes high potential, the clip control transistor 1034 turns on. If the signal amount incident on the photodiode PD1 is equal to or less than the saturation light amount, the potential change of the photodiode PD1 during the black reference signal period is slight. The gate potential of the amplification transistor QM1 is
Since the voltage is higher than the gate voltage of the gate 33, the black reference voltage of the amplification transistor QM1 is output to the signal line 1012, and as a result, an output signal with a good S / N ratio is obtained.

Next, when a high voltage is applied to the line switching signal SEL2, the source of the amplification transistor QM2 is connected to the signal line 1012. At this time, since the clip control signal SELD has a low potential, the clip control transistor 1
034 is cut off. Therefore, the signal of the photodiode PD2 on which an excessive amount of light is incident is transmitted to the signal line 1
012. This voltage is applied to the clamp circuit 1019
, The saturation signal voltage is maintained.

Next, the photodiode PD2 is reset to a predetermined voltage by applying the reset pulse RS2 to the reset transistor QR2. When the light amount is excessive, when the reset transistor QR2 is turned off, the voltage of the signal line 1012 rapidly decreases.

In the no-signal period, the clip control signal SEL
D is supplied with a high potential and the clip control transistor 10
34 is on, when the gate potential of the amplification transistor QM2 becomes lower than the gate voltage of the clip transistor 1033,
3, a current flows to the signal line 1012, and the black reference voltage is clipped to a predetermined level.

Therefore, the photoelectric conversion characteristics shown in FIG.
As shown in the signal voltage Vb at the voltage Vsig of 1
Since the reduction of the signal at the saturation light amount or more is stopped, the conventional output reduction such as a broken line can be avoided. This makes it possible to solve the abnormal phenomenon that the output of the image sensor decreases when the incident light amount exceeds the saturation amount. (Embodiment 6) FIG. 12 is a block diagram of a solid-state imaging device according to another embodiment of the present invention.

The solid-state imaging device according to this embodiment further includes reading transistors QD1, QD2,... And photodiodes PD1, PD2,. Transistor QM
, QM2,... Are provided between the gates.
Also, the switch transistors QW1, QW2,.
Are connected between the drains of the amplification transistors QM1, QM2,... And the power supply 1210.

Thus, the reference voltage when there is no signal can be generated without using a photodiode on which light is incident.

As shown by light 1301 in FIG.
There is oblique incident light in the reading transistor portion, or the charge generated in the substrate is diffused and flows into the detection node as shown by an arrow 1302.

The clipping circuit includes, for example, a resistor 1231 connected to a power supply 1210 for generating a voltage slightly lower than the initialization voltage of the photosensitive pixel, a current source 1232 connected to the resistor 1231 and having one end provided thereto, and a black reference signal. , A transistor 1235 that performs a switching operation by a timing signal RSD, and a transistor 1236 that performs a switching operation by a timing signal TGD. Clip transistor 12
The gate of 33 is biased to a low potential by a transistor 1235 that is turned on simultaneously with the reset transistor QR. Therefore, the signal line potential is clipped below a predetermined level due to the light sensitivity of the detection node during the black reference voltage period.

At the same time that the pulse is applied to the read transistor QD, the transistor 1236 conducts.
Thus, the gate of the clip transistor 1233 becomes the ground potential, the transistor 1233 is cut off regardless of the signal line voltage, and the signal voltage in the signal period is not clipped. For this reason, the black reference signal is suppressed to a constant value as in the fifth embodiment, so that it is possible to avoid a decrease in the output potential at a saturation light amount or more. Embodiment 7 Next, a solid-state imaging device according to another embodiment will be described with reference to the drawings. FIG. 15 is a block diagram of a solid-state imaging device according to still another embodiment. In this embodiment, the pixel element is constituted by one enhancement-type n-channel MOS transistor having a photoelectric conversion function.

That is, in FIG. 15, this solid-state image pickup device includes a photosensitive transistor PDT connected to a power supply 1542.
, PDT2,..., A switching element 1544 connected to these current paths, and a current limiting circuit 1545
, A capacitor 1546 connected thereto, a switching element 1549, a switching element 1547 provided in parallel with these and connected to a current path of the photosensitive transistors PDT1, PDT2,..., And connected thereto. Capacitor 1548 and switching element 1550
And a differential amplifier 1551 receiving the voltages of the capacitors 1546 and 1548 and outputting the difference between the two voltages.
Consisting of

In such a configuration, when light strikes the photosensitive transistor PDT, electron-hole pairs are generated, and electrons move to the substrate side and holes move below the gate electrode by a bias voltage applied to the element. . The holes that have moved under the gate electrode increase the channel charge of the MOS transistor and are extracted as a signal current. Pixel selection is
This is performed by applying a higher voltage to the SEL terminal than other transistors. By applying a higher potential to the gate, holes accumulated under the gate are swept out to the substrate,
Since the reset operation can be performed, driving can be performed according to the timing chart shown in FIG. This element also
Since the black reference level is directly output from the photosensitive element, the black reference level has a small light sensitivity.

As indicated by the broken line Iintd in the graph of FIG. 17, the black reference level monotonically increases even when the signal current is more than the light amount at which the signal current is saturated because the light sensitivity is lower than the signal output period. The signal current Iints closes the switch 1547,
The signal is integrated by the capacitor 1548 and converted into a signal voltage. The black reference current is selected by the switch 1544, subjected to current limitation by the current limiting circuit 1545, and
d, which is accumulated in the capacitor 1546 to obtain a black reference level. This difference is obtained by the differential amplifier 1551 and becomes a signal output.

As shown in FIG. 18, the current limiting circuit 1545 can be constituted by a JFET 1861 connected to a constant current diode and a shunt transistor 1862.
Thereby, the current limiting circuit 1545 is added to the black reference signal current.
, The current is limited, so that it is possible to prevent the level from dropping at the saturation light amount or more. (Embodiment 8) Further, regarding another embodiment of the present invention,
This will be described with reference to the drawings. FIG. 19 is a circuit diagram of the solid-state imaging device according to this embodiment, and FIG. 20 is a timing chart for explaining the operation of the solid-state imaging device.

The basic configuration of this embodiment is the same as that of the seventh embodiment except that the current limiting circuit 1545 is replaced with a black reference signal integrating capacitor 1546 in parallel.
A clip transistor 1975 and a power supply 1976 are provided. Thus, the clip level is
76. As a result, clipping is performed so that the black reference signal is lower than a predetermined level.
It is possible to prevent a monotonous decrease of the output signal at the operation timing as shown in FIG. It is possible to prevent a phenomenon that an image becomes dark when a high-luminance subject is imaged. 19, the same numbers as those in FIG. 15 indicate the same electric components.

In the above description, the case where the signal charges are electrons has been described. However, when the signal charges are holes, the same effect can be obtained by inverting the pulse modulation polarity and replacing the maximum value circuit with the minimum value circuit. Can be obtained.

The present invention can be applied not only to a device using a CMOS image sensor but also to a solid-state image pickup device generally using a MOS image sensor.

[0103]

As described above, according to the solid-state imaging device of the present invention, the reset voltage in the non-signal period is detected to determine whether or not the light amount is extremely large. Alternatively, the voltage before the voltage is reduced is clipped and used as the reset voltage. Therefore, it is possible to prevent the blackening phenomenon of the image that has occurred when the light amount is extremely large.

Further, according to the present invention, since the correction of a signal generated when an extremely large amount of light is received is performed using a circuit common to each pixel, the area of the phototransistor is not sacrificed and the light sensitivity is reduced. There is no.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining the principle of the present invention.

FIG. 2 is a block diagram for explaining a first embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment of FIG. 2;

FIG. 4 is a block diagram for explaining a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the embodiment of FIG. 4;

FIG. 6 is a block diagram for explaining a third embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the embodiment in FIG. 6;

FIG. 8 is a block diagram for explaining a fourth embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the embodiment in FIG. 8;

FIG. 10 is a block diagram for explaining a fifth embodiment of the present invention.

FIG. 11 is a timing chart for explaining the operation of the embodiment in FIG. 10;

FIG. 12 is a block diagram for explaining a sixth embodiment of the present invention.

FIG. 13 is a diagram for explaining a conventional improved black level light sensitivity.

FIG. 14 is a timing chart for explaining the operation of the embodiment in FIG. 12;

FIG. 15 is a block diagram for explaining a seventh embodiment of the present invention.

FIG. 16 is a timing chart for explaining the operation of the embodiment in FIG. 15;

FIG. 17 is a view showing the photoelectric conversion characteristics of the solid-state imaging device according to the embodiment shown in FIG. 15;

18 is a diagram showing a circuit configuration example of a current limiting circuit 1545 in FIG.

FIG. 19 is a block diagram for explaining an eighth embodiment of the present invention.

FIG. 20 is a timing chart for explaining the operation of the embodiment in FIG. 19;

FIG. 21 is an input / output characteristic diagram for explaining a conventional problem when an extremely large amount of light is emitted.

FIG. 22 is a diagram showing a cross-sectional structure of a pixel of a conventional active pixel sensor and a subsequent circuit.

FIG. 23 is an equivalent circuit diagram of the structure of the active pixel sensor of FIG. 22.

FIG. 24 is a timing chart for explaining a problem of the conventional solid-state imaging device.

[Explanation of symbols]

1a, 1b,..., PE1, PE2,.
S2,..., DE1, DE2,... Active pixel sensor, 2a, 2b,.
, PH1, PH2, ..., photodiode, 3a, 3b, ..., 121, 122, ..., amplifier, 4a, 4b, ... switch, 5, 13, 83, ...
-Signal line, 6-Voltage detector, 7-Changeover switch, 15, 81-Timing signal generator, 16, 8
2 ... Driver, 17, 23, 31, 87 ... Sample hold circuit, 18 ... Comparator, 19 ... Pulse synthesizer, 20 ... Selector, 21 ... Voltage generator, 22 , 85 ... clamp circuit, 51 ... pulse amplitude modulation circuit, 52 ... maximum value circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA10 AB01 BA14 CA02 DB01 DD12 FA06 5C024 AA01 BA01 CA12 CA15 FA01 FA11 GA01 GA22 GA31 GA33 HA03 HA06 HA18

Claims (9)

[Claims] A plurality of active elements, each of which has a photodetector for converting incident light into an electric signal and an amplifier for reading the electric signal converted by the photodetector for each pixel, and outputs a signal voltage to a common signal line. In a solid-state imaging device equipped with a pixel sensor, voltage detection means for detecting that a voltage output to the signal line after the active pixel sensor is reset drops more rapidly than usual, A reset voltage setting means for using a predetermined voltage as a reset voltage when a voltage drop is detected by the solid-state imaging device. 2. A method according to claim 1, wherein each of the pixels includes a photodetector for converting incident light into an electric signal and an amplifier for reading the electric signal converted by the photodetector, and outputs a signal voltage to a common signal line. In a solid-state imaging device equipped with a pixel sensor, voltage detection means for detecting whether a reset voltage output to the signal line after resetting the active pixel sensor is within a predetermined range, and the voltage detection means A solid-state imaging device comprising: a voltage replacement unit that replaces the reset voltage with a predetermined voltage when it is detected that the reset voltage is within a predetermined range. 3. The voltage replacing means has a voltage generator for generating a constant voltage. When the voltage detecting means detects that the reset voltage is within a predetermined range, the voltage replacing means changes the signal voltage. The solid-state imaging device according to claim 2, wherein the output voltage is replaced with an output voltage of the voltage generator. 4. The voltage replacing means has a sample and hold circuit for sampling and holding a reset voltage of the active pixel sensor, and the voltage detecting means detects that the reset voltage is within a predetermined range. 3. The solid-state imaging device according to claim 2, wherein the signal voltage is replaced with a voltage held by the sample and hold circuit. 5. The voltage replacement means includes a pulse amplitude modulation circuit and a maximum value circuit for obtaining a maximum value of an output of the pulse amplitude modulation circuit and a voltage of a signal line. 3. The solid-state imaging device according to claim 2, wherein the pulse amplitude modulation circuit is operated when it is detected that is within a predetermined range. 6. The active pixel sensor includes a photodiode that receives light and converts the light into an electric signal, an amplifying transistor that amplifies an output signal of the photodiode, and outputs an output of the amplifying transistor to the signal line. The solid-state imaging device according to any one of claims 1 to 5, comprising a switch transistor for turning on / off the transistor, a transistor for reset, and a transistor for signal reading. 7. The apparatus according to claim 2, wherein said voltage detecting means detects whether a reset voltage is equal to or lower than a predetermined voltage.
6. The solid-state imaging device according to any one of Items 1 to 5, 8. A plurality of active elements each having a photodetector for converting incident light into an electric signal and an amplifier for reading the electric signal converted by the photodetector for each pixel, and outputting a signal voltage to a common signal line. A solid-state imaging device equipped with a pixel sensor, comprising a structure having a transistor instead of a photodetector of the active pixel sensor, a reset replacement voltage generation circuit connected to the signal line, and a current source connected to the signal line A solid-state imaging device comprising: clamp means for clamping a voltage of the signal line; and sample and hold means for sampling and holding an output of the clamp circuit. 9. A plurality of active elements, each having a photodetector for converting incident light into an electric signal and an amplifier for reading the electric signal converted by the photodetector for each pixel, and outputting a signal voltage to a common signal line. In a solid-state imaging device equipped with a pixel sensor, voltage detection means for detecting that the voltage output to the signal line after the active pixel sensor is reset falls more rapidly than usual, A solid-state imaging device comprising: voltage clipping means for clipping a voltage drop when a voltage drop is detected by the device; and reset voltage replacement means for using the voltage clipped by the voltage clipping means as a reset voltage. apparatus.