JP2002290835A - Solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging device which can suppress the effect of element temperature exerted on the output. SOLUTION: The effect of a dark current flowing from a photodiode PD which is affected by the element temperature and the threshold voltage of a MOS transistor T2 can be reduced by placing the MOS transistor T2 in a potential state corresponding to the element temperature by supplying a DC voltage VPS-L corresponding to the element temperature detected by a shading pixel provided in a voltage generating circuit 10x to the source of the MOS transistor T2 when the device is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having photoelectric conversion means for outputting a signal obtained by logarithmically converting the amount of incident light.

[0002]

2. Description of the Related Art Solid-state imaging devices are not only compact, lightweight and low power consumption, are free from image distortion and image sticking, and are resistant to environmental conditions such as vibration and magnetic fields. LSI (Large Scale)
Since it can be manufactured by a process common to or similar to that of an integrated circuit, it has high reliability and is suitable for mass production. For this reason, solid-state imaging devices having pixels arranged in a line are widely used in facsimile and flatbed scanners, and solid-state imaging devices having pixels arranged in a matrix are widely used in video cameras, digital cameras, and the like. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading out (extracting) photocharges generated by a photoelectric conversion element. The CCD type has a drawback that the dynamic range is narrow because the photoelectric charge is transferred while being accumulated in the potential well. On the other hand, the MOS type uses the charge accumulated in the pn junction capacitance of the photodiode as M
Reading is performed through an OS transistor.

In order to widen the dynamic range of such a MOS type solid-state imaging device, the present applicant has proposed a photosensitive means capable of generating a photocurrent according to the amount of incident light, a MOS transistor for inputting the photocurrent, There has been proposed a solid-state imaging device having a bias means for biasing the MOS transistor to a state in which a subthreshold current can flow, and performing a logarithmic conversion of a photocurrent (Japanese Patent Laid-Open No. 19276/1991).
No. 4).

[0004]

Although such a solid-state imaging device has a wide dynamic range, the threshold characteristics of MOS transistors provided for each pixel may be different, and the sensitivity may be different for each pixel. There are cases. Therefore, it is necessary to take measures such as holding an output obtained by previously irradiating bright light (uniform light) having a uniform luminance as correction data for correcting the output of each pixel when capturing an image of a subject. . However, there are problems that it is complicated for the operator to irradiate each pixel using an external light source, and that the exposure cannot be uniformly performed well. Further, when the uniform light irradiation mechanism is provided in the imaging device, there is a problem that the configuration of the imaging device becomes complicated.

Accordingly, the applicant of the present invention has detected the threshold voltage of a MOS transistor which operates in the sub-threshold region by flowing a photocurrent at the time of image pickup, and detects the threshold voltage of the MOS transistor. We are studying a solid-state imaging device having a circuit configuration that detects a variation in sensitivity and removes a noise component caused by the variation in the detected sensitivity from image data obtained by imaging. However, in the image data obtained by removing the noise component due to the variation in sensitivity as described above, the image temperature obtained by imaging at the same time has no variation in each pixel, but the element temperature changes. As a result, the photoelectric conversion characteristics are different, so that a component due to the element temperature in the imaging device is included in the image data.

Therefore, for example, as shown in FIG. 17, when each pixel has a photodiode P and a MOS transistor T which operates in a sub-threshold region during imaging in which the gate and the drain are connected to the anode of the photodiode P, When an image is taken at an element temperature set as a normal temperature, the image data is generated with respect to the illuminance of light incident on the pixel.
It varies almost logarithmically.

However, for example, in such a pixel, when the element temperature drops from room temperature, the amount of dark current flowing from the photodiode P decreases, and the potential of the region under the gate of the MOS transistor T after resetting decreases. When the current value of the photocurrent generated in the photodiode P is small, the MOS transistor T does not operate in the sub-threshold region and operates in a state close to the offset. Therefore, as shown in FIG. 18, a linear conversion component appears when the amount of incident light is lower than when imaging is performed at room temperature.

Conversely, when the element temperature rises from room temperature, the amount of dark current flowing from the photodiode P increases, and the amount of charge accumulated in the MOS transistor T increases. When the potential of the lower region becomes high and an image of a subject with high illuminance is taken, the same state as when an image of a subject with low illuminance at room temperature is taken. Therefore, as shown in FIG. 18, even if the same incident light is applied, the output from the pixel is lower than when imaging is performed at room temperature.

In view of such a problem, an object of the present invention is to provide a solid-state imaging device capable of suppressing the influence of the element temperature on the output.

[0010]

According to a first aspect of the present invention, there is provided a solid-state imaging device, comprising: a photosensitive element for generating an electric signal corresponding to an amount of incident light; and an electric signal from the photosensitive element. A solid-state imaging device including a plurality of pixels that include a transistor that is input and operates in a sub-threshold region and that has a photoelectric conversion unit that converts the electric signal into a natural logarithm; a voltage corresponding to a temperature of the solid-state imaging device; , And the potential state of the transistor is set by biasing the transistor with a voltage output from the voltage generation circuit.

In such a solid-state imaging device, the transistor operating in the subthreshold region is a MOS transistor.
When a transistor is used, its potential state is changed according to the element temperature. As described above, by changing the potential state of the transistor according to the element temperature, the influence of the dark current of the photosensitive element, which varies with the element temperature, the threshold voltage of the transistor, and the like can be reduced.

According to a second aspect of the present invention, a temperature detector having the same configuration as that of the photoelectric conversion unit is provided in the voltage generation circuit to detect an element temperature, and further, no light is incident on the temperature detector. Light may be shielded as described above.

According to a third aspect of the present invention, there is provided a solid-state imaging device, comprising: a photosensitive element for generating an electric signal according to the amount of incident light; and a first transistor having a first electrode and a control electrode connected to one electrode of the photosensitive element. And resetting the plurality of pixels according to the temperature of the solid-state imaging device, the plurality of pixels outputting an electric signal obtained by natural logarithmic conversion of the electric signal from the control electrode of the first transistor. And a second voltage for operating the first transistor in a sub-threshold region to a second electrode of the first transistor. The first voltage is applied to the second electrode of the first transistor from the voltage generation circuit, and when the pixel performs an imaging operation, the first voltage is applied from the voltage generation circuit to the first electrode. Wherein the second voltage to the second electrode of the transistor is applied.

According to such a solid-state imaging device, at the time of reset, the first voltage applied to the second electrode of the first transistor by the voltage generation circuit changes according to the element temperature. Therefore, when the first transistor is a MOS transistor, the potential state of the first transistor after reset changes according to the element temperature, so that the dark state of the photosensitive element that changes according to the element temperature, the threshold voltage of the transistor, etc. The effect can be reduced.

According to a fourth aspect of the present invention, the voltage generating circuit includes a photosensitive element having the same characteristics as the photosensitive element provided in the pixel, and a first electrode provided on one electrode of the photosensitive element.
A first transistor having an electrode connected to the control electrode, an inverting buffer having an input connected to a connection node between the first electrode and the control electrode of the first transistor, and outputting the first voltage; A drive circuit for selecting and outputting a voltage and the second voltage may be provided, and light may be shielded so that light does not enter the photosensitive element.

According to a fifth aspect of the present invention, there is provided a solid-state imaging device, wherein a photosensitive element for generating an electric signal according to the amount of incident light, a first electrode and a control electrode are connected to one electrode of the photosensitive element, and a sub-threshold is provided. A first transistor biased to operate in a region, and a second transistor having a second electrode connected to a control electrode of the first transistor, wherein the electrical signal is a natural logarithmic conversion of the electrical signal. A plurality of pixels that output signals from a control electrode of the first transistor, a voltage generation circuit that outputs a voltage corresponding to the temperature of the solid-state imaging device to the first electrode of the second transistor,
When the pixel is reset, the second transistor is turned on, a voltage from the voltage generation circuit is applied to a control electrode of the first transistor, and the pixel performs an imaging operation At this time, the second transistor is turned off.

According to such a solid-state imaging device, the voltage applied to the control electrode of the first transistor from the voltage generation circuit through the second transistor at the time of reset changes according to the element temperature. Therefore, when the first transistor is a MOS transistor, the potential state of the first transistor after reset changes according to the element temperature, so that the dark state of the photosensitive element that changes according to the element temperature, the threshold voltage of the transistor, etc. The effect can be reduced.

According to a sixth aspect of the present invention, the voltage generating circuit includes a photosensitive element having the same characteristics as the photosensitive element provided in the pixel, and a first electrode provided on one electrode of the photosensitive element.
A first transistor having an electrode and a control electrode connected thereto, and an input side connected to a connection node between the first electrode and the control electrode of the first transistor, and a voltage output to a first electrode of the second transistor in the pixel And the light-receiving element may be shielded so that light does not enter the photosensitive element.

According to a seventh aspect of the present invention, in the solid-state imaging device according to any one of the third to sixth aspects, the pixel includes a first electrode connected to one electrode of the photosensitive element. A third transistor in which a second electrode is connected to a first electrode and a control electrode of the first transistor, wherein when the pixel is reset, the third transistor is turned off; Is characterized in that the third transistor is turned on when performing an imaging operation. With this configuration, it is possible to prevent a photocurrent from flowing from the photosensitive element into the first transistor at the time of reset.

According to an eighth aspect of the present invention, in the solid-state imaging device according to any one of the third to seventh aspects, the pixel includes a control electrode provided on a first electrode and a control electrode of the first transistor. And a fourth transistor which amplifies a voltage appearing at a control electrode of the first transistor and outputs the amplified voltage from a second electrode. The fourth
By using a MOS transistor as a source follower transistor, a signal obtained at the time of imaging or at the time of reset can be amplified and output.

According to a ninth aspect of the present invention, in the solid-state imaging device, a photosensitive element for generating an electric signal corresponding to the amount of incident light, a second electrode connected to one electrode of the photosensitive element, and operating in a sub-threshold region. And a second transistor having a first electrode connected to a second electrode of the first transistor, and an electrical signal obtained by natural logarithmic conversion of the electrical signal. A plurality of pixels that output from the second electrode of the first transistor, and a voltage generation circuit that outputs a voltage corresponding to the temperature of the solid-state imaging device to the control electrode of the first transistor;
When the pixel is reset, the second transistor is turned on, a voltage from the voltage generation circuit is applied to a second electrode of the first transistor, and when the pixel performs an imaging operation, The second transistor is turned off.

According to such a solid-state imaging device, the voltage applied from the voltage generation circuit to the control electrode of the first transistor changes according to the element temperature. Therefore, when the first transistor is a MOS transistor, the potential state of the first transistor after reset determined by the reset DC voltage applied to the second electrode changes according to the element temperature. The influence of the dark current of the photosensitive element, which varies with temperature, the threshold voltage of the transistor, and the like can be reduced.

According to another aspect of the present invention, the voltage generating circuit includes a photosensitive element having the same characteristics as the photosensitive element provided in the pixel, and a second electrode provided on one electrode of the photosensitive element. A first transistor connected to the first transistor, an inverting buffer having an input connected to a second electrode of the first transistor, and outputting a voltage to a control electrode of the first transistor in the pixel; The light may be shielded so as not to enter the light.

According to the present invention, there is provided a solid-state imaging device, wherein a photosensitive element for generating an electric signal corresponding to the amount of incident light, a second electrode is connected to one electrode of the photosensitive element, and the solid-state imaging device operates in a sub-threshold region. A plurality of pixels having a first transistor biased so as to output an electric signal obtained by natural logarithmic conversion of the electric signal from a second electrode of the first transistor; And a voltage generation circuit that outputs a voltage corresponding to the above to the control electrode of the first transistor, wherein the pixel is reset by changing the voltage applied to the first electrode of the first transistor. It is characterized by.

According to such a solid-state imaging device, the voltage applied to the control electrode of the first transistor by the voltage generation circuit at the time of reset changes according to the element temperature.
Therefore, when the first transistor is a MOS transistor, the potential state of the first transistor after reset determined by the reset DC voltage applied to the first electrode changes according to the element temperature. The influence of the dark current of the photosensitive element, which varies with temperature, the threshold voltage of the transistor, and the like can be reduced.

According to a twelfth aspect of the present invention, the voltage generating circuit includes a photosensitive element having the same characteristics as the photosensitive element provided in the pixel, and a second electrode provided on one electrode of the photosensitive element. A first transistor connected to the first transistor, an inverting buffer having an input connected to a second electrode of the first transistor, and outputting a voltage to a control electrode of the first transistor in the pixel; The light may be shielded so as not to enter the light.

According to a thirteenth aspect of the present invention, in the solid-state imaging device according to any one of the ninth to twelfth aspects, the pixel has a first electrode connected to a second electrode of the first transistor. And a third transistor having a second electrode connected to one electrode of the photosensitive element,
When the pixel is reset, the third transistor is turned off, and when the pixel performs an imaging operation,
The third transistor is turned on. With this configuration, it is possible to prevent a photocurrent from flowing from the photosensitive element into the first transistor at the time of reset.

A solid-state imaging device according to a fourteenth aspect is the solid-state imaging device according to any one of the ninth to thirteenth aspects, wherein the pixel has a control electrode connected to a second electrode of the first transistor. A fourth transistor for amplifying a voltage appearing at a second electrode of the first transistor and outputting the amplified voltage from a second electrode. By using the fourth transistor as a source-follower MOS transistor, a signal obtained at the time of imaging or at the time of reset can be amplified and output.

[0029]

Embodiments of the present invention will be described below.

<Structure of solid-state imaging device> First, an example of the structure of the solid-state imaging device of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a configuration of a part of a two-dimensional MOS type solid-state imaging device according to the present invention. In the figure, G11
Gmn indicate pixels arranged in a matrix (matrix arrangement). Numeral 2 denotes a vertical scanning circuit, and a row (line) 4-
,..., 4-n are sequentially scanned. Reference numeral 3 denotes a horizontal scanning circuit which outputs output signal lines 6-1 and 6-2,
.., The photoelectric conversion signals derived in 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. Furthermore, 10
Is a voltage generation circuit, and a bias supply line 9-1,
A bias voltage is applied to each pixel through 9-2,..., 9-m. For each pixel, the lines 4-1 and 4-
, 4-n and output signal lines 6-1, 6-2, ..., 6-
m, power supply line 5, bias supply lines 9-1, 9-
In addition to 2,..., 9-m, other lines (for example, clock lines) are also connected, but these are omitted in FIG.

The output signal lines 6-1, 6-2,..., 6
As shown, one set of N-channel MOS transistors Q1 is provided for each m. Taking the output signal line 6-1 as an example, the gate of the MOS transistor Q1 is connected to the DC voltage line 7, and the drain is connected to the output signal line 6-1.
And the source is connected to line 8 of the DC voltage VPS '. The output signal lines 6-1, 6-2,.
The image data at the time of imaging of each pixel and the correction data at the time of resetting, which are output through 6-m, are sequentially supplied to the sample hold circuit 11.

For this sample and hold circuit 11,
Image data and correction data are output and sampled and held for each row. The sampled and held image data and correction data are output to the output circuit 12 for each column, and the output circuit 12 corrects the image data based on the correction data so that noise components due to sensitivity variations are removed. You. Therefore, the output circuit 12 serially outputs image data in which the sensitivity variation of each pixel is corrected for each pixel.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor T3 for outputting a signal based on the photocharge generated in those pixels is provided. The connection relationship between the MOS transistor T3 and the MOS transistor Q1 is as shown in FIG. Where MOS
DC voltage VPS 'connected to the source of transistor Q1
And the DC voltage VPD 'connected to the drain of the MOS transistor T3 is VPD'> VPS ', and the DC voltage VPS' is, for example, a ground voltage (ground).

In this circuit configuration, a signal is input to the gate of the upper MOS transistor T3, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1.
Therefore, the lower MOS transistor Q1 is equivalent to a resistor or a constant current source, and the circuit of FIG. 2 is a source follower type amplifier circuit. In this case, the MOS transistor T
It may be considered that what is amplified and output from 3 is a current.
The configuration shown in FIGS. 1 and 2 is a configuration common to the first to fifth embodiments described below.

With the configuration shown in FIG. 2, a large signal can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Further, the MOS transistor Q1 forming the load resistance portion of the amplifier circuit is not provided in the pixel, and the output signal line 6 to which a plurality of pixels arranged in the column direction are connected is connected.
, 6-2,..., 6-m, the number of load resistances or constant current sources can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.

<First Embodiment> A first embodiment applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 3 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment.

In FIG. 3, a pn photodiode PD
Form a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to the drain of the MOS transistor T1, and the source of the MOS transistor T1 is connected to the drain and gate of the MOS transistor T2 and the gate of the MOS transistor T3. M
The source of the OS transistor T3 is connected to the drain of the row selection MOS transistor T4. The source of the MOS transistor T4 is connected to an output signal line 6 (the output signal line 6 corresponds to 6-1 to 6-m in FIG. 1). The MOS transistors T1 to T4
Are N-channel MOS transistors each having a back gate grounded.

A DC voltage VPD is applied to the cathode of the photodiode PD and the drain of the MOS transistor T3. On the other hand, the source of the MOS transistor T2 is connected to a bias supply line 9 (the bias supply line 9 corresponds to 9-1, 9-2,..., 9-m in FIG. 1).
The output voltage generated by the voltage generating circuit 10x (corresponding to the voltage generating circuit 10 in FIG. 1) is applied through the corresponding voltage generating circuit 10x. The signal φS is applied to the gate of the MOS transistor T1.
, And a signal φV is input to the gate of the MOS transistor T4.

The voltage generation circuit 10x provided in the solid-state imaging device having the pixel having such a configuration will be described below. FIG. 4 is a block diagram illustrating an internal configuration of the voltage generation circuit 10x provided in the solid-state imaging device according to the present embodiment.

The voltage generating circuit 10x shown in FIG. 4 includes a light-shielded pixel 10a composed of a photodiode Pd, a MOS transistor T10, and an inverting buffer B1, a voltage VPS-L and a voltage VPS-L generated by the light-shielded pixel 10a. And a drive circuit 10b for selecting and outputting a voltage VPS-H for operating the MOS transistors T2 in the pixels G11 to Gmn in the sub-threshold region at a higher voltage by an input signal φVPS.

In the light-shielded pixel 10a, the drain and gate of the MOS transistor T10 and the input side of the inverting buffer B1 are connected to the anode of the photodiode Pd whose DC voltage VDA is applied to the cathode.
The DC voltage V is applied to the source of the MOS transistor T10.
SA is applied. The output voltage VPS-L from the inversion type buffer B1 is supplied to the drive circuit 10b. The light-shielded pixel 10a having such a configuration is shielded by an aluminum film or the like so that light does not enter the photosensitive portion of the photodiode Pd.

Further, when the light-shielding pixel 10a is configured as described above, the configuration of the inversion type buffer B1 is, for example, as shown in FIG.
You may do like this. That is, the inversion type buffer B1
Is a P-channel MOS transistor 11 having a gate connected to a connection node of the gate and the drain of the MOS transistor T10 and a DC voltage VDB applied to the drain, and one end connected to the source of the MOS transistor T11 and the other end. And a resistor R to which a DC voltage VSB is applied.

When the voltage generating circuit 10 is configured as shown in FIG. 4, the photodiode Pd and the MOS transistor T10 in the light-shielded pixel 10a function as a temperature detector for detecting the element temperature of the solid-state imaging device. That is, when the element temperature decreases, the dark current of the photodiode Pd decreases and the threshold voltage of the MOS transistor T10 decreases, so that the gate voltage of the MOS transistor T10 decreases. Conversely, when the element temperature rises, the photodiode P
As the dark current of d increases and the threshold voltage of the MOS transistor T10 increases, the gate voltage of the MOS transistor T10 increases. Therefore, the gate voltage of the MOS transistor T10 input to the inversion type buffer B1 changes according to the element temperature.

As described above, the photodiodes Pd and M
When the OS transistor T10 operates, the inverting buffer B1 having the configuration shown in FIG.
When the gate voltage of the transistor T10 decreases, the MOS
Since the current flowing through the transistor T11 increases, the voltage generated at the resistor R increases, and the output voltage VPS-L increases. Conversely, when the element temperature is high, the MOS transistor T1
0, the gate voltage of the MOS transistor T1 increases.
Since the current flowing through 1 becomes small, the voltage generated in the resistor R becomes low, and the output voltage VPS-L becomes low.

Next, the pixels G11 to G11 configured as shown in FIG.
The operation of Gmn will be described. The signal φVPS applied to the drive circuit 10b in the voltage generation circuit 10x is set to low level, the gate voltage of the MOS transistor T2 is reset, the signal φVPS is set to high level, and the DC voltage VPS-H is applied to the source of the MOS transistor T2. After
The signal φS is set to the high level and the MOS transistor T1
Is turned on, the imaging operation starts. At this time, when light enters the photodiode PD, a photocurrent is generated,
Due to the sub-threshold characteristic of MOS transistor,
A voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T2 and T3.

When the MOS transistor T4 is turned on by applying the pulse signal φV, the MOS transistor T4 is turned on.
The drain current amplified from the gate voltage of No. 3 is
It is led to the output signal line 6 via the transistors T3 and T4. The drain current of the MOS transistor T3 led to the output signal line 6 has a value that is proportional to the photocurrent in a natural logarithmic manner. At this time, the drain voltage of the MOS transistor Q1, which is determined by the on-state resistance of the MOS transistor T3 and the MOS transistor Q1 (FIG. 1) and the current flowing therethrough, appears on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T4 is turned off. At this time, the drain voltage appearing on the output signal line 6 is supplied to the sample and hold circuit 11 (FIG. 1) as image data and is sampled and held.

When the imaging operation is performed as described above, next,
A reset operation is performed. About this reset operation,
This will be described with reference to the flowchart of FIG. As described above, when the pulse signal φV is applied, the image data is output and sampled and held by the sample and hold circuit 11, first, the signal φS is set to low level, the MOS transistor T1 is turned off, and the phototransistor PD is turned off.
And the electrical connection between the MOS transistor T2. At this time, negative charges flow from the source side of the MOS transistor T2, and the positive charges stored in the gate and drain of the MOS transistor T2 and the gate of the MOS transistor T3 are recombined.

When the potential of the region under the drain and the gate of the MOS transistor T2 becomes a certain value after the reset, the speed of the reset is reduced. Therefore, next, the voltage φVPS applied to the drive circuit 10b in the voltage generation circuit 10x is set to the low level, and the MO
The output voltage VPS-L from the light-shielded pixel 10a is applied to the source of the S transistor T2. Thus, MO
DC voltage V is applied to the source of S transistor T2.
By converting PS-H to DC voltage VPS-L and lowering it,
The amount of negative charge flowing from the source of the MOS transistor T2 is increased. Therefore, the positive charges stored in the gate and drain of the MOS transistor T2 and the gate of the MOS transistor T3 are quickly recombined.

When the area under the drain and gate of the MOS transistor T2 is reset, the voltage φVPS applied to the drive circuit 10b in the voltage generation circuit 10x is set to a high level, and the DC voltage VPS-H is applied to the source of the MOS transistor T2. Apply. By applying the pulse signal φV to turn on the MOS transistor T4, the drain current corresponding to the gate voltage of the MOS transistor T3 at the time of resetting is reduced.
3, and are led out to the output signal line 6 via T4. Therefore, at this time, the drain voltage of the MOS transistor Q1 is output to the sample and hold circuit 11 as correction data, and is sampled and held. Then, after turning off the MOS transistor T4, the signal φS is set to the high level, and the MOS transistor T1 is turned on to prepare for the next imaging operation.

When operated in this manner, the potential of the region under the gate of the MOS transistor T2 after reset is determined by the output voltage VPS-L from the voltage generation circuit 10x applied to the source of the MOS transistor T2. At this time, when the element temperature is low, the output voltage VPS-L
As in the conventional case, the same DC voltage as that at normal temperature is applied to the source of the MOS transistor T2 to lower the potential of the region under the gate of the MOS transistor T2 after reset, which is caused by the decrease in the potential of the source of the MOS transistor T2. Can be prevented by giving the output voltage VPS-L, which is a higher voltage than at normal temperature.

When the element temperature is high, the output voltage VPS
Since -L is low, the same DC voltage as that at normal temperature is applied to the source of the MOS transistor T2 to increase the potential of the region under the gate of the MOS transistor T2 after reset, as in the prior art. Can be prevented by applying an output voltage VPS-L, which is a lower voltage than at normal temperature, to the source. Therefore, the potential of the region under the gate of the MOS transistor T2 after the reset is substantially constant regardless of the element temperature.

As described above, in the voltage generation circuit 10x, the temperature is detected by the light-shielded pixel 10a having the same temperature characteristics as the pixels G11 to Gmn, and the voltage corresponding to the detected temperature is reset and the MOS transistors T2 of the pixels G11 to Gmn are reset. , It is possible to reduce the influence of the element temperature which causes the output variation of each pixel.

<Second Embodiment> A second embodiment applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 7 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 3 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

The pixel shown in FIG. 7 is different from the pixel having the structure of the first embodiment (FIG. 3) in that the source is connected to the connection node between the gate and the drain of the MOS transistor T2.
The configuration is such that a transistor T5 is added. At this time,
The DC voltage VPS is applied to the source of the MOS transistor T2, and the voltage generation circuit 10y (FIG. 1) is connected to the drain of the MOS transistor T5 through the bias supply line 9.
Corresponding to the voltage generation circuit 10). Then, signal φSW is applied to the gate of MOS transistor T5. Other configurations are the same as those of the pixel in FIG. Further, the MOS transistor T5 is
Similar to the MOS transistors T1 to T4, an N-channel M
The back gate of the OS transistor is grounded.

FIG. 8 shows a configuration of a voltage generating circuit provided in a solid-state imaging device having pixels having such a configuration. In the voltage generation circuit of FIG. 8, elements and signal lines used for the same purpose as the voltage generation circuit of FIG.
The same reference numerals are given and the detailed description is omitted.

The voltage generation circuit 10y shown in FIG. 8 has a configuration in which the driver circuit 10b is omitted from the voltage generation circuit 10x in the first embodiment (FIG. 4). That is, the output voltage output from the inverting buffer B1 of the light-shielded pixel 10a is always applied to the drain of the MOS transistor T5. Other configurations are the same as those of the voltage generation circuit 10x of FIG. At this time, the output voltage VD output from the light-shielded pixel 10a is applied to the drain of the MOS transistor T5. The output voltage VD is lower when the temperature is high than when the temperature is normal, and is lower when the temperature is low than when the temperature is normal, similarly to the output voltage VPS-L from the voltage generation circuit 10x in FIG. Get higher.

As described above, the pixels G11 to G11 in the solid-state imaging device
The operation when Gmn and the voltage generation circuit 10y are configured will be described below. After the pulse signal φSW is applied to the gate of the MOS transistor T5 and the gate voltage of the MOS transistor T2 is reset, the signal φS is set to the high level and the MOS transistor T1 is turned on, and the imaging operation starts. . At this time, when light enters the photodiode PD, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T2 and T3 due to the subthreshold characteristic of the MOS transistor.

When the pulse signal φV is applied to turn on the MOS transistor T4, the MOS transistor T4 is turned on.
The drain current amplified from the gate voltage of No. 3 is
It is led to the output signal line 6 via the transistors T3 and T4. Therefore, the drain voltage of the MOS transistor Q1, which is proportional to the logarithm of the photocurrent appearing on the output signal line 6 in a natural logarithmic manner, is used as image data in the sample hold circuit
(FIG. 1) to be sampled and held.

When the imaging operation is performed as described above, next,
A reset operation is performed. About this reset operation,
This will be described with reference to the flowchart of FIG. As described above, when the pulse signal φV is supplied, the image data is output, and sampled and held by the sample and hold circuit 11, first, the signal φS is set to the low level to turn off the MOS transistor T1.

Then, by turning on the MOS transistor T5 by setting the signal φSW to high level, the output voltage VD from the voltage generation circuit 10y is applied to the gate of the MOS transistor T2. Therefore, M
The area under the gate of the OS transistor T2 is reset according to the output voltage VD applied to the gate. When reset in this manner, the signal φSW is set to low level to turn off the MOS transistor T5, and then the pulse signal φV is applied to the gate of the MOS transistor T4,
The output at the time of reset is output to the sample and hold circuit 11 through the output signal line 6 and sampled and held as correction data. After that, the signal φS is set to the high level to prepare for the next imaging operation.

When operated as described above, the potential of the region under the gate of the MOS transistor T2 after the reset is determined by the output voltage VD from the voltage generating circuit 10y applied to the gate of the MOS transistor T2 via the MOS transistor T5. It is determined. Therefore, as in the first embodiment, when the device temperature is low, the output voltage VD is high, so that the potential of the region under the gate is prevented from lowering. When the device temperature is high, the output voltage VD is low. Therefore, the potential of the region under the gate is prevented from increasing. Therefore, the reset MOS transistor T2
Is substantially constant regardless of the device temperature.

As described above, in the voltage generation circuit 10y, the temperature is detected by the light-shielded pixel 10a having the same temperature characteristics as the pixels G11 to Gmn, and the voltage corresponding to the detected temperature is reset and the MOS transistors T2 of the pixels G11 to Gmn are reset. , It is possible to reduce the influence of the element temperature which causes the output variation of each pixel.

<Third Embodiment> A third embodiment applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 10 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 3 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

In the pixel shown in FIG. 10, the cathode of the photodiode PD is connected to the source of the MOS transistor T1, and the drain of the MOS transistor T1 is connected to the gate of the MOS transistor T3, the source of the MOS transistor T6, and the drain of the MOS transistor T7. Connected. The MOS transistors T6 and T7 are
As in the case of the MOS transistors T1, T3, and T4, each is an N-channel MOS transistor and has a back gate grounded.

A DC voltage VPS is applied to the anode of the photodiode PD. And the MOS transistor T
Reference numeral 6 denotes a DC voltage VPD applied to its drain, and an output voltage VPG generated by a voltage generating circuit 10z (corresponding to the voltage generating circuit 10 in FIG. 1) to its gate through a bias supply line 9. The DC voltage RL is applied to the source of the MOS transistor T7,
Signal φRS is input to the gate. Other configurations are the same as those of the pixel of the first embodiment (FIG. 3).

FIG. 11 shows a configuration of a voltage generating circuit provided in a solid-state imaging device having pixels having such a configuration. In the voltage generating circuit of FIG. 11, elements and signal lines used for the same purpose as those of the voltage generating circuit of FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The voltage generating circuit 10z shown in FIG. 11 comprises a light-shielded pixel 10c composed of a photodiode Pd, a MOS transistor T20 and an inversion buffer B2. In the light-shielded pixel 10c, the source of the MOS transistor T20 and the input side of the inversion type buffer B2 are connected to the cathode of the photodiode Pd to which the DC voltage VSC is applied to the anode. The MOS transistor T20 is biased to operate in the sub-threshold region by applying the DC voltage VDC to its drain and the DC voltage VGA to its gate. The light-shielded pixel 10c having such a configuration is shielded by an aluminum film or the like so that light does not enter the photosensitive portion of the photodiode Pd.

When the voltage generating circuit 10z is configured as shown in FIG. 11, the photodiode Pd in the light-shielded pixel 10c
The MOS transistor T20 functions as a temperature detector for detecting the element temperature of the solid-state imaging device. That is, when the element temperature decreases, the dark current of the photodiode Pd decreases, and the threshold voltage of the MOS transistor T20 decreases, so that the source voltage of the MOS transistor T20 increases. Conversely, when the element temperature increases, the dark current of the photodiode Pd increases, and the threshold voltage of the MOS transistor T20 increases, so that the source voltage of the MOS transistor T20 decreases. Therefore, the gate voltage of the MOS transistor T20 input to the inversion type buffer B2 changes according to the element temperature.

As described above, the photodiodes Pd and M
Since the OS transistor T20 operates, the output voltage VPG from the inversion type buffer B2 has a low element temperature,
The higher the source voltage of the transistor T20, the lower the voltage. The higher the element temperature, the lower the source voltage of the MOS transistor T20, the higher the voltage.

Next, the pixel G11 constructed as shown in FIG.
To Gmn will be described. The pulse signal φRS is applied to the gate of the MOS transistor T7,
After the source voltage of the transistor T6 is reset, when the signal φS is set to the high level and the MOS transistor T1 is turned on, the imaging operation starts.

At this time, when light is incident on the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, the voltage obtained by natural logarithmically converting the photocurrent is applied to the source of the MOS transistor T6 and the MO.
This occurs at the gate of the S transistor T3. At this time, the negative photocharge generated in the photodiode PD is MO
Since the light flows into the source of the S-transistor T6, the source voltage of the MOS transistor T6 decreases as the intensity of the incident light increases.

When the MOS transistor T4 is turned on by applying the pulse signal φV, the MOS transistor T4 is turned on.
The drain current amplified from the gate voltage of No. 3 is
It is led to the output signal line 6 via the transistors T3 and T4. Therefore, the drain voltage of the MOS transistor Q1, which is proportional to the logarithm of the photocurrent appearing on the output signal line 6 in a natural logarithmic manner, is used as image data in the sample hold circuit 11
(FIG. 1) to be sampled and held.

When the imaging operation is performed as described above, next,
A reset operation is performed. About this reset operation,
This will be described with reference to the flowchart of FIG. As described above, when the pulse signal φV is supplied, the image data is output, and sampled and held by the sample and hold circuit 11, first, the signal φS is set to the low level to turn off the MOS transistor T1.

Then, the DC voltage RL is applied to the source of the MOS transistor T6 by turning on the MOS transistor T7 by setting the signal φRS to high level. Therefore, the MOS transistor T6 becomes
The source voltage is reset according to DC voltage RL. When reset in this manner, the signal φRS is set to low level to turn off the MOS transistor T7,
The pulse signal φV is supplied to the gate of the MOS transistor T4, and the output at the time of reset is output to the sample and hold circuit 11 through the output signal line 6 and sampled and held as correction data. After that, the signal φS is set to the high level to prepare for the next imaging operation.

In this operation, since the source voltage of the MOS transistor T6 after reset is constant, the potential between the region under the gate and the source of the MOS transistor T6 is always applied to the gate of the MOS transistor T6. Output voltage VPG from voltage generation circuit 10z
Is determined by At this time, when the element temperature is low, the output voltage VPG becomes low, so that the same DC voltage as that at normal temperature is applied to the gate of the MOS transistor T6 to reduce the area under the gate of the MOS transistor T6 after the reset. Can be prevented by applying an output voltage VPG, which is a voltage lower than that at normal temperature, to the gate of the MOS transistor T6.

When the element temperature is high, the output voltage VPG
As in the conventional case, the same DC voltage as that at normal temperature is applied to the gate of the MOS transistor T6 to lower the potential of the region under the gate of the MOS transistor T6 after the reset, as in the prior art. By applying an output voltage VPG, which is a voltage higher than that at normal temperature. Therefore, MO after reset
The potential between the region under the gate and the source of the S transistor T6 is substantially constant regardless of the element temperature.

As described above, in the voltage generation circuit 10z, the temperature is detected by the light-shielded pixel 10c having the same temperature characteristics as the pixels G11 to Gmn, and a voltage corresponding to the detected temperature is always applied to the MOS transistors T6 of the pixels G11 to Gmn. By giving the voltage to the gate, it is possible to reduce the influence of the element temperature which causes the output variation of each pixel.

<Fourth Embodiment> A fourth embodiment applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 13 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The pixel shown in FIG. 13 has a configuration in which the MOS transistor T7 is omitted from the third embodiment (FIG. 10). At this time, the signal φVPD is input to the drain of the MOS transistor T6. Other configurations are the same as those of the pixel in FIG. Further, the voltage generation circuit 10z connected to the gate of the MOS transistor T6 is a voltage generation circuit having the configuration shown in FIG. 11, as in the third embodiment. still,
A voltage for operating the MOS transistor T6 in the sub-threshold region is set as a first voltage, and a DC voltage V is detected in order to detect a variation in the threshold value of the MOS transistor T6.
A voltage having a value substantially equal to PS is defined as a second voltage.

Hereinafter, the pixel G configured as shown in FIG.
Operations of 11 to Gmn will be described. The signal .phi.VPD applied to the drain of the MOS transistor T6 is set to the second voltage, the source voltage of the MOS transistor T6 is reset, and the signal .phi.VPD is set to the first voltage. Is turned on, the imaging operation starts. At this time, when light is incident on the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage of a value obtained by natural logarithmically converting the photocurrent is applied to the MOS transistor T6.
And the gate of the MOS transistor T3.

When the pulse signal φV is applied to turn on the MOS transistor T4, the MOS transistor T4 is turned on.
The drain current amplified from the gate voltage of No. 3 is
It is led to the output signal line 6 via the transistors T3 and T4. Therefore, the drain voltage of the MOS transistor Q1, which is proportional to the logarithm of the photocurrent appearing on the output signal line 6 in a natural logarithmic manner, is used as image data in the sample hold circuit 11
(FIG. 1) to be sampled and held.

When the imaging operation is performed as described above, next,
A reset operation is performed. About this reset operation,
This will be described with reference to the flowchart of FIG. As described above, when the pulse signal φV is supplied, the image data is output, and sampled and held by the sample and hold circuit 11, first, the signal φS is set to the low level to turn off the MOS transistor T1.

Then, by setting the signal φVPD to the second voltage, a negative charge flows into the MOS transistor T6 from the drain side, and then the signal φVPD is returned to the first voltage, and the source of the MOS transistor T6 is returned to the first voltage. To accumulate negative charges. The amount of negative charge accumulated in the source of the MOS transistor T6 has a value corresponding to the threshold value of the MOS transistor T6.

Therefore, a voltage corresponding to the threshold voltage of MOS transistor T6 appears at the gate of MOS transistor T3. At this time, the pulse signal φV is supplied to the gate of the MOS transistor T4, and the output at the time of reset proportional to the threshold voltage of the MOS transistor T6 is output to the sample and hold circuit 11 through the output signal line 6 and sampled and held as correction data. . After that, the signal φS is set to the high level to prepare for the next imaging operation.

When operating as described above, the source voltage of the reset MOS transistor T6 is always applied to the gate of the MOS transistor T6.
It is determined by the difference between the output voltage VPG from z and the first voltage of the DC voltage VPD and the threshold voltage of the MOS transistor T6. At this time, when the element temperature is low, the output voltage VPG
Therefore, the difference between the output voltage VPG and the DC voltage VPD is increased to reduce the influence of the threshold voltage of the lowered MOS transistor T6. When the element temperature is high,
Since the output voltage VPG increases, the difference between the output voltage VPG and the DC voltage VPD is reduced, and the effect of the increased threshold voltage of T6 of the MOS transistor is reduced.

As described above, in the voltage generation circuit 10z, the temperature is detected by the light-shielded pixel 10c having the same temperature characteristics as the pixels G11 to Gmn, and a voltage corresponding to the detected temperature is constantly applied to the MOS transistors T6 of the pixels G11 to Gmn. By giving the voltage to the gate, it is possible to reduce the influence of the element temperature which causes the output variation of each pixel.

<Fifth Embodiment> A fifth embodiment applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 15 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The pixel shown in FIG. 15 has a configuration in which the MOS transistor T1 is omitted from the fourth embodiment (FIG. 13). That is, the cathode of the photodiode PD is connected to the source of the MOS transistor T6. Other configurations are the same as those of the pixel in FIG. Further, the voltage generation circuit 10z connected to the gate of the MOS transistor T6 is a voltage generation circuit having the configuration shown in FIG. 11, as in the third and fourth embodiments.

The operation of the pixels G11 to Gmn thus configured is almost the same as that of the pixel shown in FIG. That is, as shown in the timing chart of FIG. 16, the pulse signal φV is applied to the gate of the MOS transistor T4,
When the image data is supplied to the sample hold circuit 11 (FIG. 1) and sampled and held, first, the signal φVPD is set to the second voltage. Then, by returning the signal φVPD to the first voltage, a negative charge is accumulated in the source of the MOS transistor T6.
The OS transistor T4 is turned on, and correction data obtained based on the source voltage of the MOS transistor T6 is supplied to the sample and hold circuit 11 and sampled and held.

In the present embodiment, a solid-state imaging device is provided in which a pixel having a configuration in which the MOS transistor T1 is deleted from the pixel in the fourth embodiment is provided. The solid-state imaging device may be provided with a pixel having a configuration in which the transistor T1 is omitted. As described above, by using a pixel having a configuration in which the MOS transistor T1 is omitted from the pixel of each embodiment, the configuration can be simplified and the pixel size can be reduced.

In the first to fifth embodiments, the MO
An integration circuit such as a capacitor may be connected to the source of the S transistor T3, and when the MOS transistor T4 is turned on, an electric signal having a value integrated by the integration circuit may be output. By providing this integration circuit, the fluctuation component of the light source, high frequency noise, and the like are absorbed and removed by the integration circuit. Further, instead of the N-channel MOS transistor, a P-channel MOS transistor of opposite polarity may be used as an element constituting the solid-state imaging device.

Further, in each of the above-described embodiments, the voltage generating circuit is not limited to the above-described one, and various configurations can be employed. For example, in the first and second embodiments, it is sufficient that the output increases as the element temperature decreases. As shown in FIG. 11, the photodiode has the opposite polarity to that of FIG. 4 or FIG. May be something,
In the third and fourth embodiments, it is sufficient that the output decreases as the element temperature decreases. Even if the photodiode has the opposite polarity to that of FIG. good.

[0093]

According to the present invention, it is possible to detect the element temperature of the solid-state imaging device from the voltage generation circuit, and to change the voltage applied to the transistor operating in the sub-threshold region of each pixel according to the element temperature. be able to. That is, since the potential state of the transistor can be made substantially constant irrespective of the element temperature, the output from the solid-state imaging device is less affected by the dark current of the photosensitive element, which varies with the element temperature, and the threshold voltage of the transistor. Output. Therefore, the linearity between the logarithmic conversion value of the illuminance of the subject and the output level of the electric signal from the pixel can be maintained without depending on the element temperature change.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a part of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a voltage generation circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an inversion type buffer in the voltage generation circuit of FIG. 4;

FIG. 6 is a timing chart of a signal applied to each element of a pixel used in the first embodiment.

FIG. 7 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a voltage generation circuit according to a second embodiment of the present invention.

FIG. 9 is a timing chart of a signal applied to each element of a pixel used in the second embodiment.

FIG. 10 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a voltage generation circuit according to third to fifth embodiments of the present invention.

FIG. 12 is a timing chart of a signal applied to each element of a pixel used in the third embodiment.

FIG. 13 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 14 is a timing chart of a signal applied to each element of a pixel used in the fourth embodiment.

FIG. 15 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 16 is a timing chart of a signal applied to each element of a pixel used in the fifth embodiment.

FIG. 17 is a circuit diagram illustrating a partial configuration of a pixel provided in a solid-state imaging device.

FIG. 18 is a graph showing the relationship between the illuminance of a subject and the output of a solid-state imaging device.

[Explanation of symbols]

G11 to Gmn pixel 2 vertical scanning circuit 3 horizontal scanning circuit 4-1 to 4-n row selection line 6-1 to 6-m output signal line 7 DC voltage line 8 line 9-1 to 9-m bias supply line 10 voltage Generation circuit 11 Sample hold circuit 12 Output circuit PD, Pd, P Photodiode T1 to T7, T10, T11, T20, TMOS transistor

Claims (14)

[Claims] 1. An electric device comprising: a photosensitive element for generating an electric signal corresponding to an amount of incident light; and a transistor which receives an electric signal from the photosensitive element and operates in a sub-threshold region. A solid-state imaging device including a plurality of pixels having a photoelectric conversion unit for converting, comprising: a voltage generation circuit that outputs a voltage corresponding to a temperature of the solid-state imaging device; Wherein the potential state of the transistor is set by biasing. 2. The voltage generation circuit according to claim 1, wherein the voltage generation circuit has a temperature detection unit having the same configuration as that of the photoelectric conversion unit, and is shielded so that light does not enter the temperature detection unit. Solid-state imaging device. 3. A photosensitive element for generating an electric signal corresponding to the amount of incident light, and a first transistor having a first electrode and a control electrode connected to one electrode of the photosensitive element. A plurality of pixels that output an electrical signal obtained by natural logarithm conversion from the control electrode of the first transistor, and a first voltage or the first voltage for resetting the plurality of pixels according to the temperature of the solid-state imaging device. A voltage generation circuit that outputs any of a second voltage for operating the transistor in a sub-threshold region to a second electrode of the first transistor; and when the pixel is reset, the voltage generation circuit The first voltage is applied to a second electrode of the first transistor, and when the pixel performs an imaging operation, the voltage is applied from the voltage generation circuit to a second electrode of the first transistor. The solid-state imaging device, wherein a second voltage is applied. 4. A voltage-generating circuit comprising: a photosensitive element having the same characteristics as the photosensitive element provided in the pixel; and a first electrode having a first electrode and a control electrode connected to one electrode of the photosensitive element. A transistor; an inverting buffer having an input side connected to a connection node between a first electrode and a control electrode of the first transistor for outputting the first voltage; and selecting the first voltage and the second voltage. 4. The solid-state imaging device according to claim 3, further comprising: a drive circuit configured to output the light through the light-receiving element, wherein the light-shielded element is shielded so that light does not enter the photosensitive element. 5. A photosensitive element for generating an electric signal in accordance with the amount of incident light, a first electrode and a control electrode connected to one electrode of the photosensitive element, and biased to operate in a sub-threshold region. A first transistor, and a second transistor having a second electrode connected to a control electrode of the first transistor, wherein an electrical signal obtained by natural logarithmic conversion of the electrical signal is used as a control electrode of the first transistor. And a voltage generation circuit that outputs a voltage corresponding to the temperature of the solid-state imaging device to a first electrode of the second transistor, wherein the second transistor is provided when the pixel is reset. Is turned on, the voltage from the voltage generation circuit is applied to the control electrode of the first transistor, and when the pixel performs an imaging operation, the second transistor A solid-state imaging apparatus characterized by data are turned OFF. 6. A photosensitive element having the same characteristics as the photosensitive element provided in the pixel, wherein the voltage generating circuit has a first electrode and a control electrode connected to one electrode of the photosensitive element. A transistor, and an inverting buffer having an input connected to a connection node between a first electrode and a control electrode of the first transistor, and outputting a voltage to a first electrode of the second transistor in the pixel, The solid-state imaging device according to claim 5, wherein light is shielded so that light does not enter the photosensitive element. 7. The pixel according to claim 3, wherein a first electrode is connected to one electrode of the photosensitive element, and a second electrode is connected to a first electrode and a control electrode of the first transistor.
A transistor, wherein when the pixel is reset, the third transistor is turned off, and when the pixel performs an imaging operation,
The solid-state imaging device according to claim 3, wherein the third transistor is turned on. 8. A fourth transistor in which the pixel has a control electrode connected to a first electrode and a control electrode of the first transistor, and amplifies a voltage appearing at the control electrode of the first transistor and outputs the amplified voltage from a second electrode. The solid-state imaging device according to any one of claims 3 to 7, further comprising: 9. A photosensitive element for generating an electric signal according to the amount of incident light, and a first transistor having a second electrode connected to one electrode of the photosensitive element and biased to operate in a sub-threshold region. And a second transistor having a first electrode connected to the second electrode of the first transistor and a reset DC voltage applied to the second electrode, and a natural logarithm of the electric signal. A plurality of pixels that output the converted electric signals from the second electrode of the first transistor; and a voltage generation circuit that outputs a voltage corresponding to the temperature of the solid-state imaging device to the control electrode of the first transistor. When the pixel is reset, the second transistor is turned on, and when the pixel performs an imaging operation, the second transistor is turned off. Solid-state imaging device. 10. A photosensitive element having the same properties as the photosensitive element provided in the pixel, a first transistor having a second electrode connected to one electrode of the photosensitive element, and An inverting buffer having an input connected to the second electrode of the first transistor and outputting a voltage to a control electrode of the first transistor in the pixel, wherein the buffer is shielded so that light does not enter the photosensitive element. The solid-state imaging device according to claim 9, wherein: 11. A photosensitive element for generating an electric signal according to the amount of incident light, a first transistor having a second electrode connected to one electrode of the photosensitive element and biased to operate in a sub-threshold region. A plurality of pixels that output an electrical signal obtained by natural logarithmic conversion of the electrical signal from a second electrode of the first transistor, and a voltage corresponding to a temperature of a solid-state imaging device is applied to the first transistor. A solid-state imaging device, comprising: a voltage generation circuit that outputs a voltage to a control electrode of the first transistor, wherein the pixel is reset by changing a voltage applied to a first electrode of the first transistor. 12. The photosensitive element having the same characteristics as the photosensitive element provided in the pixel, a first transistor having a second electrode connected to one electrode of the photosensitive element, and An inverting buffer having an input connected to the second electrode of the first transistor and outputting a voltage to a control electrode of the first transistor in the pixel, wherein the buffer is shielded so that light does not enter the photosensitive element. The solid-state imaging device according to claim 11, wherein: 13. The pixel includes a third transistor in which a first electrode is connected to a second electrode of the first transistor and a second electrode is connected to one electrode of the photosensitive element. When the pixel is reset, the third transistor is turned off, and when the pixel performs an imaging operation,
The solid-state imaging device according to claim 9, wherein the third transistor is turned on. 14. The pixel includes a fourth transistor having a control electrode connected to a second electrode of the first transistor, amplifying a voltage appearing at a second electrode of the first transistor, and outputting the amplified voltage from the second electrode. 10. The method according to claim 9, wherein
The solid-state imaging device according to claim 13.