JP2000260933A - Manufacture for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce mounting area and to make multi-functioning by forming an electric junction between a first and a second semiconductor chips, by melting solder after a metallic fine wire passing through a through holes which are formed at electrode pads of the first and the second semiconductor chips. SOLUTION: Pads 3-1 for electrical junction are formed on a semiconductor chip 1-1 and through holes 2 having a predetermined diameter at the central part of the pads 3-1. Through holes are formed at the same pad position as of the pads 3-1 on semiconductor chips 1-2 and 1-3 in the same way. The semiconductor chips 1-1 to 1-3 on which the through holes are formed are overlapped by aligning, after that each semiconductor chip 1-1 to 1-3 is electrically junctioned via the through holes by melting solder in the state of Au fine wires 4-1 on which surfaces solder plating is made to pass through the through holes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a higher function by stacking a plurality of semiconductor chips.

[0002]

2. Description of the Related Art Due to recent rapid advances in semiconductor technology,
2. Description of the Related Art Higher performance semiconductor chips and smaller chip sizes have been attempted. However, the miniaturization of the chip itself has made it difficult to package and mount it, and has also caused a significant increase in mounting cost.

[0003] Furthermore, a complex high function is required for a semiconductor device, and a system incorporating a plurality of semiconductor devices is required. As a result, the area occupied by a semiconductor on a substrate is increasing. 3 to solve this problem
Many ideas for semiconductor chip packages having a two-dimensional structure have already been considered. For example, JP-A-5-63
137 and JP-A-6-291250 (Patent No. 26
05968), JP-A-8-264712 and JP-A-1
No. 0-163411. FIG. 3 shows a basic structure common to these. Semiconductor chips 1-1, 1-2, 1-
3 are overlapped with each other to obtain an electrical connection via a conductive substance formed in the through hole 4.

[0004]

SUMMARY OF THE INVENTION The present invention has been created in order to easily realize a three-dimensional structure as shown in FIG. 4, and has a small size, a small mounting area, and a multifunctional structure. The purpose of the present invention is to obtain a semiconductor chip.

[0005]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first semiconductor chip on which a wiring and an electrode pad for extracting an electric signal are formed; In a semiconductor device manufacturing method for stacking a second semiconductor chip on which an extraction wiring and an electrode pad are formed and manufacturing a semiconductor device having at least two semiconductor chips, a first semiconductor chip and a second semiconductor chip are provided. After passing a thin metal wire with solder plating through the through hole formed in the electrode pad for taking out the electric signal, the solder is melted by heating,
An electrical junction between the first and second semiconductor chips is formed.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, a hole is formed in a state of a wafer before being cut into chips, a plurality of wafers are stacked, and a wire plated with solder is passed through the hole to collectively form a hole. After forming the electrical junction by reflow, dicing may be performed to a chip size (claim 2).

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

<First Embodiment> FIG. 2 is a cross-sectional view showing a structure of a semiconductor device manufactured according to a first embodiment. The semiconductor chips 1-1, 1-2, and 1-3 are pads 3-
They are electrically connected to each other by metal wires 4-1 inserted into through holes formed in 1, 3, 2 and 3-3.

Next, the manufacturing method of the present invention will be described in detail with reference to FIG.

As shown in FIG. 1A, the semiconductor chip 1
A pad 3-1 for making an electrical connection is formed on -1. The size of the pad portion is 100 microns square. A through hole 2-1 having a diameter of 80 microns is formed at the center of the pad. As a method of opening the through hole, there is a method of opening with a laser or a method of opening silicon by anisotropic etching. The material of the pad is generally Al, but here, a pad in which a Ti / TiN layer is formed as a barrier layer on Al and Cu is formed is used.

Next, as shown in FIG. 1B, the semiconductor chips 1-1, 1-2, and 1-3 having the through-holes are overlapped while being aligned. As shown, a diameter of 7 μm with a 10 μm solder plated surface
A 0 μm Au fine wire 4-1 was prepared and passed through a through hole.

In this state, by melting the solder in a reflow furnace, the semiconductor chips 1-1, 1-2, and 1-3 could be electrically connected via through holes.

<Second Embodiment> FIG. 3 is a diagram showing a configuration of a semiconductor device manufactured according to a second embodiment. On the first semiconductor chip 1-1, the second semiconductor chip 1-
2 are stacked. Pad 3 on each chip
Are formed, and a pad group 5 formed on the semiconductor chip 1-1 is a pad for wire bonding. The pad group 7 formed on the chip 1-2
Are also pads for wire bonding. Here, the upper and lower chips are electrically connected by a pad group 6 in which a metal wire 4 plated with solder is formed in the center of the pad 3.

Next, the manufacturing method of the second embodiment will be described in detail with reference to FIG.

As shown in FIG. 3, the semiconductor chip 1-1
Above, pads 3 for making electrical connections have already been formed. A plurality of the pads 3 are formed, and a pad group 5 and a pad group 6 are formed. The size of this pad is 100 microns square. For only the pad group 6, a through hole having a diameter of 80 microns is formed at the center. The method of opening the through-hole used a method of opening with a laser. The pad material is usually Al
However, here, a pad having Au formed on Al was used.

Next, similarly, pads 3 for electrical connection are formed on the semiconductor chip 1-2.
A plurality of the pads 3 are formed, and a pad group 6 and a pad group 7 are formed. The size of this pad is 100 microns square. Only for pad group 6 of these,
A through hole having a diameter of 80 microns is formed at the center. The forming method is the same as above. Pad group 6
Is formed so that when the chips 1-1 and 1-2 are stacked, the alignment can be performed accurately so that the through holes penetrate. The semiconductor chips 1-1 and 1-2 having the through holes formed thereon were aligned with each other while being aligned, and then the surface was plated with a solder having a diameter of 10 μm.
A 0 μm Au fine wire 4 was prepared and passed through a through hole.

In this state, by melting the solder in a reflow furnace, the semiconductor chips 1-1 and 1-2 could be electrically connected via the through holes.

[0018]

According to the present invention, a three-dimensional semiconductor chip having a small size, a small mounting area, and a multi-function can be easily realized as shown in FIG.
For example, by combining a microcomputer chip as the first chip and a memory as the second chip, it is possible to obtain a semiconductor device such as a multifunctional semiconductor chip which is smaller than the conventional one.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip formed according to the first embodiment.

FIG. 3 is a plan view of a semiconductor chip manufactured according to Embodiment 2;

FIG. 4 is a cross-sectional view of a three-dimensional structure in which general semiconductor chips are stacked.

[Explanation of symbols]

1-1. First semiconductor chip 1-2. Second semiconductor chip 1-3. 1. Third semiconductor chip Through hole 3-1. Electrode pad of first semiconductor chip 3-2. Electrode pad of second semiconductor chip 3-3. Electrode pad of third semiconductor chip 4-1. Fine metal wire with solder plating on the surface 4-2. Conductive material 5. 5. Pad group of first semiconductor chip 6. Pad group for connecting the first semiconductor chip and the second semiconductor chip Pad group of second semiconductor chip

Claims (2)

[Claims] 1. A first semiconductor chip on which wiring and electrode pads for extracting electric signals are formed, and a second semiconductor chip on which wiring and electrode pads for extracting electric signals are formed at the same position as the first semiconductor chip In a method of manufacturing a semiconductor device having at least two semiconductor chips, wherein a through hole formed in an electrode pad for extracting an electric signal of the first semiconductor chip and the second semiconductor chip includes: After passing the solder-plated thin metal wire, the solder is melted by heating,
A method for manufacturing a semiconductor device, comprising: forming an electrical junction between a first semiconductor chip and a second semiconductor chip. 2. A method of manufacturing a semiconductor device according to claim 1, wherein a through-hole is formed in a state of the wafer before being cut into chips, a plurality of wafers are stacked, and a wire plated with solder is formed in the through-hole. Forming an electrical joint by reflow at a time, and then dicing to a chip size.