JP2000251473A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output data without causing any phase deviation in an external clock at the time of generating an internal clock synchronously with the external clock and controlling the data output operation at an off-chip driver circuit by using the internal clock. SOLUTION: This circuit has an off-chip driver circuit, a synchronous circuit 31, which outputs an internal clock Tu that is synchronized to an external clock CK, a synchronous circuit 32, which outputs an internal clock Td having a phase that is 180 deg. shifted with respect to the clock CK, a synchronous circuit 33, which outputs an internal clock aTx1 that is synchronized to the clock Tu and has a phase that is advanced at least for the amount equivalent to a signal delay time in the off-chip driver circuit, a synchronous circuit 34, which outputs an internal clock aTx2 that is synchronized with the clock Td and has a phase that is advanced at least for the amount equivalent to a signal delay time in the off-chip driver circuit, and an OR circuit 35 into which clock aTx1 and aTx2 are inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an off-chip driver circuit for outputting data inside a chip to the outside, and more particularly to an off-chip circuit for generating an internal clock used for data output control in the off-chip driver circuit. The present invention relates to a semiconductor integrated circuit including a driver control signal generation circuit.

[0002]

2. Description of the Related Art In recent years, in an I / O section of a semiconductor integrated circuit such as a semiconductor memory such as a DRAM, data input / output is performed in synchronization with both rising and falling edges of an external clock. I have. Such a method is called a DDR (Double Data Rate) method, which is twice as fast as the case where data is input / output in synchronization with either one of the rising edge and the falling edge of the external clock. Data can be input and output.

Further, in order to input / output data in synchronization with both rising and falling edges of the external clock, the internal clock Tu synchronized with the rising edge of the external clock and the rising edge of the external clock are internally provided within the chip. An internal clock Td synchronized with the falling edge and an internal clock Tw synchronized with both rising and falling edges of the external clock are generated.

[0004] Further, an off-chip driver (off chip d) which is a data output circuit provided in an I / O section of the chip.
In a river (OCD) circuit, when a delay time from input of an internal clock for controlling data output to data output is long, it is necessary to generate the internal clock in consideration of the delay time in the OCD circuit. That is, when the delay time in the OCD circuit cannot be ignored, it is necessary to generate an internal clock for controlling the operation of the OCD circuit ahead of the delay time in the OCD circuit.

[0005] By the way, various synchronous circuit methods for synchronizing the internal clock with the external clock have been considered, and among them, "A 2.5 ns C" by T. Saeki et al.
lockAccess 250MHz 256Mb SDRAM with a Synchronous M
irror Delay SMD (Synchronous Mirror Delay) used in "ISSCC Digest of technical papers." and STBD disclosed in JP-A-10-69326.
(SAD including Synchronous TracedBackward Delay etc.
The (Synchronous Adjustable Delay, Synchronous Adjustable Delay circuit) method is often used because of its high synchronization speed and low power consumption.

Here, the principle of the synchronous circuit of the SAD system disclosed in Japanese Patent Application Laid-Open No. 10-69326 will be described.

FIG. 19 is a block diagram of a synchronous circuit of the SAD system.

The synchronous circuit includes an input buffer 11, a delay monitor circuit 12, a forward pulse delay line 14 composed of a plurality of cascade-connected unit delay elements 13, and a unit delay element in the forward pulse delay line 14. 13, the same number as the unit delay elements provided in the backward pulse delay line 16, the forward pulse delay line 14, and the backward pulse delay line 16 configured by the same number of multi-stage cascaded unit delay elements 15. A control circuit 17 having a state holding circuit (not shown) for controlling the pulse delay operation of the backward pulse delay line 16 in accordance with the pulse delay state of the forward pulse delay line 14, and the backward pulse delay line 16 And an output buffer 18 to which the output of the above is input. In FIG. 19, the circuit composed of the forward pulse delay line 14, the backward pulse delay line 16, and the control circuit 17 is SA
This is called a D circuit SAD.

FIG. 20 is a timing chart showing an example of the operation of the synchronization circuit shown in FIG. Now, FIG.
Consider a case where an external clock CK having a period τ is input to the input buffer 11 as shown in FIG. External clock C
K is shaped and amplified by the input buffer 11,
It is output as a pulse CLK. Now, input buffer 1
Assuming that the delay time at 1 is D1, the pulse CLK is delayed by D1 with respect to the external clock CK as shown in FIG. Pulse CL output from input buffer 11
K is input to the delay monitor circuit 12 and the control circuit 17 of the SAD circuit SAD.

The delay monitor circuit 12 has a delay time A (= D1 + D) equal to the sum of the delay time D1 in the input buffer 11 and the delay time D2 in the output buffer 18.
Have 2). Therefore, the pulse output from the delay monitor circuit 12 is, as shown in FIG.
The pulse CLK output from 1 is input to the forward pulse delay line 14 as a signal Din with a delay of A period.

The forward pulse delay line 14 is composed of a plurality of unit delay elements 13 connected in cascade as described above. The signal Din is sequentially delayed by the plurality of cascade-connected unit delay elements 13 until the pulse CLK of the next cycle is input to the control circuit 17. After the pulse CLK of the next cycle is input to the control circuit 17, the backward pulse delay line 16 sequentially delays the pulse CLK of the next cycle. The delay operation is controlled by the control circuit 17. here,
The control circuit 17 controls the operation of the backward pulse delay line 16 based on the propagation state of the forward pulse in the forward pulse delay line 14 so that the backward pulse propagation time is equal to the forward pulse propagation time. Therefore, the pulse CLK of the next cycle is (τ) by the backward pulse delay line 16.
-A). Delay line 16 for backward pulse
Is delayed by the time of D2 by the output buffer 18 and output as the internal clock CK '.

Here, the delay time from the input of the external clock CK to the output of the internal clock CK 'is Δt.
If it is assumed to be total, Δtotal is expressed as follows.

Δtotal = D1 + A + 2 (τ−A) + D2 (1) Here, since D1 + D2 = A, Δtotal becomes 2τ, and the internal clock CK ′ is synchronized with the external clock CK from the third clock of the external clock CK. Become.

In the synchronous circuit of FIG. 19, the number of the unit delay elements 15 in the backward pulse delay line 16 is reduced to half of the number of the unit delay elements 13 in the forward pulse delay line 14, and the backward pulse delay line 16 Is set to be half of the delay time in the forward pulse delay line 14 and the delay time in the delay monitor circuit 12 is set to twice the delay time (2A) in FIG. CK 'is shifted by 180 ° with respect to the external clock CK.

FIG. 21 is a block circuit diagram of a conventional off-chip driver control signal generation circuit constructed using such a SAD type synchronous circuit. This circuit includes a synchronizing circuit 21 for generating an internal clock Tu synchronized with the external clock CK from the external clock CK, and a 180 ° phase shift from the external clock CK with respect to the external clock CK.
Synchronous circuit 22 for generating shifted internal clock Td
An OR circuit 23 that receives the internal clocks Tu and Td to generate an internal clock Tw, and a synchronizing circuit 24 that generates an internal clock Tx having a frequency twice the frequency of the external clock CK from the internal clock Tw. Have been.

As shown in FIG. 22, the synchronizing circuit 21 comprises an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD1, and an output buffer 18, like the synchronizing circuit shown in FIG. In this synchronous circuit 21,
The delay monitor circuit 12 is set to have a delay amount corresponding to the signal delay time in one input buffer and one output buffer. And this synchronous circuit 2
1 from the internal clock T synchronized with the external clock CK.
u is output.

As shown in FIG. 23, the synchronizing circuit 22 comprises an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD2, and an output buffer 18, as in the synchronizing circuit shown in FIG. In this synchronous circuit 21,
The delay monitor circuit 12 is set to have a delay amount corresponding to a signal delay time in each of two input buffers and output buffers. Also, the SAD circuit SAD
The number of unit delay elements of the second backward pulse delay line 16 is reduced to half of the number of unit delay elements. Therefore, the phase of the external clock CK is 1 from the synchronous circuit 22.
The internal clock Td shifted by 80 ° is output.

Then, when the two internal clocks Tu and Td are input to the OR circuit 23 in FIG. 21, an internal clock Tw having a frequency twice as high as the external clock CK is output. However, the internal clock Tw output from the OR circuit 23 cannot be used as a control clock for controlling the off-chip driver circuit because it includes the signal delay time in the OR circuit 23.

Therefore, the internal clock Tw output from the OR circuit 23 is input to the synchronizing circuit 24, where the internal clock Tx in which the signal delay time in the OR circuit 23 has been compensated is
To get

The synchronizing circuit 24 includes a delay monitor circuit 12, a SAD circuit SAD3, and an output buffer 18, as shown in FIG. In this case, the delay monitor circuit 12 includes an OR circuit 25 having a delay time equivalent to the OR circuit 23 and an output buffer 26 having a delay time equivalent to the output buffer 18.

In the synchronization circuit 24 shown in FIG. 24, the signal delay time in the OR circuit 23 in FIG.
The signal delay time in the output buffer 18 for outputting x is compensated, and an internal clock Tx having a frequency twice as high as that of the external clock CK is obtained.

Incidentally, the internal clock Tx must have a large driving capability in order to be distributed to each part of the chip. Therefore, the output buffer 18 in the synchronizing circuit 24 needs to have a large buffer capacity. In order to compensate for the delay time in the output buffer 18, a synchronizing circuit using a SAD circuit as shown in FIG. 24 are required.

Also, the delay time in OCD is large,
The internal clock Tx by the delay amount with respect to the external clock
This synchronization circuit 24 is also required when it is necessary to precede.

[0024]

By the way, even if the synchronization is synchronized in each synchronous circuit, there is a synchronous error as an offset in each synchronous circuit. For example, FIG.
2 is Δτ1 and SAD circuit SAD1 in FIG.
It is assumed that the D circuit SAD2 includes a synchronization error of Δτ2. In this case, as shown in the timing chart of FIG. 25, the internal clock Tu has a synchronization error of Δτ1 with respect to the ideal internal clock Tu having no synchronization error indicated by a broken line. Similarly, the internal clock Td is also different from the ideal internal clock Td indicated by a broken line having no synchronization error by Δ
A synchronization error of τ2 occurs. And both internal clocks T
The internal clock Tw after taking the OR logic of u and Td is
The period alternates between τ1 and τ2. In addition,
The two periods τ1 and τ2 are respectively expressed by the following equations.

Τ1 = (1/2) τ + (Δτ1-Δτ2) (2) τ2 = (1/2) τ− (Δτ1-Δτ2) (3) Then, a period τ1 indicated by C1 in FIG. When an internal clock Tx indicated by C3 in FIG. 25 is to be created using the synchronization circuit 24 in FIG. 24 from the internal clock Tw of FIG.
When there is no synchronization error in the AD circuit SAD3, the deviation of the clock C3 from the ideal internal clock Tx indicated by the broken line is-
Δτ1 + 2Δτ2. Here, as shown in FIG. 25, assuming that the deviations of Δτ1 and Δτ2 are in the opposite directions, the deviation between the internal clock Tx (C3) and the ideal Tx becomes very large.

For example, if .DELTA..tau.1 = .DELTA..tau. And .DELTA..tau.2 =-. DELTA..tau., Even if it is assumed that there is no synchronization error in the SAD circuit SAD3, the phase shift is amplified by 3.DELTA..tau. And SAD circuit SAD
When an additional synchronization error of Δτ occurs in 3, 4Δτ and each S
There is a problem that a synchronization error four times as large as the error generated in the AD circuit occurs in the internal clock Tx.

As described above, in the conventional off-chip driver control signal generating circuit shown in FIG.
It is amplified by the D circuit. Therefore, when the amplified error causes a problem in chip operation, the SAD circuit SAD3
Instead of PLL (Phase Locked Loop) circuit or DLL
(Delay Locked Loop) circuit had to be used.

However, PLL circuits and DLL circuits are
Since the power consumption is large and the synchronization speed is slow as compared with the D circuit, there is a problem that the power consumption as a whole increases and the synchronization speed becomes slow.

The present invention has been made in view of the above circumstances, and has as its object to provide a control for an off-chip driver capable of reducing a synchronization error without using a PLL circuit or a DLL circuit. An object of the present invention is to provide a semiconductor integrated circuit including a signal generation circuit.

[0030]

A semiconductor integrated circuit according to a first aspect of the present invention outputs data based on an output control signal, and has an off-chip driver having a predetermined signal delay time between the output control signal and the data output. A first synchronizing circuit to which a first clock is input and which outputs a second clock synchronized with the first clock and having a phase advanced by at least a signal delay time in the off-chip driver circuit; , A third clock synchronized with the third clock, a fourth clock having a phase advanced by at least a signal delay time in the off-chip driver circuit and having a frequency different from the second clock. A second synchronizing circuit for outputting, the second clock and the fourth
And an OR circuit for receiving a clock signal and outputting a fifth clock signal for controlling a data output operation in the off-chip driver circuit.

A semiconductor integrated circuit according to a second aspect of the present invention outputs data based on an output control signal, and a signal delay from an output control signal to data output at the time of "H" level data output and "L" level data output. "H" between the off-chip driver circuit with different time and the off-chip driver circuit
A first output control signal generation circuit for generating a first output control signal used when outputting level data, and a second output control signal used when outputting "L" level data in the off-chip driver circuit And a second output control signal generating circuit for generating

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to a first embodiment of the present invention. This circuit is
A synchronization circuit 31 for outputting an internal clock Tu synchronized with the external clock CK from the external clock CK;
Synchronous circuit 3 that outputs internal clock Td shifted by 0 °
2 and the internal clock Tu, and a synchronizing circuit 33 which synchronizes with the internal clock Tu and outputs an internal clock aTx1 whose phase has been advanced at least by a signal delay time in the off-chip driver circuit, and the internal clock Td Is synchronized with the internal clock Td,
A synchronizing circuit 34 for outputting an internal clock aTx2 whose phase has been advanced at least by the signal delay time in the off-chip driver circuit, an OR circuit 35 to which the internal clocks aTx1 and aTx2 are input, and an OR circuit 3
5 and an output buffer 36 that receives the internal clock aTx and outputs the internal clock Tx.

Here, the internal clock Tx output from the output buffer 36 is used as a control clock for controlling a data output operation in an off-chip driver circuit provided in the same semiconductor integrated circuit. In this case, the internal clock Tx has twice the frequency of the external clock CK, and is used as a control clock according to the DDR system.

FIG. 2 shows a detailed circuit configuration of the synchronization circuit 31 in FIG. The synchronization circuit 31 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD11, and an output buffer 18, similarly to the synchronization circuit of FIG. In the synchronous circuit 31, the delay monitor circuit 12 is set to have a delay amount corresponding to a signal delay time in one input buffer and one output buffer. A plurality of unit delay elements are provided in the backward pulse delay line 16 of the SAD circuit SAD11. Then, from the synchronization circuit 31, an internal clock Tu synchronized with the external clock CK is output.

FIG. 3 shows a detailed circuit configuration of the synchronization circuit 32 in FIG. The synchronization circuit 32 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD12, and an output buffer 18, similarly to the synchronization circuit of FIG. In the synchronous circuit 32, the delay monitor circuit 12 is set to have a delay amount corresponding to a signal delay time in each of two input buffers and output buffers.

Specifically, the delay monitor circuit 12
Two input buffers 37 and 38 having a circuit configuration equivalent to the input buffer 11 in the synchronization circuit 32 and output buffers 39 and 40 having a circuit configuration equivalent to the output buffer 18 in the synchronization circuit 32 are connected in cascade. Configuration.

Further, the number of unit delay elements of the backward pulse delay line 16 of the SAD circuit SAD12 is reduced to half of the number of unit delay elements. Therefore, the internal circuit Td whose phase is shifted by 180 ° with respect to the external clock CK is output from the synchronous circuit 32.

FIG. 4 shows a detailed circuit configuration of the synchronization circuits 33 and 34 in FIG. The synchronization circuits 33 and 3
In No. 4, the input clock of the synchronizing circuit 33 is Tu and the input clock of the synchronizing circuit 34 is only Td and the input clock is different.

The synchronization circuits 33 and 34 are composed of an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD13, and an output buffer 18, as in the case of the synchronization circuit of FIG. In the synchronization circuits 33 and 34, the delay monitor circuit 12 has a delay amount corresponding to a signal delay time in one input buffer and one output buffer, respectively.
The delay amount corresponding to the signal delay time in the OR circuit 35 in FIG. 1, the delay amount corresponding to the signal delay time in the output buffer 36 in FIG. 1 to which the output of the OR circuit 35 is input, and the off-chip driver circuit Are set to have a total delay amount corresponding to the signal delay time at

Specifically, the delay monitor circuit 12
An input buffer 41 having a circuit configuration equivalent to the input buffer 11 in the synchronization circuits 33 and 34;
1 and 2. An output buffer 42 having a circuit configuration equivalent to the output buffer 18 in 3 and 34, an OR circuit 43 having a circuit configuration equivalent to the OR circuit 35 in FIG.
An output buffer 44 having a circuit configuration equivalent to the middle output buffer 36, an internal clock Tx is supplied, and a circuit configuration equivalent to an off-chip driver circuit (not shown) in which a data output operation is controlled based on the internal clock Tx. And an imitation circuit 45 having a simple circuit pattern and having a signal delay time substantially equal to that of the off-chip driver circuit.

The synchronizing circuits 33 and 34 basically output an internal clock aTx1 or aTx2 synchronized with the internal clock Tu or Td.

However, in the middle of the clock propagation path in the delay monitor circuit 12, the OR circuit 3 in FIG.
5, an OR circuit 43 having a circuit configuration equivalent to that of the OR circuit 35 and having a signal delay amount substantially equal to the OR circuit 35;
6, an output buffer 44 having a circuit configuration equivalent to that of the output buffer 36 and a signal delay amount substantially equal to the output buffer 36, and an off-chip driver circuit having a circuit configuration equivalent to the off-chip driver and an equivalent circuit pattern. And the imitation circuit 45 having a signal delay time substantially equal to the above is inserted, the input to the SAD circuit SAD13 is delayed by the sum of the delay times of these circuits, and as a result, the output from the output buffer 18 is output. The internal clock aTx1 or aTx2 is ORed with the internal clock Tu or Td.
The phase is advanced by the signal delay time in the circuit 35, the signal delay time in the output buffer 44, and the signal delay time in the off-chip driver circuit.

The internal clocks aTx1 and aTx2 obtained as described above are input to the OR circuit 35 in FIG. 1 to obtain the clock aTx. The clock aTx is input to the output buffer 36, and the output buffer 36 outputs the internal clock Tx.

Here, the internal clocks aTx1 and aTx1
As Tx2 passes through the OR circuit 35, the phases of the internal clocks aTx1 and aTx2, which have been advanced by the signal delay time in the OR circuit 35, are delayed by that amount to become the clock aTx, and the clock aTx passes through the output buffer 36. As a result, the phase of the internal clock aTx, which has been advanced earlier by the signal delay time in the output buffer 36, is delayed by the clock T
x. Therefore, the obtained internal clock Tx has twice the frequency of the external clock CK, and
The phase of K is advanced by the signal delay time in the off-chip driver circuit.

That is, if the data output operation in the off-chip driver circuit is controlled using this clock Tx, the data output timing from this off-chip driver circuit is synchronized with the external clock CK, The data output operation can be performed without delay.

FIG. 5 is a timing chart showing an example of the operation of the circuit according to the first embodiment. Here, for example, the SAD circuit SAD in the synchronization circuit 31 of FIG.
11 is Δτ1, the SAD circuit SA in the synchronization circuit 32 of FIG.
It is assumed that D12 includes a synchronization error of Δτ2. In this case, as shown in FIG. 5, the internal clock Tu has a synchronization error of Δτ1 with respect to the ideal internal clock Tu having no synchronization error indicated by a broken line. Similarly, the internal clock Td
, A synchronization error of Δτ2 occurs with respect to the ideal internal clock Td indicated by a broken line having no synchronization error. Further, in one of the synchronization circuits 33 shown in FIG. 4, the SAD circuit SAD1
3 (for example, δ3), the output clock aTx1 includes an ideal internal clock aTx without a synchronization error indicated by a broken line.
A synchronization error of Δτ1 + δ3 occurs for x1.

Similarly, in the other synchronization circuit 34 shown in FIG. 4, the synchronization error (for example, δ4) included in the SAD circuit SAD13 is added to the synchronization error Δτ2 included in the internal clock Td. Therefore, the output clock aTx2 has a synchronization error of Δτ2 + δ4 with respect to the ideal internal clock aTx2 having no synchronization error indicated by a broken line. Then, the clocks aTx1 and aT
Thereafter, the OR logic is taken by the OR circuit 35 and x2 does not pass through the SAD circuit, so that the synchronization error included in the clock Tx is Δτ1 + δ3 or Δτ2 + δ4 originally included in the clocks aTx1 and aTx2.

Here, for example, assuming that the synchronization error in each SAD circuit is Δτ as in the prior art, the internal clock Tx
, The synchronization error is at most 2Δτ, and the synchronization error can be reduced as compared with the related art.

FIG. 6 is a block circuit diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to a second embodiment of the present invention. This circuit includes a synchronization circuit 51 that outputs an internal clock aTx1 from an external clock CK, and an internal clock aTx from an external clock CK.
x2, and the two internal clocks a
An OR circuit 53 to which Tx1 and aTx2 are input and an output buffer 54 to which an internal clock aTx output from the OR circuit 53 is input and output an internal clock Tx for controlling an off-chip driver circuit. I have.

The one synchronizing circuit 51 is synchronized with the external clock CK, and is synchronized with the external clock CK by the signal delay time in the OR circuit 53, the signal delay time in the output buffer 54, and the signal in the off-chip driver circuit. The internal clock aTx1 whose phase is advanced by the total signal delay time of the delay time is output.

The other synchronizing circuit 52 synchronizes with the internal clock whose phase is shifted by 180 ° with respect to the external clock CK, and further synchronizes the internal clock CK with the signal delay time in the OR circuit 53 and the output buffer 54. And outputs the internal clock aTx2 whose phase is advanced by the total signal delay time of the signal delay time in the off-chip driver circuit.

FIG. 7 shows a detailed circuit configuration of the synchronization circuit 51 in FIG. This synchronizing circuit 51 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD21, and an output buffer 18, similarly to the synchronizing circuit of FIG. In this synchronous circuit 31, the delay monitor circuit 12 has a delay amount corresponding to a signal delay time in one input buffer 11 and one output buffer 18, respectively.
The delay amount corresponding to the sum of the delay amount corresponding to the signal delay time in the OR circuit 53, the delay amount corresponding to the signal delay time in the output buffer 54, and the delay amount corresponding to the signal delay time in the off-chip driver circuit is provided. Is set.

Specifically, the delay monitor circuit 12
An input buffer 61 having a circuit configuration equivalent to the input buffer 11 in the synchronization circuit 51 and an output buffer 6 having a circuit configuration equivalent to the output buffer 18 in the synchronization circuit 51
6, an OR circuit 63 having a circuit configuration equivalent to the OR circuit 53 in FIG. 6 and having one end grounded, an output buffer 64 having a circuit configuration equivalent to the output buffer 54 in FIG. 6, and an internal clock Tx. It has an equivalent circuit configuration and an equivalent circuit pattern to an unillustrated off-chip driver circuit supplied and whose data output operation is controlled based on this internal clock Tx, and has a signal delay time substantially equal to that of the off-chip driver circuit. The imitation circuit 65 is connected in cascade.

The internal clock aTx1 basically synchronized with the external clock CK is output from the synchronous circuit 51.

However, in the course of the clock propagation path in the delay monitor circuit 12, the OR circuit 5 in FIG.
An OR circuit 63 having a circuit configuration equivalent to that of the OR circuit 3 and having a signal delay amount substantially equal to the OR circuit 53;
4, an output buffer 64 having a circuit configuration equivalent to that of the output buffer 54 and having a signal delay amount substantially equal to the output buffer 54, and a circuit pattern equivalent to the off-chip driver circuit and having an equivalent circuit pattern. Since the circuit and the imitation circuit 65 having a signal delay time substantially equal to the circuit are inserted, the SAD is equivalent to the sum of the delay times of these circuits.
The input to the circuit SAD21 is delayed, and as a result, the internal clock aTx1 output from the output buffer 18 is output.
The phase of the external clock CK is advanced by the signal delay time in the OR circuit 63, the signal delay time in the output buffer 54, and the signal delay time in the off-chip driver circuit.

FIG. 8 shows a detailed circuit configuration of the synchronization circuit 52 in FIG. The synchronization circuit 52 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD22, and an output buffer 18, similarly to the synchronization circuit of FIG. In this synchronous circuit 52, the delay monitor circuit 12 corresponds to a delay amount corresponding to twice the signal delay time in one input buffer 11 and one output buffer 18 and twice the signal delay time in the OR circuit 53. The delay amount, the delay amount corresponding to twice the signal delay time in the output buffer 54, and the total delay amount corresponding to twice the signal delay time in the off-chip driver circuit are set. .

More specifically, the delay monitor circuit 12
Input buffers 71 and 72 having a circuit configuration equivalent to the input buffer 11 in the synchronization circuit 52;
, Output circuits 73 and 74 having a circuit configuration equivalent to the output buffer 18, OR circuits 75 and 76 having a circuit configuration equivalent to the OR circuit 53 in FIG. 6 and having one end grounded, and an output buffer in FIG. Output buffers 77 and 78 having a circuit configuration equivalent to 54 and an internal clock Tx are supplied, and a circuit configuration and a circuit pattern equivalent to an unillustrated off-chip driver whose data output operation is controlled based on the internal clock Tx And mimic circuits 79 and 80 having a signal delay time substantially equal to that of the off-chip driver circuit
Are connected in tandem.

The number of unit delay elements of the backward pulse delay line 16 of the SAD circuit SAD 22 is reduced to half of the number of unit delay elements.

Therefore, the synchronization circuit 52 basically outputs an internal clock whose phase is shifted by 180 ° with respect to the external clock CK. However, in the course of the clock propagation path in the delay monitor circuit 12,
It has a circuit configuration equivalent to the OR circuit 53 in FIG. 6, and has a circuit configuration equivalent to the two OR circuits 75 and 76 with the signal delay amounts substantially equal to the OR circuit 53 and the output buffer 54. Two output buffers 77 and 78 having a signal delay amount substantially equal to the output buffer 54, a circuit configuration equivalent to the off-chip driver circuit and an equivalent circuit pattern, and substantially equivalent to the off-chip driver circuit. Since two imitation circuits 79 and 80 having the same signal delay time are inserted, S is equal to the sum of the delay times of these circuits.
The input to the AD circuit SAD22 is delayed, and as a result, the internal clock aT output from the output buffer 18 is output.
x2 is a signal whose phase is shifted by 180 ° with respect to the external clock CK by a signal delay time in the OR circuit 53, a signal delay time in the output buffer 54, and a signal delay time in the off-chip driver circuit. Hastened.

When the internal clock aTx1 output from the synchronization circuit 51 and the internal clock aTx2 output from the synchronization circuit 52 pass through the OR circuit 53,
The phases of the internal clocks aTx1 and aTx2 previously advanced by the signal delay time in the OR circuit 53 become clocks aTx delayed by that amount and having a frequency twice as high as CK, and this clock aTx is output to the output buffer 54. , The phase of the internal clock aTx advanced in advance by the signal delay time in the output buffer 54 is delayed by the clock T
x. Therefore, the obtained internal clock Tx has twice the frequency of the external clock CK, and
The phase of K is advanced by the signal delay time in the off-chip driver circuit.

That is, if the output operation in the off-chip driver circuit is controlled using this clock Tx, the data output timing from this off-chip driver circuit is synchronized with the external clock CK, and the data output timing with respect to the external clock CK Output operation can be performed without delay.

In this embodiment, the internal clock Tu and the external clock CK synchronized with the external clock CK are used.
The internal clock Td whose phase is shifted by 180 ° is not output. However, if both internal clocks Tu and Td are required, the synchronization circuits 31 and 32 shown in FIGS. 2 and 3 may be provided.

If the internal clocks Tu and Td are not required, the synchronizing circuits 31 and 32 become unnecessary, and the SA
Since only two D circuits need to be provided, the chip area and power consumption can be significantly reduced.

FIG. 9 shows a synchronous circuit 3 for outputting internal clocks Tu and Td in the circuit of the second embodiment.
It is a timing chart which shows an example of the operation at the time of providing 1 and 32. Here, for example, the SAD circuit SAD11 in the synchronization circuit 31 in FIG.
2 includes a synchronization error of Δτ2, and the SAD circuit SAD12 in the synchronization circuit 51 of FIG.
21 is δ3, the SAD circuit SA in the synchronization circuit 52 in FIG.
It is assumed that D22 includes a synchronization error of δ4.

In this case, as shown in FIG. 9, the internal clock aTx1 has a δ3 synchronization error with respect to an ideal internal clock having no synchronization error indicated by a broken line. Similarly,
Also for the internal clock aTx2, a synchronization error of δ4 occurs with respect to an ideal internal clock indicated by a broken line without a synchronization error. Then, the internal clocks aTx1 and aTx2
Is then ORed by the OR circuit 53,
Since the signal does not pass through the SAD circuit, the synchronization error included in the clock Tx originally includes the clocks aTx1 and aTx2.
.Delta.3 or .delta.4 included in.

Here, for example, assuming that the synchronization error in each SAD circuit is Δτ as in the conventional case, the internal clock Tx
Is at most Δτ, and the synchronization error can be further reduced as compared with the circuit of the first embodiment.

In the first and second embodiments, as shown in the timing charts of FIGS. 5 and 9, when the duty of the external clock CK is low, ie, CK
Has been described as a case where the period during which the signal is at the “H” level is sufficiently shorter than the period during which the signal is at the “L” level. However, when the duty of the external clock CK increases, the first period shown in FIG. When the OR logic of the internal clocks aTx1 and aTx2 is obtained by the OR circuit 35 of the embodiment circuit, the “H” level periods of both internal clocks may overlap each other.

In such a case, a pulse circuit is provided on the input side of the OR circuit 35, and the internal clock aT
O1 after shortening the “H” level period of x1 and aTx2
What is necessary is just to take OR logic in the R circuit 35. However, when this pulsing circuit is provided, it is necessary to provide a circuit having a signal delay equivalent to the pulsing circuit in the delay monitor circuits of the synchronization circuits 33 and 34 in order to match the signal delay time.

Next, an off-chip driver circuit for controlling the output of data using the internal clock Tx output from the circuits of the above embodiments and an off-chip driver circuit used in the circuits of the above embodiments are equivalent. An imitation circuit having a large amount of signal delay will be described.

FIG. 10 is a block diagram showing a schematic configuration of the off-chip driver circuit. The off-chip driver circuit 91 applies a voltage signal VD corresponding to output data “1” or “0” to the data Dout generated in the previous stage.
out is output to the output pad at a timing when the output control signal OCDOUT becomes "H" level, for example, so as to be synchronized with the external clock. Also, the output control signal OCDOU
During the period when T is at the "L" level, the voltage signal VDout corresponding to the output data is not output to the output pad, and the output pad is disconnected from the power supply and enters a high impedance state.

Here, the output control signal OCDOUT
Is a signal based on the internal clock Tx shown in FIG. 1 or FIG.

In the I / O section which requires particularly high-speed operation, a method is employed in which two bits of internal data are converted from parallel to serial data into one bit of external data and output. FIG. 11 is a block diagram showing a schematic configuration of the parallel-serial type off-chip driver circuit.

One data Dout 1 generated in the preceding stage is input to the off-chip driver circuit 92, and the other data Dout 2 is input to the off-chip driver circuit 93. The data output operation of the off-chip driver circuits 92 and 93 is performed by the Dout selection circuit 94 to which the output control signal OCDOUT is input. The outputs of the off-chip driver circuits 92 and 93 are commonly connected.

Further, in addition to the output control signal OCDOUT, internal clocks Tu 'and Td' based on the internal clocks Tu and Td shown in FIG. 1 or FIG. 6 are input to the Dout selection circuit 94. And, for example, one D
The out1 selection signal is output in synchronization with the internal clock Tu ', and the other Dout2 selection signal is output from the internal clock Td'.
Is output in synchronization with.

Next, an example of the operation of the off-chip driver circuit configured as shown in FIG. 11 will be described with reference to a timing chart shown in FIG. Now, for example, "H" is set as data Dout1 in one off-chip driver circuit 92.
Of the other off-chip driver circuit 9
It is assumed that data of “L” is input to 3 as data Dout 2. Then, first, the output control signal OCDOU
After T rises to the “H” level, the Dout1 selection signal is output from the Dout selection circuit 94, and one of the off-chip driver circuits 92 is selected to output the data Dout.
A voltage signal VDout corresponding to 1 is output to the output pad. Therefore, voltage signal VDout rises to "H" level.

When the output control signal OCDOUT rises to the “H” level again after dropping to the “L” level, the Dout selection circuit 94 outputs a Dout 2 selection signal. Therefore, the other off-chip driver circuit 93 is selected this time, and the voltage signal VDout falls to “L” level. Since the output pad has a load, the voltage signal VDout lowered to the "L" level is charged through this load, and finally returns to the original state.

As described above, the selection signals of the two off-chip driver circuits are sequentially activated in accordance with the output control signal OCDOUT, and 2-bit data is sequentially output to the output pad.

In the circuit of FIG. 11, there is a predetermined delay time DOCD (for example, 1 nS) from when the output control signal OCDOUT goes to "H" level until the signal is actually output to the output pad. ing. The output control signal OCDOUT needs to be ahead of the external clock by DOCD in order to compensate for the delay time in the off-chip driver circuit.

In the first and second embodiments, the synchronizing circuit (for example, the synchronizing circuit 31 shown in FIGS.
32, 33, 34), the internal clock Tx precedes the external clock CK by the delay time in the off-chip driver circuit. And
In each of the above synchronous circuits, in order to accurately reproduce the delay time corresponding to the DOCD, the synchronous circuit has a circuit configuration equivalent to the off-chip driver circuit, has an equivalent circuit pattern, and has a signal delay equivalent to the off-chip driver circuit. An imitation circuit is used. That is, when the characteristics of the off-chip driver circuit change due to the influence of manufacturing process variations and the like, the characteristics of the mimic circuit also change in the same manner, so that the off-chip driver circuit and the mimic circuit have an equivalent circuit configuration and are equivalent. It is desirable to have a simple circuit pattern.

However, by using the circuit of FIG. 11 as it is as an imitation circuit,
When Dout is set as the output of the imitation circuit, the following problem occurs. For example, in the circuit of FIG.
Consider a case where t1 is fixed at "H" and Dout2 is fixed at "L", and the Dout1 selection signal is activated. D
When the out1 selection signal is activated and becomes “H” level, the off-chip driver circuit 92 is selected, and the voltage signal VDout becomes “H” level. But then, OC
When DOUT goes to "L" level and VDout goes into a high impedance state, VDout remains at the original "H" level and does not drop to "L" level, so that no signal is transmitted to the next stage. Therefore, the circuit shown in FIG. 11 cannot be used as an imitation circuit as it is.

Therefore, a circuit having a configuration as shown in FIG. 13 is used as a simulation circuit corresponding to a 2-bit parallel-serial off-chip driver. The imitation circuit shown in FIG. 13 is provided with two off-chip driver circuits 92 and 93 and a Dout selection circuit 94 similarly to the circuit shown in FIG. However, the difference from the circuit of FIG. 11 is that instead of using the Dout2 selection signal,
That is, the t1 selection signal is inverted using the inverter 95 and used for the selection operation of the off-chip driver circuit 93.

According to the imitation circuit having such a configuration, FIG.
As shown in the timing chart of FIG.
Dout after CDOUT rises to “H” level
1 selection signal is activated and the off-chip driver circuit 9
2 is selected, and the voltage signal VDout goes to the “H” level. Next, when the output control signal OCDOUT falls to the “L” level, the Dout1 selection signal becomes inactive, and the selection state of the off-chip driver 92 is released.
Further, when the Dout1 selection signal becomes inactive,
The output of the inverter 95 becomes “H” level, and the off-chip driver circuit 93 is selected this time, and the voltage signal VD
out falls to the “L” level. That is, when such a circuit is used, if a clock is input as the output control signal OCDOUT, the voltage signal VDout as a clock delayed by the delay time DOCD rises, and the voltage signal VDout is output from the output control signal OCDOUT.
The delay time until this is the same as the actual off-chip driver circuit.

The signal for selecting the off-chip driver circuit 93 is delayed by the signal delay time in the inverter 95, which is caused by the voltage signal VDout.
Of the voltage signal VDout does not affect the rise of the voltage signal VDout.

In an actual off-chip driver circuit, a pad having a predetermined pattern is formed at a node to which the voltage signal VDout is output. This pad acts as a load for the voltage signal VDout. Therefore, in order to accurately match the signal delay time in the imitation circuit with the actual off-chip driver circuit, a dummy pad 96 having the same pattern as the actual pad is provided at the node of the voltage signal VDout of the imitation circuit. What should I do?

In the off-chip driver circuit, it is preferable that the delay time when outputting "H" level data is the same as the delay time when outputting "L" level data. May be different.

FIG. 15 is a timing chart in the case where the delay time at the time of outputting "H" level data is short in the 2-bit parallel-serial type off-chip driver circuit shown in FIG. In this case, the input data Dout1 of one off-chip driver circuit 92 is fixed at “H” level, and the input data Dout2 of the other off-chip driver circuit 93 is fixed at “L” level. As shown, the off-chip driver circuit 92
Is selected and the delay time DOCDH when the voltage signal VDout rises to the “H” level is short.

On the other hand, FIG. 16 shows a timing chart when the delay time at the time of outputting the "L" level data is long. In this case, one off-chip driver 92
Is fixed at “L” level, and the input data Dout of the other off-chip driver circuit 93 is fixed at “L” level.
2 is fixed at the “H” level. As shown, the off-chip driver circuit 92 is selected and the voltage signal VDo
delay time DOCDL when ut falls to “L” level
Is long.

The cause of the difference between the two delay times is the difference in the circuit system, that is, “H” of the P-channel and N-channel MOS transistors constituting the off-chip driver circuit.
This is due to the case where the channel width of the P-channel MOS transistor outputting the level is sufficiently larger than the channel width of the N-channel MOS transistor outputting the “L” level, or due to a variation in the manufacturing process.

In this case, as shown in FIG. 11, input data Dout1 is set to "H" level and input data Dout2 is set to "H" level.
In the imitation circuit where is fixed at the “L” level, the delay time when the input clock rises to the “H” level and the output clock rises to the “H” level can be accurately reproduced. However, the delay time when the output data of the off-chip driver circuit falls to the “L” level cannot be accurately reproduced, and the error increases.

Therefore, the signal delay time in the off-chip driver circuit when the output data of the off-chip driver circuit changes to "H" level and "L" level is compensated for and output in synchronization with an external clock. A possible third embodiment of the present invention will be described below.

FIG. 17 is a block diagram of an off-chip driver control signal generating circuit according to the third embodiment. In the figure, reference numeral 101 denotes, for example, a circuit similar to the off-chip driver control signal generation circuit according to the first embodiment shown in FIG. 1 or the off-chip driver control signal generation circuit according to the second embodiment shown in FIG. Having the configuration,
The imitation circuit 45 in FIG. 4 or the imitation circuit 65 in FIG. 7 and the imitation circuits (79, 80) in FIG.
This is an output control signal generating circuit having a circuit configuration similar to that of the first embodiment, and having a mimic circuit 102 having a signal delay time equivalent to the signal delay time when outputting "H" level data in the off-chip driver circuit.

Reference numeral 103 denotes, for example, the same as the off-chip driver control signal generation circuit according to the first embodiment shown in FIG. 1 or the off-chip driver control signal generation circuit according to the second embodiment shown in FIG. And the imitation circuit 45 in FIG. 4 or the imitation circuit 65 in FIG. 7 and the imitation circuits 79 and 8 in FIG.
This is an output control signal generation circuit having a circuit configuration similar to that of (0), and having an imitation circuit 104 having a signal delay time equivalent to the signal delay time when outputting "L" level data in the off-chip driver circuit.

The output control signal OCDOUTH output from the one output control signal generation circuit 101 and the output control signal OCDOUTL output from the other output control signal generation circuit 103 are output from the off-chip driver circuit 10.
5 is input.

FIG. 18 shows the off-chip driver circuit 1
It is a block diagram which shows the structure of 05. In this circuit, the output control signal OCDOUTH is input corresponding to the Dout selection circuit 94 in FIG. 11, and a Dout selection circuit 94a that outputs a Dout1 selection signal and a Dout2 selection signal in accordance with the output control signal OCDOUTH; The output control signal OCDOUTL is input, and Do
Do that outputs an out1 selection signal and a Dout2 selection signal
out selection circuit 94b.

The two-system selection signals output from the two Dout selection circuits 94a and 94b are supplied to a selection circuit 97 provided for each of the off-chip driver circuits (only 92 is shown).
Is input to The selection circuit 97 detects the level of the data Dout1 for the off-chip driver circuit 92, and according to the detected level, the Dout selection circuit 9
4a and 94b are selected and output to the corresponding off-chip driver circuit 92.

Here, when the off-chip driver circuit 92 outputs data “Dout1” of “H” level,
The selection signal from the Dout selection circuit 94 a is selected by the selection circuit 97 and is input to the off-chip driver circuit 92. On the other hand, when the off-chip driver circuit 92 outputs “L” level data Dout 1, the selection signal from the Dout selection circuit 94 b is selected by the selection circuit 97 and input to the off-chip driver circuit 92.

Therefore, in this embodiment, even when the delay time from the data selection signal to the data output differs between when the "H" level data is selected and when the "L" level data is selected, the respective delay times are different. Since the selection operation is controlled using the output selection signal preceding by the amount, data can be output in any case in synchronization with the external clock.

The present invention is not limited to the above embodiments, and it goes without saying that various modifications are possible. For example, in each embodiment, the case where the internal clock Tx synchronized with the external clock CK is output has been described. However, this is not the case of the external clock CK but the internal clock Tx output from another synchronization circuit provided inside the chip. The internal clock Tx may be output from the clock, or the internal clock Tx may be output from an asynchronous clock that is not output from another synchronous circuit inside the chip.

In the third embodiment shown in FIG. 17, output control signal generating circuits 103 and 104 for generating one and the other output control signals are respectively provided, for example, in FIG.
Using a control signal generation circuit for off-chip driver according to the first embodiment shown in FIG. 6 or a control signal generation circuit for off-chip driver according to the second embodiment shown in FIG. However, the present invention is not limited to this. In short, what is necessary is to generate an internal clock capable of compensating a signal delay time at the time of outputting “H” level and “L” level data in an off-chip driver circuit. Can be used.

[0101]

As explained above, according to the present invention,
It is possible to provide a semiconductor integrated circuit including an off-chip driver control signal generation circuit capable of reducing a synchronization error without using a PLL circuit or a DLL circuit.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a control signal generation circuit for an off-chip driver provided in a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a detailed circuit configuration of a synchronization circuit 31 in FIG. 1;

FIG. 3 is a diagram showing a detailed circuit configuration of a synchronization circuit 32 in FIG. 1;

FIG. 4 is a diagram showing a detailed circuit configuration of synchronization circuits 33 and 34 in FIG. 1;

FIG. 5 is a timing chart showing an example of the operation of the circuit according to the first embodiment;

FIG. 6 is a block circuit diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a detailed circuit configuration of a synchronization circuit 51 in FIG. 6;

FIG. 8 is a diagram showing a detailed circuit configuration of a synchronization circuit 52 in FIG. 6;

FIG. 9 is a timing chart showing an example of an operation in the circuit according to the second embodiment;

FIG. 10 is a block diagram showing a schematic configuration of an off-chip driver.

FIG. 11 is a block diagram showing a schematic configuration of a parallel-serial type off-chip driver circuit.

FIG. 12 is a timing chart showing an example of the operation of the off-chip driver circuit of FIG.

FIG. 13 shows a 2-bit parallel data used in the present invention.
FIG. 3 is a circuit diagram of a mimic circuit of a serial off-chip driver circuit.

FIG. 14 is a timing chart showing an operation example of the imitation circuit of FIG. 13;

FIG. 15 is a timing chart showing an operation example when the delay time at the time of outputting “H” level data is short in the off-chip driver circuit shown in FIG. 11;

FIG. 16 is a timing chart showing an operation example when the delay time at the time of outputting “L” level data is short in the off-chip driver circuit shown in FIG. 11;

FIG. 17 is a block diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of an off-chip driver circuit 105 according to the third embodiment.

FIG. 19 is a block diagram of a synchronous circuit of the SAD system.

20 is a timing chart showing an example of the operation of the synchronization circuit shown in FIG.

FIG. 21 is a block circuit diagram of a conventional off-chip driver control signal generation circuit configured using a SAD synchronous circuit.

FIG. 22 is a circuit diagram of a synchronization circuit 21 in FIG. 21;

FIG. 23 is a circuit diagram of a synchronization circuit 22 in FIG. 21;

FIG. 24 is a circuit diagram of a synchronization circuit 24 in FIG. 21;

FIG. 25 is a timing chart showing an operation example of the conventional circuit of FIG. 21;

[Explanation of symbols]

11, 37, 38, 41, 61, 71, 72: input buffer, 12: delay monitor circuit, 14: delay line for forward pulse, 16: delay line for backward pulse, 18, 36, 39, 40, 42, 44 , 54, 62, 6
4, 73, 74, 77, 78 ... output buffer, 31, 32, 33, 34, 51, 52 ... synchronous circuit, 35, 43, 53, 63 ... OR circuit, 45, 65, 79, 80, 102, 104 ... imitation circuit, 91, 92, 93, 105 ... off-chip driver circuit, 94, 94a, 94b ... Dout selection circuit, 95 ... inverter, 96 ... dummy pad, 97 ... selection circuit, 101, 103 ... output control signal generation circuit , SAD11, SAD12, SAD13, SAD21, S
AD22 ... SAD circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822 H03K 19/00 101N 5K047 H03K 19/0175 H04L 7/02 Z H04L 7/02 (72) Invention Person Kenji Tsuchida 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture, in the Toshiba Yokohama Office (72) Inventor Haruki Toda 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa, Japan F-term (reference) 5B024 AA03 BA21 BA29 CA11 5B079 BA20 BB10 BC03 CC02 CC14 DD06 DD20 5F038 CA10 CD06 CD08 CD09 DF01 DF05 DF07 DF16 DT12 EZ20 5F064 BB01 BB14 BB27 BB28 BB37 DD32. KK15 MM36 MM53

Claims (14)

[Claims] 1. An off-chip driver circuit that outputs data based on an output control signal and has a predetermined signal delay time from output control signal to data output, and a first clock, A first synchronizing circuit for outputting a second clock synchronized with the second clock and having a phase advanced by at least a signal delay time in the off-chip driver circuit; a third clock being input; A second synchronizing circuit that outputs a fourth clock whose phase is advanced at least by a signal delay time in the off-chip driver circuit and whose frequency is different from the second clock; and And the fourth clock are input, and a fifth clock for controlling a data output operation in the off-chip driver circuit is output. And an OR circuit. 2. The method according to claim 1, wherein the first synchronizing circuit includes the OR circuit in addition to a signal delay time in the off-chip driver circuit.
The second clock is configured to output the second clock so as to advance the phase by the signal delay time in the circuit, and the second synchronization circuit is configured to output the second clock in addition to the signal delay time in the off-chip driver circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the fourth clock is output so as to advance the phase by an amount corresponding to a signal delay time in an OR circuit. 3. The semiconductor device according to claim 1, wherein at least one of the first clock input to the first synchronization circuit and the third clock input to the second synchronization circuit is provided inside a chip. 2. The semiconductor integrated circuit according to claim 1, wherein the internal clock is an internal clock output from a synchronous circuit. 4. An external clock or an internal chip in which both the first clock input to the first synchronization circuit and the third clock input to the second synchronization circuit are input from outside the chip. 2. The semiconductor integrated circuit according to claim 1, wherein the clock is not output from another synchronous circuit. 5. Each of the first and second synchronization circuits has a delay monitor circuit to which a clock is input, a forward pulse delay line and a backward pulse delay line, and wherein the clock and the delay monitor circuit And the output pulse from the delay monitor circuit after the input of the clock in the first cycle is delayed for a predetermined time by the forward pulse delay line, and in the next cycle of the first cycle. After the arrival of the clock of a certain second cycle, the clock of the second cycle is shifted backward by the time corresponding to the delay time of the output pulse from the delay monitor circuit delayed by the forward pulse delay line or by half the time. 2. A synchronous adjustment delay circuit for delaying and outputting a delayed signal by a pulse delay line.
3. The semiconductor integrated circuit according to claim 1. 6. The circuit according to claim 5, wherein a mimic circuit having substantially the same circuit configuration as the off-chip driver circuit is inserted in the propagation path of the clock in the delay monitor circuit. Semiconductor integrated circuit. 7. The first off-chip driver imitation circuit having substantially the same circuit configuration as the off-chip driver circuit, wherein input data is fixed at an “L” level; A second off-chip driver imitation circuit having substantially the same circuit configuration as the driver circuit, the output of which is commonly connected to the output of the first off-chip driver imitation circuit, and the input data fixed at "H" level And the fifth clock output from the OR circuit is a first clock.
The first off-chip driver imitation circuit is selectively operated when the logic level is
7. The semiconductor integrated circuit according to claim 6, further comprising: an off-chip driver selection control circuit that selectively operates the second off-chip driver imitation circuit when the logic level is equal to the above. 8. A dummy pad having a capacitance equivalent to a pad connected to an output of the off-chip driver circuit is connected to an output common connection point of the first and second off-chip driver imitation circuits. The semiconductor integrated circuit according to claim 7, wherein: 9. The semiconductor integrated circuit according to claim 8, wherein the pattern of the dummy pad has a pattern equivalent to the pad connected to the output of the off-chip driver circuit. 10. An off-chip driver circuit that outputs data based on an output control signal and has a different signal delay time from an output control signal to data output when outputting "H" level data and when outputting "L" level data. A first output control signal generation circuit for generating a first output control signal used when outputting the "H" level data in the off-chip driver circuit; and outputting the "L" level data in the off-chip driver circuit A second output control signal generating circuit for generating a second output control signal used at the time. 11. The first output control signal generating circuit receives a first clock, synchronizes with the first clock, and outputs at least “H” level data from the off-chip driver circuit. A first synchronous circuit that outputs a second clock whose phase has been advanced by a signal delay time from the first output control signal to the data output, and a third clock, and the third clock is input to the third clock. Synchronous and at least “H” from the off-chip driver circuit.
A second synchronization in which the phase is advanced by a signal delay time from the first output control signal to the data output when the level data is output and a fourth clock different in frequency from the second clock is output. A second clock for inputting the second clock and the fourth clock, and outputting a fifth clock for controlling a data output operation when “H” level data is output from the off-chip driver circuit; The second output control signal generating circuit receives a sixth clock, synchronizes with the sixth clock, and at least outputs an “L” level signal from the off-chip driver circuit. A third synchronizing circuit for outputting a seventh clock whose phase is advanced by a signal delay time from the second output control signal to data output when data is output, and an eighth clock. The phase is synchronized with the eighth clock and the phase is at least the signal delay time from the second output control signal to the data output when the "L" level data is output from the off-chip driver circuit. A fourth synchronizing circuit that outputs a ninth clock that is advanced and has a different frequency from the seventh clock, and the seventh clock and the ninth clock are input, and “ 11. The semiconductor device according to claim 10, further comprising: a second OR circuit for outputting a tenth clock for controlling a data output operation when L "level data is output. Integrated circuit. 12. The first and second synchronization circuits respectively increase the phase of the second OR circuit so as to advance the phase by the signal delay time of the first OR circuit in addition to the signal delay time of the off-chip driver circuit. And a fourth clock, respectively, and the third and fourth synchronization circuits respectively include the second O.sub.2 signal in addition to the signal delay time in the off-chip driver circuit.
12. The semiconductor integrated circuit according to claim 11, wherein said seventh and ninth clocks are respectively output so as to advance the phase by a signal delay time in the R circuit. 13. Each of the first to fourth synchronizing circuits has a delay monitor circuit to which a clock is input, a forward pulse delay line and a backward pulse delay line, wherein the clock and the delay monitor circuit And the output pulse from the delay monitor circuit after the input of the clock in the first cycle is delayed for a predetermined time by the forward pulse delay line, and in the next cycle of the first cycle. After the arrival of the clock of a certain second cycle, the clock of the next second cycle is changed by the time corresponding to the delay time of the output pulse from the delay monitor circuit delayed by the forward pulse delay line or half of the time. 12. The semiconductor device according to claim 11, further comprising: a synchronous adjustment delay circuit that delays and outputs the delayed signal by the backward pulse delay line. Integrated circuit. 14. The delay monitor circuit according to claim 11, wherein a mimic circuit having substantially the same circuit configuration as the off-chip driver circuit is inserted in the propagation path of the clock in the delay monitor circuit. Semiconductor integrated circuit.