JP4050763B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having an off-chip driver circuit that outputs data inside a chip to the outside, and more particularly to an off-chip driver control signal generating circuit that generates an internal clock used for data output control in the off-chip driver circuit. The present invention relates to a semiconductor integrated circuit provided.

  In recent years, in an I / O portion of a semiconductor integrated circuit such as a semiconductor memory such as a DRAM, data is input / output in synchronization with both rising and falling edges of an external clock. Such a method is called a DDR (Double Data Rate) method, which is twice as fast as when data is input / output in synchronization with either the rising or falling edge of the external clock. Data can be input and output.

  In addition, in order to perform data input / output in synchronization with both the rising and falling edges of the external clock, the internal clock Tu synchronized with the rising edge of the external clock and the falling edge of the external clock in the chip. Three types of internal clock Td synchronized and internal clock Tw synchronized with both rising and falling edges of the external clock are generated.

  Further, in an off chip driver (OCD) circuit that is a data output circuit provided in the I / O portion of the chip, a delay time from input of an internal clock for performing data output control to data output is large. In this case, it is necessary to generate the internal clock in consideration of the delay time in the OCD circuit. That is, when the delay time in the OCD circuit cannot be ignored, it is necessary to generate an internal clock for controlling the operation of the OCD circuit in advance by the delay time in the OCD circuit.

  By the way, various synchronization circuit methods for synchronizing the internal clock with the external clock have been considered, and among them, disclosed in SMD (Synchronous Mirror Delay) used in Non-Patent Document 1 and Patent Document 1. The SAD (Synchronous Adjustable Delay, Synchronous Adjustable Delay) system including STBD (Synchronous Traced Backward Delay) is often used because of its high synchronization speed and low power consumption.

  Here, the principle of the SAD type synchronization circuit disclosed in Patent Document 1 will be described.

  FIG. 19 is a block diagram of a SAD type synchronization circuit.

  This synchronization circuit has the same number of input buffer 11, delay monitor circuit 12, forward pulse delay line 14 composed of a plurality of unit delay elements 13 connected in cascade, and unit delay elements 13 in forward pulse delay line 14. The number of state holding circuits equal to the number of unit delay elements provided in the backward pulse delay line 16, the forward pulse delay line 14, and the backward pulse delay line 16, each of which is composed of the unit delay elements 15 connected in a multistage cascade. (Not shown), and a control circuit 17 for controlling the pulse delay operation in the backward pulse delay line 16 in accordance with the pulse delay state in the forward pulse delay line 14, and an output from the backward pulse delay line 16 The output buffer 18 is input. In FIG. 19, a circuit including the forward pulse delay line 14, the backward pulse delay line 16, and the control circuit 17 is referred to as a SAD circuit SAD.

  FIG. 20 is a timing chart showing an example of the operation of the synchronization circuit shown in FIG. Consider a case where an external clock CK having a period τ is input to the input buffer 11 as shown in FIG. The external clock CK is shaped and amplified by the input buffer 11 and output as a pulse CLK. If the delay time in the input buffer 11 is now D1, the pulse CLK is delayed by D1 with respect to the external clock CK as shown in FIG. The pulse CLK output from the input buffer 11 is input to the delay monitor circuit 12 and the control circuit 17 of the SAD circuit SAD.

  The delay monitor circuit 12 has a delay time A (= D1 + D2) equal to the sum of the delay time D1 in the input buffer 11 and the delay time D2 in the output buffer 18. Therefore, as shown in FIG. 20, the pulse output from the delay monitor circuit 12 is input to the forward pulse delay line 14 as the signal Din after a delay of A from the pulse CLK output from the input buffer 11.

  As described above, the forward pulse delay line 14 includes a plurality of unit delay elements 13 connected in cascade. Then, during a period until the pulse CLK of the next cycle is input to the control circuit 17, the signal Din is sequentially delayed by the plurality of unit delay elements 13 connected in cascade. The backward pulse delay line 16 sequentially delays the next cycle pulse CLK after the next cycle pulse CLK is input to the control circuit 17, and the delay operation is controlled by the control circuit 17. Here, the control circuit 17 operates the backward pulse delay line 16 based on the forward pulse propagation state in the forward pulse delay line 14 so that the backward pulse propagation time becomes equal to the forward pulse propagation time. Control. Therefore, the pulse CLK of the next cycle is delayed by the time of (τ−A) by the backward pulse delay line 16. The output Dout from the backward pulse delay line 16 is delayed by the time D2 by the output buffer 18 and output as the internal clock CK '.

  Here, assuming that the delay time from the input of the external clock CK to the output of the internal clock CK ′ is Δtotal, Δtotal is expressed as follows.

Δtotal = D1 + A + 2 (τ−A) + D2 (1)
Here, since D1 + D2 = A, Δtotal is 2τ, and the internal clock CK ′ is synchronized with the external clock CK from the third clock of the external clock CK.

  19, the delay time in the backward pulse delay line 16 is reduced by reducing the number of unit delay elements 15 in the backward pulse delay line 16 to half the number of unit delay elements 13 in the forward pulse delay line 14. Is set to be half of the delay time in the forward pulse delay line 14, and the delay time in the delay monitor circuit 12 is set to twice the delay time (2A) in FIG. 19, the internal clock CK 'is It is shifted by 180 ° with respect to the external clock CK.

  FIG. 21 is a block circuit diagram of a conventional off-chip driver control signal generating circuit configured using such a SAD type synchronization circuit. This circuit includes a synchronization circuit 21 that generates an internal clock Tu synchronized with the external clock CK from an external clock CK, and a synchronization that generates an internal clock Td whose phase is shifted by 180 ° with respect to the external clock CK from the external clock CK. A circuit 22, an OR circuit 23 that receives the internal clocks Tu and Td and generates an internal clock Tw, and a synchronization circuit 24 that generates an internal clock Tx having a frequency twice that of the external clock CK from the internal clock Tw. It is composed of

  As shown in FIG. 22, the synchronization circuit 21 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD1, and an output buffer 18, similarly to the synchronization circuit of FIG. In the synchronization circuit 21, the delay monitor circuit 12 is set to have a delay amount corresponding to the signal delay time in one input buffer and one output buffer. The synchronization circuit 21 outputs an internal clock Tu that is synchronized with the external clock CK.

  As shown in FIG. 23, the synchronization circuit 22 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD2, and an output buffer 18, similarly to the synchronization circuit of FIG. In the synchronization circuit 21, the delay monitor circuit 12 is set to have a delay amount corresponding to the signal delay time in each of the two input buffers and the output buffer. Further, the number of unit delay elements of the backward pulse delay line 16 of the SAD circuit SAD2 is reduced to half of the number of unit delay elements. Accordingly, the synchronization circuit 22 outputs an internal clock Td whose phase is shifted by 180 ° with respect to the external clock CK.

  Then, when both the internal clocks Tu and Td are input to the OR circuit 23 in FIG. 21, an internal clock Tw having a frequency twice that of the external clock CK is output. However, since the internal clock Tw output from the OR circuit 23 includes the signal delay time in the OR circuit 23, it cannot be used as a control clock for controlling the off-chip driver circuit.

  Therefore, the internal clock Tw output from the OR circuit 23 is input to the synchronization circuit 24, and the internal clock Tx in which the signal delay time in the OR circuit 23 is compensated is obtained.

  As shown in FIG. 24, the synchronization circuit 24 includes a delay monitor circuit 12, an SAD circuit SAD3, and an output buffer 18. In this case, the delay monitor circuit 12 includes an OR circuit 25 having a delay time equivalent to the OR circuit 23 and an output buffer 26 having a delay time equivalent to the output buffer 18.

  In the synchronizing circuit 24 shown in FIG. 24, the signal delay time in the OR circuit 23 in FIG. 21 and the signal delay time in the output buffer 18 that outputs the internal clock Tx are compensated, and the internal frequency has twice the frequency of the external clock CK. A clock Tx is obtained.

  By the way, the internal clock Tx must have a large driving capability in order to be distributed to each part of the chip. For this reason, the output buffer 18 in the synchronization circuit 24 needs to have a large buffer capability. In order to compensate for the delay time in the output buffer 18, a synchronization circuit using an SAD circuit as shown in FIG. 24 is required.

The synchronization circuit 24 is also required when the delay time in the OCD is large and the internal clock Tx needs to be preceded by the delay amount with respect to the external clock.
T. Saeki et al. "A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay" ISSCC Digest of technical papers Japanese Patent Laid-Open No. 10-69326

  By the way, even if each synchronization circuit is synchronized, each synchronization circuit has a synchronization error as an offset. For example, it is assumed that the SAD circuit SAD1 in FIG. 22 includes a synchronization error of Δτ1, and the SAD circuit SAD2 in FIG. In this case, as shown in the timing chart of FIG. 25, the internal clock Tu has a synchronization error of Δτ1 with respect to an ideal internal clock Tu having no synchronization error indicated by a broken line. Similarly, with respect to the internal clock Td, a synchronization error of Δτ2 occurs with respect to the ideal internal clock Td indicated by a broken line with no synchronization error. The cycle of the internal clock Tw after taking the OR logic of both the internal clocks Tu and Td alternately changes between τ1 and τ2. Both the periods τ1 and τ2 are expressed by the following equations, respectively.

τ1 = (1/2) τ + (Δτ1-Δτ2) (2)
τ2 = (1/2) τ− (Δτ1−Δτ2) (3)
Then, from the internal clock Tw having the cycle τ1 indicated by C1 in FIG. 25 and the internal clock Tw having the cycle τ2 indicated by the next C2, the internal circuit indicated by C3 in FIG. 25 is used by using the synchronization circuit 24 in FIG. When an attempt is made to generate the clock Tx, the deviation of the clock C3 from the ideal internal clock Tx indicated by the broken line when there is no synchronization error in the SAD circuit SAD3 is −Δτ1 + 2Δτ2. Here, as shown in FIG. 25, if the difference between Δτ1 and Δτ2 is opposite to each other, the difference between the internal clock Tx (C3) and the ideal Tx becomes very large.

  For example, if Δτ1 = Δτ and Δτ2 = −Δτ, even if it is assumed that there is no synchronization error in the SAD circuit SAD3, the phase shift is amplified three times by 3Δτ in the SAD circuit SAD3. If a further synchronization error of Δτ occurs in the SAD circuit SAD3, there is a problem that a synchronization error of 4Δτ and four times the error generated in each SAD circuit occurs in the internal clock Tx.

  Thus, in the conventional off-chip driver control signal generation circuit shown in FIG. 21, the synchronization error is amplified by each SAD circuit. Therefore, when this amplified error becomes a problem in the operation of the chip, it is necessary to use a PLL (Phase Locked Loop) circuit or a DLL (Delay Locked Loop) circuit instead of the SAD circuit SAD3.

  However, since the PLL circuit and the DLL circuit have larger power consumption and slower synchronization speed than the SAD circuit, there is a problem that the overall power consumption increases and the synchronization speed becomes slower.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide an off-chip driver circuit regardless of whether the output data of the off-chip driver circuit is at either “H” level or “L” level. It is an object to provide a semiconductor integrated circuit including an off-chip driver control signal generation circuit capable of compensating for the signal delay time.

  The semiconductor integrated circuit of the present invention outputs data based on the output control signal, and the signal delay time from the output control signal to the data output at the time of “H” level data output and “L” level data output is different from off-chip. A driver circuit, a first output control signal generation circuit for generating a first output control signal used when outputting "H" level data in the off-chip driver circuit, and an "L" level in the off-chip driver circuit And a second output control signal generation circuit for generating a second output control signal used when outputting data.

  According to the present invention, the off-chip driver control signal that can compensate for the signal delay time in the off-chip driver circuit even if the output data of the off-chip driver circuit is at either the “H” level or the “L” level. A semiconductor integrated circuit including a generation circuit can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block circuit diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to a first embodiment of the present invention. This circuit outputs a synchronous circuit 31 that outputs an internal clock Tu synchronized with the external clock CK from an external clock CK, and a synchronous circuit 31 that outputs an internal clock Td whose phase is shifted by 180 ° with respect to the external clock CK. A synchronization circuit 33 that receives the internal clock Tu and outputs the internal clock aTx1 whose phase is advanced at least by the signal delay time in the off-chip driver circuit; and the internal clock Tu Td is inputted, and the synchronizing circuit 34 for outputting the internal clock aTx2 which is synchronized with the internal clock Td and whose phase is advanced at least by the signal delay time in the off-chip driver circuit, and both the internal clocks aTx1 and aTx2 are inputted. OR circuit 35 and the OR circuit 35 Internal clock aTx output are input, and an output buffer 36 for outputting an internal clock Tx.

  Here, the internal clock Tx output from the output buffer 36 is used as a control clock for controlling a data output operation in an off-chip driver circuit provided in the same semiconductor integrated circuit. In this case, the internal clock Tx has a frequency twice that of the external clock CK, and is used as a control clock according to the previous DDR system.

  FIG. 2 shows a detailed circuit configuration of the synchronization circuit 31 in FIG. The synchronization circuit 31 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD11, and an output buffer 18, similarly to the synchronization circuit of FIG. In the synchronization circuit 31, the delay monitor circuit 12 is set to have a delay amount corresponding to the signal delay time in one input buffer and one output buffer. A plurality of unit delay elements are provided in the backward pulse delay line 16 of the SAD circuit SAD11. The synchronization circuit 31 outputs an internal clock Tu that is synchronized with the external clock CK.

  FIG. 3 shows a detailed circuit configuration of the synchronization circuit 32 in FIG. The synchronization circuit 32 includes the input buffer 11, the delay monitor circuit 12, the SAD circuit SAD 12, and the output buffer 18 as in the synchronization circuit of FIG. In the synchronization circuit 32, the delay monitor circuit 12 is set to have a delay amount corresponding to the signal delay time in each of the two input buffers and the output buffer.

  Specifically, the delay monitor circuit 12 includes two input buffers 37 and 38 each having an equivalent circuit configuration to the input buffer 11 in the synchronization circuit 32 and an equivalent circuit configuration to the output buffer 18 in the synchronization circuit 32. The output buffers 39 and 40 are connected in cascade.

Further, the number of unit delay elements of the backward pulse delay line 16 of the SAD circuit SAD12 is reduced to half of the number of unit delay elements. Accordingly, the synchronization circuit 32 outputs an internal clock Td whose phase is shifted by 180 ° with respect to the external clock CK.

  FIG. 4 shows a detailed circuit configuration of the synchronization circuits 33 and 34 in FIG. The synchronization circuits 33 and 34 will be described together because the input clock of the synchronization circuit 33 is Tu and the input clock of the synchronization circuit 34 is only different from the input clock Td.

  The synchronization circuits 33 and 34 are composed of an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD13, and an output buffer 18, similarly to the synchronization circuit of FIG. In the synchronization circuits 33 and 34, the delay monitor circuit 12 includes a delay amount corresponding to the signal delay time in one input buffer and an output buffer, and a delay amount corresponding to the signal delay time in the OR circuit 35 in FIG. The delay amount corresponding to the signal delay time in the output buffer 36 in FIG. 1 to which the output of the OR circuit 35 is input and the total delay amount corresponding to the signal delay time in the off-chip driver circuit are provided. Is set to

  Specifically, the delay monitor circuit 12 includes an input buffer 41 having a circuit configuration equivalent to the input buffer 11 in the synchronization circuits 33 and 34, and an output buffer having a circuit configuration equivalent to the output buffer 18 in the synchronization circuits 33 and 34. 42, an OR circuit 43 having a circuit configuration equivalent to the OR circuit 35 in FIG. 1 and grounded at one end, an output buffer 44 having a circuit configuration equivalent to the output buffer 36 in FIG. 1, and an internal clock Tx It has a circuit configuration equivalent to an off-chip driver circuit (not shown) whose data output operation is controlled based on this internal clock Tx and an equivalent circuit pattern, and has a signal delay time substantially equal to that of the off-chip driver circuit. The imitation circuit 45 is connected in cascade.

  The synchronization circuits 33 and 34 basically output the internal clock aTx1 or aTx2 synchronized with the internal clock Tu or Td.

  However, in the middle of the clock propagation path in the delay monitor circuit 12, an OR circuit 43 having a circuit configuration equivalent to the OR circuit 35 in FIG. An output buffer having an equivalent circuit configuration to the output buffer, an output buffer having substantially the same signal delay as the output buffer, an equivalent circuit pattern to an off-chip driver, and an equivalent circuit pattern, Since the mimic circuit 45 having a signal delay time substantially equal to that of the driver circuit is inserted, the input to the SAD circuit SAD13 is delayed by the sum of the delay times of these circuits, and as a result, from the output buffer 18 The internal clock aTx1 or aTx2 to be output is a signal delay time in the OR circuit 35 with respect to the internal clock Tu or Td. Signal delay time by a phase is early in the signal delay time and the off-chip driver circuit in the output buffer 44 and.

  Then, the internal clocks aTx1 and aTx2 obtained in this way are input to the OR circuit 35 in FIG. 1 to obtain the clock aTx. The clock aTx is input to the output buffer 36, and the internal clock Tx is output from the output buffer 36.

  Here, when the internal clocks aTx1 and aTx2 pass through the OR circuit 35, the phases of the internal clocks aTx1 and aTx2, which have been advanced by the signal delay time in the OR circuit 35 in advance, are delayed by that amount, and the clock aTx. When the clock aTx passes through the output buffer 36, the phase of the internal clock aTx that has been advanced by the signal delay time in the output buffer 36 in advance is delayed by that amount to become the clock Tx. Therefore, the obtained internal clock Tx has a frequency twice that of the external clock CK, and the phase is advanced by the signal delay time in the off-chip driver circuit with respect to the external clock CK.

  That is, if the data output operation in the off-chip driver circuit is controlled using the clock Tx, the data output timing from the off-chip driver circuit is synchronized with the external clock CK, and the data output operation with respect to the external clock CK is performed. Can keep up with the delay.

  FIG. 5 is a timing chart showing an example of the operation in the circuit of the first embodiment. Here, for example, it is assumed that the SAD circuit SAD11 in the synchronization circuit 31 of FIG. 2 includes a synchronization error of Δτ1, and the SAD circuit SAD12 in the synchronization circuit 32 of FIG. 3 includes a synchronization error of Δτ2. In this case, as shown in FIG. 5, the internal clock Tu has a synchronization error of Δτ1 with respect to an ideal internal clock Tu having no synchronization error indicated by a broken line. Similarly, with respect to the internal clock Td, a synchronization error of Δτ2 occurs with respect to the ideal internal clock Td indicated by a broken line with no synchronization error. In addition, in one of the synchronization circuits 33 shown in FIG. 4, the synchronization error (for example, δ3) included in the SAD circuit SAD13 is only added to the synchronization error Δτ1 included in the internal clock Tu. The output clock aTx1 has a synchronization error of Δτ1 + δ3 with respect to an ideal internal clock aTx1 having no synchronization error indicated by a broken line.

  Similarly, in the other synchronization circuit 34 shown in FIG. 4, the synchronization error (for example, δ4) included in the SAD circuit SAD13 is only added to the synchronization error Δτ2 included in the internal clock Td. Therefore, the output clock aTx2 has a synchronization error of Δτ2 + δ4 with respect to an ideal internal clock aTx2 having no synchronization error indicated by a broken line. Then, since the clocks aTx1 and aTx2 are ORed by the OR circuit 35 and do not pass through the SAD circuit, the synchronization error included in the clock Tx is Δτ1 + δ3 or Δτ2 + δ4 originally included in the clocks aTx1 and aTx2. It becomes.

  Here, for example, if the synchronization error in each SAD circuit is Δτ as in the conventional case, the synchronization error included in the internal clock Tx is at most 2Δτ, and the synchronization error can be reduced as compared with the conventional case.

  FIG. 6 is a block circuit diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to the second embodiment of the present invention. This circuit includes a synchronization circuit 51 that outputs the internal clock aTx1 from the external clock CK, a synchronization circuit 52 that outputs the internal clock aTx2 from the external clock CK, an OR circuit 53 to which the internal clocks aTx1 and aTx2 are input, The internal clock aTx output from the OR circuit 53 is input, and the output buffer 54 outputs the internal clock Tx for controlling the off-chip driver circuit.

  The one synchronizing circuit 51 is synchronized with the external clock CK, and for this external clock CK, the signal delay time in the OR circuit 53, the signal delay time in the output buffer 54, and the signal delay time in the off-chip driver circuit. The internal clock aTx1 whose phase is advanced by the total signal delay time is output.

  The other synchronizing circuit 52 synchronizes with an internal clock whose phase is shifted by 180 ° with respect to the external clock CK, and further, with respect to this internal clock CK, a signal delay in the OR circuit 53 and a signal delay in the output buffer 54. The internal clock aTx2 whose phase is advanced by the sum of the signal delay time of the time and the signal delay time in the off-chip driver circuit is output.

  FIG. 7 shows a detailed circuit configuration of the synchronization circuit 51 in FIG. The synchronization circuit 51 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD21, and an output buffer 18, similarly to the synchronization circuit of FIG. In this synchronization circuit 31, the delay monitor circuit 12 includes a delay amount corresponding to the signal delay time in one input buffer 11 and the output buffer 18, a delay amount corresponding to the signal delay time in the OR circuit 53, and an output buffer 54. Are set to have a total delay amount corresponding to the signal delay time and the delay amount corresponding to the signal delay time in the off-chip driver circuit.

  Specifically, the delay monitor circuit 12 includes an input buffer 61 having a circuit configuration equivalent to the input buffer 11 in the synchronization circuit 51, an output buffer 62 having a circuit configuration equivalent to the output buffer 18 in the synchronization circuit 51, 6 is supplied with an OR circuit 63 having a circuit configuration equivalent to the OR circuit 53 in FIG. 6 and having one end grounded, an output buffer 64 having a circuit configuration equivalent to the output buffer 54 in FIG. 6, and an internal clock Tx. A mimic circuit 65 having a circuit configuration equivalent to an off-chip driver circuit (not shown) whose data output operation is controlled based on the internal clock Tx and an equivalent circuit pattern, and having a signal delay time substantially equal to that of the off-chip driver circuit. And are connected in cascade.

  The synchronization circuit 51 basically outputs an internal clock aTx1 synchronized with the external clock CK.

  However, in the middle of the clock propagation path in the delay monitor circuit 12, an OR circuit 63 having a circuit configuration equivalent to that of the OR circuit 53 in FIG. It has a circuit configuration equivalent to the output buffer 54, an output buffer 64 whose signal delay is substantially equal to the output buffer 54, a circuit configuration equivalent to an off-chip driver circuit, and an equivalent circuit pattern, Since the mimic circuit 65 having a signal delay time substantially equal to that of the chip driver circuit is inserted, the input to the SAD circuit SAD21 is delayed by the sum of the delay times of these circuits. As a result, the output buffer 18 The internal clock aTx1 output from the output clock 54 is equal to the signal delay time in the OR circuit 63 with respect to the external clock CK. Only the signal delay time in the definitive signal delay time and the off-chip driver circuit phase is early.

  FIG. 8 shows a detailed circuit configuration of the synchronization circuit 52 in FIG. The synchronization circuit 52 includes an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD22, and an output buffer 18, similarly to the synchronization circuit of FIG. In this synchronization circuit 52, the delay monitor circuit 12 corresponds to a delay amount corresponding to twice the signal delay time in one input buffer 11 and the output buffer 18 and twice the signal delay time in the OR circuit 53. The delay amount, the delay amount corresponding to twice the signal delay time in the output buffer 54, and the total delay amount corresponding to twice the signal delay time in the off-chip driver circuit are set. .

  Specifically, the delay monitor circuit 12 includes input buffers 71 and 72 having a circuit configuration equivalent to the input buffer 11 in the synchronization circuit 52, and an output buffer 73 having a circuit configuration equivalent to the output buffer 18 in the synchronization circuit 52, 74, OR circuits 75 and 76 having a circuit configuration equivalent to the OR circuit 53 in FIG. 6 and having one end grounded, and output buffers 77 and 78 having a circuit configuration equivalent to the output buffer 54 in FIG. A signal having an equivalent circuit configuration and equivalent circuit pattern to an off-chip driver (not shown) that is supplied with an internal clock Tx and whose data output operation is controlled based on the internal clock Tx, and is substantially equal to the off-chip driver circuit The counter circuits 79 and 80 having a delay time are connected in cascade.

  The number of unit delay elements of the backward pulse delay line 16 of the SAD circuit SAD22 is reduced to half of the number of unit delay elements.

  Accordingly, the synchronizing circuit 52 basically outputs an internal clock whose phase is shifted by 180 ° with respect to the external clock CK. However, in the middle of the clock propagation path in the delay monitor circuit 12, two OR circuits having a circuit configuration equivalent to the OR circuit 53 in FIG. 6 and a signal delay amount substantially equal to the OR circuit 53 are provided. Circuits 75 and 76 and a circuit configuration equivalent to the output buffer 54, two output buffers 77 and 78 having a signal delay amount substantially equal to the output buffer 54, and a circuit configuration equivalent to an off-chip driver circuit In addition, two imitation circuits 79 and 80 having an equivalent circuit pattern and substantially the same signal delay time as that of the off-chip driver circuit are inserted, so that only the sum of delay times of these circuits is inserted. The input to the SAD circuit SAD22 is delayed. As a result, the phase of the internal clock aTx2 output from the output buffer 18 is 180 ° with respect to the external clock CK. To shift clock signal delay time by a phase is early in the signal delay time and the off-chip driver circuit in the signal delay time and the output buffer 54 in the OR circuit 53.

  The internal clock aTx1 output from the synchronization circuit 51 and the internal clock aTx2 output from the synchronization circuit 52 pass through the OR circuit 53, so that the internal clock that has been advanced in advance by the signal delay time in the OR circuit 53 is obtained. The phase of aTx1 and aTx2 is delayed by that amount and becomes a clock aTx having a frequency twice as high as that of CK. Further, this clock aTx passes through the output buffer 54, so that only the signal delay time in the output buffer 54 is obtained in advance. The phase of the advanced internal clock aTx is delayed by that amount and becomes the clock Tx. Therefore, the obtained internal clock Tx has a frequency twice that of the external clock CK, and the phase is advanced by the signal delay time in the off-chip driver circuit with respect to the external clock CK.

  That is, if the output operation in the off-chip driver circuit is controlled using the clock Tx, the data output timing from the off-chip driver circuit is synchronized with the external clock CK, and the data output operation with respect to the external clock CK is performed. There can be no delay.

  In this embodiment, the internal clock Tu synchronized with the external clock CK and the internal clock Td whose phase is shifted by 180 ° with respect to the external clock CK are not output. However, if both the internal clocks Tu and Td are required, The synchronization circuits 31 and 32 shown in FIGS. 2 and 3 may be provided.

  Further, if the internal clocks Tu and Td are not required, the synchronization circuits 31 and 32 are unnecessary, and it is sufficient to provide two SAD circuits as a whole, so that the chip area and power consumption can be greatly reduced.

  FIG. 9 is a timing chart showing an example of the operation when the synchronizing circuits 31 and 32 for outputting the internal clocks Tu and Td are provided in the circuit of the second embodiment. Here, for example, the SAD circuit SAD11 in the synchronization circuit 31 in FIG. 2 includes a synchronization error of Δτ1, the SAD circuit SAD12 in the synchronization circuit 32 in FIG. 3 includes a synchronization error of Δτ2, and the synchronization circuit 51 in FIG. Assume that the SAD circuit SAD21 includes a synchronization error of δ3, and the SAD circuit SAD22 in the synchronization circuit 52 in FIG.

  In this case, as shown in FIG. 9, the internal clock aTx1 has a synchronization error of δ3 with respect to an ideal internal clock having no synchronization error indicated by a broken line. Similarly, for the internal clock aTx2, a synchronization error of δ4 occurs with respect to an ideal internal clock indicated by a broken line with no synchronization error. Then, since the internal clocks aTx1 and aTx2 are ORed by the OR circuit 53 and do not pass through the SAD circuit, the synchronization error included in the clock Tx is originally included in the clocks aTx1 and aTx2. Δ3 or δ4.

  Here, for example, if the synchronization error in each SAD circuit is Δτ as in the conventional case, the synchronization error included in the internal clock Tx is at most Δτ, and the synchronization error is further reduced as compared with the circuit of the first embodiment. Can do.

  By the way, in the first and second embodiments, as shown in the timing charts of FIGS. 5 and 9, when the duty of the external clock CK is low, that is, for a period in which CK is at “L” level. However, when the duty of the external clock CK becomes high, for example, the OR circuit 35 of the first embodiment shown in FIG. In addition, when the OR logic of aTx2 is taken, the “H” level periods of both internal clocks may overlap each other.

  In such a case, a pulsing circuit may be provided on the input side of the OR circuit 35 so that the OR circuit 35 takes OR logic after shortening the “H” level period of the internal clocks aTx1 and aTx2. . However, when this pulsing circuit is provided, it is necessary to provide a circuit having a signal delay amount equivalent to that of the pulsing circuit in the delay monitoring circuit of the synchronization circuits 33 and 34 in order to match the signal delay time.

  Next, an off-chip driver circuit that performs data output control using the internal clock Tx output from the circuit of each of the above embodiments and a signal delay equivalent to the off-chip driver circuit used in the circuit of each of the embodiments An imitation circuit having a quantity will be described.

  FIG. 10 is a block diagram showing a schematic configuration of an off-chip driver circuit. The off-chip driver circuit 91 uses, for example, the output control signal OCDOUT to synchronize the voltage signal VDout corresponding to the output data “1” or “0” with the external clock with respect to the data Dout generated in the previous stage. The signal is output to the output pad at the timing when it becomes H ”level. In addition, during the period when the output control signal OCDOUT is at the “L” level, the voltage signal VDout corresponding to the output data is not output to the output pad, and the output pad is disconnected from the power supply and is in a high impedance state.

  Here, the output control signal OCDOUT is a signal based on the internal clock Tx shown in FIG. 1 or FIG.

  In particular, in an I / O unit that requires high-speed operation, a system is adopted in which 2 bits of internal data are converted into 1 bit of external data by parallel-serial conversion. FIG. 11 is a block diagram showing a schematic configuration of this parallel-serial off-chip driver circuit.

  One data Dout1 generated in the preceding stage is input to the off-chip driver circuit 92, and the other data Dout2 is input to the off-chip driver circuit 93. The data output operation in both the off-chip driver circuits 92 and 93 is performed by the Dout selection circuit 94 to which the output control signal OCDOUT is input. The outputs of both the off-chip driver circuits 92 and 93 are connected in common.

  In addition to the output control signal OCDOUT, the Dout selection circuit 94 receives internal clocks Tu ′ and Td ′ based on the internal clocks Tu and Td shown in FIG. 1 or FIG. One Dout1 selection signal is output in synchronization with the internal clock Tu ′, and the other Dout2 selection signal is output in synchronization with the internal clock Td ′.

  Next, an example of the operation of the off-chip driver circuit configured as shown in FIG. 11 will be described with reference to the timing chart shown in FIG. Now, for example, it is assumed that “H” data is input to one off-chip driver circuit 92 as data Dout1, and “L” data is input to the other off-chip driver circuit 93 as data Dout2. First, after the output control signal OCDOUT rises to the “H” level, the Dout selection circuit 94 outputs the Dout1 selection signal, and one off-chip driver circuit 92 is selected, and the voltage signal VDout corresponding to the data Dout1. Is output to the output pad. Therefore, the voltage signal VDout rises to “H” level.

  When the output control signal OCDOUT falls to “H” level again after falling to “L” level, the Dout 2 selection signal is output from the Dout selection circuit 94 this time. Accordingly, this time, the other off-chip driver circuit 93 is selected, and the voltage signal VDout falls to the “L” level. Since there is a load on the output pad, the voltage signal VDout that has fallen to the “L” level is charged through this load, and finally returns to the original state.

  As described above, the selection signals of the two off-chip driver circuits are sequentially activated according to the output control signal OCDOUT, and 2-bit data is sequentially output to the output pad.

  In the circuit of FIG. 11, there is a predetermined delay time DOCD (for example, 1 nS) from when the output control signal OCDOUT becomes “H” level until the signal is actually output to the output pad. The output control signal OCDOUT needs to precede the external clock by DOCD in order to compensate for the delay time in the off-chip driver circuit.

  In the first and second embodiments, the internal clock Tx is converted to the external clock CK by using a synchronous circuit (for example, the synchronous circuits 31, 32, 33, and 34 shown in FIGS. 2, 3, 4, and 4). Is preceded by the delay time in the off-chip driver circuit. Each of the synchronous circuits has a circuit configuration equivalent to the off-chip driver circuit and an equivalent circuit pattern in order to accurately reproduce the delay time for DOCD, and a signal delay amount equivalent to the off-chip driver circuit. The imitation circuit which has is used. In other words, when the characteristics of the off-chip driver circuit change due to the influence of manufacturing process variations and the like, the characteristics of the mimic circuit change in the same way. Therefore, the off-chip driver circuit and the mimic circuit have equivalent circuit configurations and are equivalent. It is desirable to have a simple circuit pattern.

  However, when the circuit of FIG. 11 is used as it is as a mimic circuit, OCDOUT is used as an input of the mimic circuit, and VDout is used as an output of the mimic circuit, the following problems arise. For example, in the circuit of FIG. 11, consider a case where Dout1 is fixed to “H”, Dout2 is fixed to “L”, and the Dout1 selection signal is activated. When the Dout1 selection signal is activated and becomes “H” level, the off-chip driver circuit 92 is selected and the voltage signal VDout becomes “H” level. However, when OCDOUT next goes to “L” level and VDout goes to a high impedance state, VDout remains at the original “H” level and does not drop to “L” level, so a signal is transmitted to the next stage. I can't go. Therefore, the circuit of FIG. 11 cannot be used as an imitation circuit as it is.

  Therefore, a circuit having a configuration as shown in FIG. 13 is used as an imitation circuit corresponding to a 2-bit parallel-serial off-chip driver. The imitation circuit shown in FIG. 13 is provided with two off-chip driver circuits 92 and 93 and a Dout selection circuit 94 as in the case shown in FIG. However, the difference from the circuit of FIG. 11 is that, instead of using the Dout2 selection signal, the Dout1 selection signal is inverted using an inverter 95 and used for the selection operation of the off-chip driver circuit 93.

  According to the imitation circuit having such a configuration, as shown in the timing chart of FIG. 14, the Dout1 selection signal is activated after the output control signal OCDOUT rises to the “H” level, and the off-chip driver circuit 92 is selected. Thus, the voltage signal VDout becomes “H” level. Next, when the output control signal OCDOUT falls to the “L” level, the Dout1 selection signal is deactivated and the selected state of the off-chip driver 92 is released. Further, when the Dout1 selection signal is deactivated, the output of the inverter 95 becomes “H” level, and the off-chip driver circuit 93 is selected this time, and the voltage signal VDout falls to “L” level. That is, when such a circuit is used, when a clock is input as the output control signal OCDOUT, the voltage signal VDout as a clock delayed by the previous delay time DOCD rises, and the output control signal OCDOUT to the voltage signal VDout is increased. The delay time is the same as that of an actual off-chip driver circuit.

  The signal for selecting the off-chip driver circuit 93 is delayed by the signal delay time in the inverter 95. This is a signal for determining the falling edge of the voltage signal VDout. Even if this is delayed, the voltage signal It does not affect the rise of VDout.

  In an actual off-chip driver circuit, a pad having a predetermined pattern is formed at a node from which the voltage signal VDout is output. This pad acts as a load for the voltage signal VDout. Therefore, in order to accurately match the signal delay time in the mimic circuit with the actual off-chip driver circuit, a dummy pad 96 having the same pattern as the actual pad is provided for the node of the voltage signal VDout of the mimic circuit. What should I do?

  By the way, in the off-chip driver circuit, it is preferable that the delay time when outputting “H” level data is the same as that when outputting “L” level data. However, in an actual off-chip driver, both delay times are different. There may be.

  FIG. 15 shows a timing chart when the delay time at the time of “H” level data output is early in the 2-bit parallel-serial off-chip driver circuit shown in FIG. In this case, the input data Dout1 of one off-chip driver circuit 92 is fixed at “H” level, and the input data Dout2 of the other off-chip driver circuit 93 is fixed at “L” level. As shown, the delay time DOCDH when the off-chip driver circuit 92 is selected and the voltage signal VDout rises to the “H” level is short.

  On the other hand, FIG. 16 shows a timing chart when the delay time when outputting the “L” level data is slow. In this case, the input data Dout1 of one off-chip driver 92 is fixed at “L” level, and the input data Dout2 of the other off-chip driver circuit 93 is fixed at “H” level. As shown in the figure, the delay time DOCDL when the off-chip driver circuit 92 is selected and the voltage signal VDout falls to the “L” level is long.

  The cause of the difference in both delay times is the difference in circuit system, that is, the channel width of the P channel MOS transistor that outputs the “H” level among the P and N channel MOS transistors constituting the off-chip driver circuit. This is because the channel width of the N-channel MOS transistor that outputs the “L” level is sufficiently larger or due to variations in the manufacturing process.

  In this case, as shown in FIG. 11, in the imitation circuit in which the input data Dout1 is fixed to the “H” level and the input data Dout2 is fixed to the “L” level, the input clock rises to the “H” level and the output clock is “ The delay time when rising to the H "level can be accurately reproduced. However, the delay time when the output data of the off-chip driver circuit falls to the “L” level cannot be accurately reproduced, and the error becomes large.

  Therefore, both the signal delay time in the off-chip driver circuit when the output data of the off-chip driver circuit changes to the “H” level and “L” level can be compensated for and output in synchronization with the external clock. A third embodiment of the invention will be described below.

  FIG. 17 is a block diagram of an off-chip driver control signal generation circuit according to the third embodiment. In the figure, reference numeral 101 denotes, for example, a circuit similar to the off-chip driver control signal generation circuit according to the first embodiment shown in FIG. 1 or the off-chip driver control signal generation circuit according to the second embodiment shown in FIG. 4 and the imitation circuit 45 in FIG. 4 or the imitation circuit 65 in FIG. 7 and the imitation circuit (79, 80) in FIG. 8 as the imitation circuit, and the signal delay time. Is an output control signal generation circuit having a mimic circuit 102 equivalent to a signal delay time when outputting "H" level data in an off-chip driver circuit.

  Reference numeral 103 denotes, for example, a circuit configuration similar to the off-chip driver control signal generation circuit according to the first embodiment shown in FIG. 1 or the off-chip driver control signal generation circuit according to the second embodiment shown in FIG. 4 and the circuit structure similar to that of the mimic circuit 45 in FIG. 4 or the mimic circuit 65 in FIG. 7 and the mimic circuits 79 and 80 in FIG. 8, and the signal delay time is off. This is an output control signal generation circuit having an imitation circuit 104 equivalent to a signal delay time when “L” level data is output in the chip driver circuit.

  The output control signal OCDOUTH output from the one output control signal generation circuit 101 and the output control signal OCDOUTL output from the other output control signal generation circuit 103 are input to the off-chip driver circuit 105.

  FIG. 18 is a block diagram showing a configuration of the off-chip driver circuit 105. In this circuit, the output control signal OCDOUTH is input as corresponding to the Dout selection circuit 94 in FIG. 11, and a Dout selection circuit 94a that outputs a Dout1 selection signal and a Dout2 selection signal in response to this signal, The output control signal OCDOUTL is input, and a Dout selection circuit 94b that outputs a Dout1 selection signal and a Dout2 selection signal in response to this signal is provided.

  The two systems of selection signals output from both the Dout selection circuits 94a and 94b are input to a selection circuit 97 provided for each of the off-chip driver circuits (only 92 is shown). The selection circuit 97 detects the level of the data Dout1 for the off-chip driver circuit 92, selects one of the selection signals of the Dout selection circuits 94a and 94b in accordance with the detected level, and selects the corresponding off-state. The data is output to the chip driver circuit 92.

  When the off-chip driver circuit 92 outputs “H” level data Dout1, the selection signal from the Dout selection circuit 94a is selected by the selection circuit 97 and input to the off-chip driver circuit 92. On the other hand, when the off-chip driver circuit 92 outputs the “L” level data Dout1, the selection signal from the Dout selection circuit 94b is selected by the selection circuit 97 and input to the off-chip driver circuit 92.

  Therefore, in this embodiment, the off-chip driver circuits having different delay times from the data selection signal to the data output at the time of “H” level data selection and “L” level data selection are also preceded by the respective delay times. Since the selection operation is controlled using the output selection signal, data can be output in synchronization with the external clock at any time.

  Needless to say, the present invention is not limited to the above embodiments, and various modifications are possible. For example, in each embodiment, the case where the internal clock Tx synchronized with the external clock CK is output has been described, but this is an internal clock output from another synchronization circuit provided in the chip instead of the external clock CK. The internal clock Tx may be output from the clock, or the internal clock Tx may be output from an asynchronous clock that is not output from another synchronous circuit in the chip.

  In the third embodiment shown in FIG. 17, the off-chip driver according to the first embodiment shown in FIG. 1, for example, is used as each of the output control signal generation circuits 103 and 104 for generating one and the other output control signals. In the above description, the control signal generation circuit or the circuit having the same circuit configuration as that of the off-chip driver control signal generation circuit according to the second embodiment shown in FIG. 6 is used. Any driver can be used as long as it can generate an internal clock capable of compensating for signal delay time when outputting "H" level and "L" level data in the driver circuit.

1 is a block circuit diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to a first embodiment of the present invention. The figure which shows the detailed circuit structure of the synchronous circuit 31 in FIG. The figure which shows the detailed circuit structure of the synchronous circuit 32 in FIG. FIG. 3 is a diagram showing a detailed circuit configuration of synchronization circuits 33 and 34 in FIG. 1. 3 is a timing chart illustrating an example of an operation in the circuit of the first embodiment. FIG. 6 is a block circuit diagram of an off-chip driver control signal generation circuit provided in a semiconductor integrated circuit according to a second embodiment of the present invention. The figure which shows the detailed circuit structure of the synchronous circuit 51 in FIG. The figure which shows the detailed circuit structure of the synchronous circuit 52 in FIG. 9 is a timing chart showing an example of an operation in the circuit of the second embodiment. The block diagram which shows the schematic structure of an off-chip driver. FIG. 2 is a block diagram showing a schematic configuration of a parallel-serial off-chip driver circuit. 12 is a timing chart showing an example of the operation of the off-chip driver circuit of FIG. The circuit diagram of the imitation circuit of the off-chip driver circuit of 2 bits parallel-serial system used by this invention. 14 is a timing chart showing an operation example of the imitation circuit of FIG. 12 is a timing chart showing an operation example when the delay time at the time of “H” level data output is early in the off-chip driver circuit shown in FIG. 12 is a timing chart showing an operation example when the delay time at the time of “L” level data output is early in the off-chip driver circuit shown in FIG. The block diagram of the control signal generation circuit for off-chip drivers provided in the semiconductor integrated circuit by the 3rd Embodiment of this invention. The block diagram which shows the structure of the off-chip driver circuit 105 by the said 3rd Embodiment. The block diagram of the synchronous circuit of a SAD system. FIG. 20 is a timing chart illustrating an example of the operation of the synchronization circuit illustrated in FIG. 19. FIG. The block circuit diagram of the conventional control signal generation circuit for off-chip drivers comprised using the synchronous circuit of a SAD system. FIG. 22 is a circuit diagram of the synchronization circuit 21 in FIG. 21. FIG. 22 is a circuit diagram of the synchronization circuit 22 in FIG. 21. FIG. 22 is a circuit diagram of the synchronization circuit 24 in FIG. 21. The timing chart which shows the operation example of the conventional circuit of FIG.

Explanation of symbols

11, 37, 38, 41, 61, 71, 72 ... input buffer, 12 ... delay monitor circuit, 14 ... forward pulse delay line, 16 ... backward pulse delay line, 18, 36, 39, 40, 42, 44 54, 62, 64, 73, 74, 77, 78 ... output buffer 31, 32, 33, 34, 51, 52 ... synchronous circuit, 35, 43, 53, 63 ... OR circuit, 45, 65, 79, 80, 102, 104 ... imitation circuit, 91, 92, 93, 105 ... off-chip driver circuit, 94, 94a, 94b ... Dout selection circuit, 95 ... inverter, 96 ... dummy pad, 97 ... selection circuit, 101, 103 ... Output control signal generation circuit, SAD11, SAD12, SAD13, SAD21, SAD22... SAD circuit.

Claims (5)

An off-chip driver circuit that outputs data based on an output control signal, and has different signal delay times from the output control signal to data output at the time of “H” level data output and “L” level data output;
A first output control signal generating circuit for generating a first output control signal used when outputting "H" level data in the off-chip driver circuit;
And a second output control signal generating circuit for generating a second output control signal for use in outputting "L" level data in the off-chip driver circuit. The first output control signal generation circuit includes:
A signal delay time from the first output control signal to the data output when the first clock is input, and at least “H” level data is output from the off-chip driver circuit in synchronization with the first clock. A first synchronization circuit that outputs a second clock whose phase is advanced by
A third clock is input, and is synchronized with the third clock, and at least the signal delay time from the first output control signal to the data output when “H” level data is output from the off-chip driver circuit. A second synchronization circuit that outputs a fourth clock that is advanced in phase by a phase and different in frequency from the second clock;
A first clock that outputs a fifth clock for controlling a data output operation when the second clock and the fourth clock are input and "H" level data is output from the off-chip driver circuit. An OR circuit of
The second output control signal generation circuit includes:
A sixth clock is input, and is synchronized with the sixth clock and at least a signal delay time from the second output control signal to the data output when “L” level data is output from the off-chip driver circuit. A third synchronization circuit for outputting a seventh clock whose phase is advanced by a period;
A signal delay time from the second output control signal to the data output when the eighth clock is input, and at least “L” level data is output from the off-chip driver circuit in synchronization with the eighth clock. A fourth synchronization circuit that outputs a ninth clock having a phase that is advanced by a phase and a frequency different from that of the seventh clock;
The second clock that outputs the tenth clock for controlling the data output operation when the seventh clock and the ninth clock are input and the “L” level data is output from the off-chip driver circuit. The semiconductor integrated circuit according to claim 1, further comprising: an OR circuit.   The first and second synchronization circuits respectively advance the second and fourth clocks so as to advance the phase by the signal delay time in the first OR circuit in addition to the signal delay time in the off-chip driver circuit. Are respectively output, and the third and fourth synchronization circuits each have a phase corresponding to the signal delay time in the second OR circuit in addition to the signal delay time in the off-chip driver circuit. The semiconductor integrated circuit according to claim 2, wherein the seventh and ninth clocks are respectively output so as to speed up the processing. Each of the first to fourth synchronization circuits includes:
A delay monitor circuit to which a clock is input;
An output from the delay monitor circuit after the clock and the output pulse from the delay monitor circuit are input and the clock in the first cycle is input, having a forward pulse delay line and a backward pulse delay line The pulse is delayed by a forward pulse delay line for a predetermined time, and after the arrival of the clock of the second cycle, which is the next cycle of the first cycle, the clock of the next second cycle is delayed by the forward pulse delay line. And a synchronous adjustment delay circuit that outputs a delay corresponding to a delay time of the output pulse from the delay monitor circuit or a half of the time corresponding to the delay time of the backward pulse delay line. The semiconductor integrated circuit according to claim 2.   3. The semiconductor integrated circuit according to claim 2, wherein a mimic circuit having a circuit configuration substantially the same as that of the off-chip driver circuit is inserted in the middle of the clock propagation path in the delay monitor circuit.

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