JP2000134082A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device provided with an output circuit that can stably generate a low amplitude signal. SOLUTION: A current adjustment MOSFET is added to each of a plurality of output circuits of a low voltage differential signal LVDS configuration, one of them is used for a dummy output circuit, a termination resistor connects to an output terminal to generate a high level and a low level, they are respectively compared with a high level and a low level of a reference output, a control signal of the current adjustment MOSFET is generated to obtain a desired output level and the control signal is fed to the current adjustment MOSFET of a plurality of the other output circuits respectively to adjust the current automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to an LVDS (Low Voltage Differential).
The present invention relates to a technology that is effective when used with an output circuit having a signal (signal) configuration.

[0002]

2. Description of the Related Art In a digital control system composed of semiconductor integrated circuit devices, there is an LVDS as a high-speed signal transmission method between the semiconductor integrated circuit devices. This LVDS
Then, the signal transmission path is terminated with 100Ω by a twisted pair wire to transmit a positive phase signal and a negative phase signal. Since a current of about 4 mA flows through the transmission line, a signal amplitude as low as about 400 mV is applied to the terminating resistor. A MOSFET (insulated gate field effect transistor) formed in a semiconductor integrated circuit device has a relatively large process variation. Therefore, in order to stably form a low-amplitude signal as described above, the output circuit has a current adjusting function. Is required.

[0003]

The inventor of the present application has considered adding an automatic output level adjusting circuit to a semiconductor integrated circuit device in order to stably form a low-amplitude signal as described above.

An object of the present invention is to provide a semiconductor integrated circuit device having an output circuit capable of stably forming a low-amplitude signal. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a current adjusting MOSFET is added to each of the plurality of output circuits of the LVDS configuration, one of which is used as one dummy output circuit, and a terminating resistor is connected to the output terminal to form a high level and a low level. The current adjusting M is compared with the output high level and the low level level so that the desired output level is obtained.
A control signal for the OSFET is formed, and the control signal is supplied to each of the current adjusting MOSFETs of the other plurality of output circuits to perform automatic current adjustment.

[0006]

FIG. 1 is a circuit diagram showing one embodiment of an output circuit of a semiconductor integrated circuit device and a current adjusting circuit thereof according to the present invention. Each circuit in FIG.
It is formed on one semiconductor substrate such as single crystal silicon by a manufacturing technique of an OS (complementary MSO) integrated circuit.
FIG. 1 exemplarily shows a portion related to the output circuit and the current adjustment circuit in the semiconductor integrated circuit device LSI indicated by a dotted line as a representative. Therefore, other circuits such as an input circuit required as the semiconductor integrated circuit device LSI are omitted.

The dummy output circuit used for the current adjustment circuit includes a first CMOS inverter circuit composed of a P-channel MOSFET MP10 and an N-channel MOSFET MN10, and a second CMOS inverter circuit composed of a P-channel MOSFET MP20 and an N-channel MOSFET MN20.
It comprises a MOS inverter circuit and a current source circuit for generating operating currents of these two CMOS inverter circuits. The current source circuit operates as a constant current source by constantly receiving the ground potential of the circuit at its gate.
The channel type MOSFET MP00 and the N-channel type MOSFET MN00 operating as a constant current source by being constantly supplied with the power supply voltage VDD to its gate.
And P-channel MOSFETs MPS1 and MPS2 for current adjustment connected to these in parallel, respectively.
It comprises an N-channel MOSFET MNS1PMNS2. These MOSFETs MS1 and MS2 and M
N1 and MN2 are not particularly limited, but are formed such that the element sizes are 1: 2 so as to have binary weights.

The outputs of the above CMOS inverter circuits are respectively guided to external terminals.
Are provided. In the two CMOS inverter circuits, an input signal supplied to the gate of one of the CMOS inverter circuits (MP10 and MN10) is supplied to the other CMOS inverter circuit (MP20) through the inverter circuit N0 so as to form complementary output signals. And MN
20) is supplied to the gate. In this embodiment, a high level corresponding to the power supply voltage VDD is fixedly supplied to the input terminal. Therefore, the N-channel MOSFET MN10 of one CMOS inverter circuit is turned on, a low level VOL is output to the output terminal to which the drain is connected, and the P-channel MOSFET of the other CMOS inverter circuit is output.
The channel type MOSFET MP20 is turned on,
The output terminal to which the drain is connected has a high level VO
H is output.

The high-level output VOH is a sense circuit SA1 using a voltage V1 corresponding to a high level as a reference voltage.
, Where a voltage comparison with the voltage V1 is performed. The low-level output VOL is supplied to an input of a sense circuit SA2 using a voltage V2 corresponding to the low level as a reference voltage, and a voltage comparison with the voltage V2 is performed. In the LVDS output circuit, the voltage V1 is set to 1.35V, and the voltage V2 is set to 1.05V.

For example, in consideration of the process variation of the MOSFET, the high-level output VOH <1.35 V
And the low-level output VOL
> 1.05V. Correspondingly, the counter circuit COUNT1 sets the initial value to the maximum value of all 1s.
, The outputs SP1 and SP2 are both set to the high level, and the P-channel MOSFETs MS1 and MS2 are both off. In the counter circuit COUNT2, the initial value is set to the minimum value of all 0s, the outputs SN1 and SN2 are both set to low level, and the N-channel MOSFET MN
1 and MN2 are both off.

The control circuit COUNT sets the counter circuits COUNT1 and COUNT2 to the initial state as described above, and performs a current adjusting operation. For example, in the first operation, the counter circuit COUN corresponds to the output of the sense circuit SA1.
T1 is caused to perform a down-counting operation. As a result, the count value decreases from 11 to 10, and the MOSFET MS1 is turned on by the low level of the output signal SP1.
As a result, the adjustment current of 1 flows from the MOSFET MS1, and the output level VOH increases.
If the output level VOH <V1 at this time, the output of the sense circuit SA1 causes the counter circuit COUNT1 to perform a down counting operation of −1, the count value changes to 01, the MOSFET MS1 is turned off, and the MS2 is turned on. Then, the output level VOH is increased by increasing the current as in the case of the second adjustment current.

If the output level VOH <V
If 1, the output of the sense circuit SA1 causes the counter circuit C
OUNT1 performs a down counting operation of −1, and the counted value is 0.
0, and the MOSFETs MS1 and MS2 are turned on, increasing like the adjustment current of 3 and increasing the output level VOH. In this embodiment, two adjustment MOSFETs are used. In practice, however, 16 adjustment currents are formed using, for example, four MOSFETs having binary weights, and when VOH> V1 Stops the operation of the counter circuit CONT1.

In the second operation, the control circuit CONT responds to the output of the sense circuit SA2 by using the counter circuit COUN.
T2 is caused to perform an up-counting operation. As a result, the count value decreases from 00 to 01, and the MOSFET MN1 is turned on by the high level of the output signal SN1.
As a result, the adjustment current of 1 flows from the MOSFET MN1, so that the output level VOL decreases.
If the output level VOL> V2 at this time, the counter circuit COUNT2 performs an up-counting operation of +1 by the output of the sense circuit SA2, the count value changes as 10, the MOSFET MN1 is turned off, and the MN2 is turned on. Then, the output level VOL is decreased by increasing the adjustment current like the second adjustment current.

If the output level VOL> V
2, the counter circuit C is output from the sense circuit SA2.
OUNT2 performs a +1 up counting operation, and the counted value is 1
1, the MOSFETs MN1 and MN2 are turned on, and the MOSFETs MN1 and MN2 are increased like the adjustment current of No. 3 to lower the output level VOL. In this embodiment, two adjusting MOSFETs are used. However, in practice, 16 kinds of adjusting currents are formed by using, for example, four MOSFETs having binary weights, and when VOL> V2 is satisfied. Stops the operation of the counter circuit CONT2.

The output levels VOH and VOL of the output terminals
Are coupled by a terminating resistor, and the level adjustment operation of the low-level output VOL lowers VOH by being affected. Therefore, the first operation is performed by the third operation.
The same operation as described above is repeated. That is, the counter circuit CONT1 holds the first count value. If the high-level output VOH <V1 at that time, VO
The down counting operation is performed until H> V1.

Hereinafter, if necessary, the low-level output VOL is again output.
As for, the continuation of the second operation may be performed. Alternatively, in the first operation, the low-level output VOL may be adjusted, and in the second operation, the high-level output VOH may be adjusted in the reverse order.

The count value formed by the counter circuits COUNT1 and COUNT2 as described above is held by stopping the operation of the respective counter circuits COUNT1 and COUNT2. Such a count output is output from an output circuit DOB1 to DOBN having the same configuration as the output circuit.
Corresponding adjustment signals SP1, SP2 and SN1, SN2
Used as These output circuits DOB1 to DOB
N is formed of, for example, an internal logic circuit LOG composed of a CMOS gate array or the like, receives signals DO1 to DON to be output to other semiconductor integrated circuit devices, and receives corresponding output terminals D1T, D1B to DNT. , DNB. These output terminals D1T, D1B to DNT,
The terminating resistor corresponding to the DNB is connected between a pair of input terminals of a receiving-side semiconductor integrated circuit device (not shown).

The above operation may be performed each time the semiconductor integrated circuit device starts signal output, in addition to being performed when the power is turned on. Alternatively, a temperature sensor may be provided so that the adjustment operation is performed when the temperature exceeds a certain temperature.
In this case, the counter circuits COUNT1 and COUNT2
Is used to perform an up / down (U / D) operation. The operation of the counter circuit COUNT1 will be described. When VOH> V1 at the start of the readjustment operation, the up-count operation of +1 is performed in reverse to the above. Done. This up counting operation is performed until VOH <V1. When VOH <V1 at the start of the readjustment operation, the down counting operation of −1 is performed until VOH> V1 as described above. That is, assuming that the adjustment voltage corresponding to the minimum adjustment current of the current adjustment MOSFET is ΔV with respect to the reference voltage V1, the output level VOH of the output signal VOH falls within the range of V1 ± ΔV.

In the same manner as described above, in the operation of the counter circuit COUNT2, when VOL <V2 at the start of the readjustment operation, a down counting operation of -1 is performed contrary to the above. This down counting operation is performed until VOL> V2. Also,
If VOL> V2 at the start of the readjustment operation, the +1 up counting operation is performed until VOL <V2 in the same manner as described above. That is, assuming that the adjustment voltage corresponding to the minimum adjustment current of the current adjustment MOSFET is ΔV around the reference voltage V2, the output level VOL is also V2 ±
It is made to fall within the range of ΔV.

FIG. 2 is a circuit diagram showing another embodiment of the output circuit of the semiconductor integrated circuit device according to the present invention and its current adjusting circuit. In the embodiment of FIG. 1, since the output high level VOH and the output low level VLO are adjusted alternately, there arises a problem that control becomes complicated and time is required. In this example,
It is devised that the output high levels VOH and VOL are adjusted simultaneously by one operation.

In this embodiment, a terminating resistor provided between a pair of output terminals is divided into 50 ohms, and a center voltage of a signal level, for example, 1.2 V is supplied to a middle point thereof. As a result, the control circuit COUNT sets the counter circuits COUNT1 and COUNT2 to the initial state as described above, and in the first operation, causes the counter circuit COUNT1 to perform a down-counting operation in response to the output of the sense circuit SA1. The counter circuit C corresponding to the output of the sense circuit SA2
OUNT1 is caused to perform an up-counting operation.

As a result, in the counter circuit COUNT1, the count value decreases from 11 to 10 in the same manner as described above.
Since MS1 is turned on and the adjustment current of 1 flows from the MOSFET MS1, the output level VOH
Increase. If the output level at this time is VOH <V
If 1, the output of the sense circuit SA1 causes the counter circuit C
OUNT1 performs a down counting operation of −1, and the counted value is 0.
It changes sequentially like 1, 00, and when VOH> V1, the operation of the counter circuit CONT1 stops.

In the control of the counter circuit COUNT2 in the first operation, the control circuit CONT increases the count value from 00 to 01 in the same manner as described above, and outputs the output signal SN1.
Since the MOSFET MN1 is turned on by the high level of (1) and the adjustment current of 1 flows from the MOSFET MN1, the output level VOL decreases. If the output level VOL> V2 at this time, the sense circuit SA
The counter circuit COUNT2 performs an up-counting operation of +1 by the output of 2 and the count value sequentially changes as 10 and 11, and when the VOL <V2, the counter circuit COUNT2
The operation of NT2 stops. Since the two output levels VOH and VOL are adjusted at the same time, the levels can be set with high accuracy in a single time and without being affected by the level adjustment.

FIG. 3 is a block diagram showing an example of a signal transmission method using the semiconductor integrated circuit device according to the present invention. In FIG. 1A, a semiconductor integrated circuit device LS
I1 is the output side, and the output circuit as described above is provided. A pair of output signals of the output circuit are transmitted to an input circuit including a differential circuit of the semiconductor integrated circuit device LSI2 via a twisted pair line. On the receiving circuit side, a terminating resistor of 100Ω is provided between the pair of input terminals, and a current of about 4 mA flows from the output circuit of the semiconductor integrated circuit device LSI1. Thereby, about 40 at both ends of the terminating resistor.
An input signal such as 0 mV is transmitted, received by an input circuit including a differential circuit of the semiconductor integrated circuit device LSI2, and taken into an internal circuit.

FIG. 3B shows a voltage waveform diagram generated in the signal transmission line. In the output circuit as described above, the N-channel MOSFET of the output circuit
And the output low level is about 1.0V
And a signal voltage of 0.4 V (400 mV) is generated, so that the output high level is about 1.4 V. Therefore, the midpoint voltage of the high level and the low level is about 1.2 V. Therefore, as in the embodiment of FIG. By supplying such a midpoint voltage, it is possible to obtain high-level outputs VOH and VOL corresponding to signal halves each based on the midpoint voltage. By using such a divided termination resistor and the midpoint voltage to form a current adjusting circuit as in the embodiment of FIG. 2, the level adjustment can be performed in a single time and with each other as described in the embodiment of FIG. The level setting can be performed with high accuracy because the level setting is not affected.

The functions and effects obtained from the above embodiment are as follows. (1) A current adjusting MOSFET is added to each of a plurality of LVDS-configured output circuits, and one of them is used as one dummy output circuit to connect a terminating resistor to an output terminal to form a high level and a low level. The control signal of the current adjusting MOSFET is formed so as to be a desired output level by comparing the output high level and the low level level of the output signal, and the control signal is applied to the current adjusting MOSFETs of a plurality of other output circuits. By supplying and performing automatic current adjustment, a low-amplitude signal can be formed stably, and an effect that an extremely easy-to-use semiconductor integrated circuit device can be obtained is obtained.

(2) The current adjusting MOSFET is
By forming a current having a binary weight, using a binary counter circuit as the control circuit, and controlling the counting operation by the output of the comparison circuit, a simple configuration is achieved. The effect that current adjustment becomes possible is obtained.

(3) In the above control circuit, in the first operation, the first comparator circuit and the first counter circuit adjust the level of the high level or the second comparator circuit and the second counter circuit adjust the high level.
Adjust the low level by the counter circuit of
In the second operation, the low level adjustment is performed by the second comparison circuit and the second counter circuit or the high level adjustment is performed by the first comparison circuit and the first counter circuit. The current control is performed by repeating a simple control operation of performing high-level level adjustment by the first comparison circuit and the first counter circuit or low-level level adjustment by the second comparison circuit and the second counter circuit. Is obtained.

(4) By supplying the midpoint potential of the high level and the low level to be output to the midpoint of the terminating resistor, the current adjustment operation can be easily performed without being affected by the level adjustment. The effect that it can be done is obtained.

(5) Using the terminating resistor supplied with the midpoint potential as described above, the first comparator circuit and the first counter circuit adjust the level of the high level, and the second comparator circuit and the second comparator By performing the low-level adjustment simultaneously with the counter circuit described above, it is possible to obtain an effect that the current adjustment can be performed with high accuracy in a short time.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the resistance value of the terminating resistor only needs to correspond to the characteristic impedance of the transmission line. Further, the output current may be changed according to the performance of the circuit on the receiving side. That is, if the signal to be transmitted is a low voltage or low amplitude complementary signal and the receiving circuit receives the voltage generated at the terminating resistor as described above, the signal level can be variously selected. is there. As the current adjusting MOSFET, a plurality of MOSFETs having a binary weight as described above and a plurality of MOSFETs which allow the same current to flow are provided, and the number of operating MOSFETs is determined by the decode output of the counter circuit. Is also good. As described above, the current formed by the current adjusting MOSFET and the control signal thereof can be configured by various combinations. INDUSTRIAL APPLICABILITY The present invention can be widely used for various semiconductor integrated circuit devices having an output circuit that forms a low voltage or low amplitude complementary current and flows the same to a terminating resistor.

[0032]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a current adjusting MOSFET is added to each of the plurality of output circuits of the LVDS configuration, one of which is used as one dummy output circuit, and a terminating resistor is connected to the output terminal to form a high level and a low level. The current adjusting M is compared with the output high level and the low level level so that the desired output level is obtained.
A low-amplitude signal can be formed stably by forming a control signal for the OSFET and supplying the control signal to each of the current adjusting MOSFETs of the other plurality of output circuits to perform automatic current adjustment. An extremely easy-to-use semiconductor integrated circuit device can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an output circuit of a semiconductor integrated circuit device according to the present invention and a current adjusting circuit thereof.

FIG. 2 is a circuit diagram showing another embodiment of an output circuit and a current adjusting circuit of the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a configuration diagram showing an example of a signal transmission method using the semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

COUNT1, COUNT2 ... Counter circuit, COUNT
... Control circuit, DOB1, DOB2 to DOBN ... output circuit, LOG ... internal logic circuit, SA1, SA2 ... sense circuit, MP00 to MP11 ... P-channel type MOSFE
T, MN00 to MN11 ... N-channel type MOSFE
T, MPS1, MPS2: P-channel type for current adjustment,
MNS1, MNS2 ... N-channel type MOS for current adjustment
FET, LSI, LSI1, LSI2 ... Semiconductor integrated circuit device.

Claims (5)

[Claims] 1. A first constant current source MOSFET provided on a power supply voltage side, and a second constant current source MOSF provided on a ground potential side of a circuit.
A first CMOS output provided between the first and second constant current source MOSFETs and receiving a positive-phase input signal and forming a first output signal transmitted from a first output terminal; And a circuit, provided between the first and second constant current source MOSFETs, for receiving a negative-phase input signal having a reverse-phase relationship to the positive-phase input signal and transmitting the signal from a second output terminal. Second
A second CMOS output circuit for forming an output signal of the first and second constant current source MOSFETs, and a plurality of first and second current adjusting MOSFET circuits respectively provided in parallel with the first and second constant current source MOSFETs. A plurality of output circuits having a plurality of level adjustment functions, wherein one of the plurality of output circuits is used as a dummy output circuit to provide a predetermined resistance value between the first and second output terminals. And the first output circuit sends out a high-level output signal through the first output terminal, and the second output circuit sends the output signal through the second output terminal. A high-level output signal is transmitted, and a voltage of a first output terminal of the dummy output circuit is compared with a first reference voltage corresponding to a high level to be output by a first comparison circuit. Output terminal The first current adjusting MOSFET as but a desired signal level
Forming a first control signal for controlling the second output terminal of the dummy output circuit and a second reference voltage corresponding to a low level to be output by a second comparison circuit. The second current adjusting MOSFET so that the voltage of the output terminal of the second terminal becomes a desired signal level.
And a control circuit for forming a second control signal for controlling the first and second control signals. The first and second control signals formed by the control circuit are provided to other output circuits except the dummy output circuit. A semiconductor integrated circuit device provided to first and second current adjusting MOSFETs. 2. The control circuit according to claim 1, wherein the first and second current adjusting MOSFETs generate a current having a binary weight. A binary counter circuit is provided, and a counting operation is performed by the first and second comparison circuits.
A current adjusting M whose count output has a corresponding binary weight.
A semiconductor integrated circuit device supplied to a gate of an OSFET. 3. The control circuit according to claim 2, wherein in the first operation, the first comparator circuit and the first counter circuit adjust the level of a high level or the second comparator circuit and the second counter. In the second operation, the second comparator circuit and the second counter circuit adjust the low level, or the first comparator circuit and the first counter circuit adjust the low level. At least in the third operation, the first comparison circuit and the first
A high-level level adjustment by the counter circuit or a low-level level adjustment by the second comparison circuit and the second counter circuit. 4. The semiconductor integrated circuit device according to claim 2, wherein the terminating resistor is supplied with the midpoint potential of the high level and the low level to be output at the midpoint. 5. The control circuit according to claim 4, wherein the first comparator circuit and the first counter circuit adjust a high-level level, and the second comparator circuit and a second counter circuit reduce a low-level level. A semiconductor integrated circuit device wherein adjustment is performed simultaneously.