JP2000196017A5 - Semiconductor device manufacturing method - Google Patents
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- JP2000196017A5 JP2000196017A5 JP1998369686A JP36968698A JP2000196017A5 JP 2000196017 A5 JP2000196017 A5 JP 2000196017A5 JP 1998369686 A JP1998369686 A JP 1998369686A JP 36968698 A JP36968698 A JP 36968698A JP 2000196017 A5 JP2000196017 A5 JP 2000196017A5
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- 239000004065 semiconductor Substances 0.000 title claims 34
- 238000004519 manufacturing process Methods 0.000 title claims 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 19
- 229910052710 silicon Inorganic materials 0.000 claims 19
- 239000010703 silicon Substances 0.000 claims 19
- 239000000758 substrate Substances 0.000 claims 17
- 238000005530 etching Methods 0.000 claims 15
- 239000012535 impurity Substances 0.000 claims 12
- 239000002184 metal Substances 0.000 claims 12
- 229920002120 photoresistant polymer Polymers 0.000 claims 10
- 238000000151 deposition Methods 0.000 claims 8
- 239000011229 interlayer Substances 0.000 claims 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 5
- 239000003990 capacitor Substances 0.000 claims 4
- 238000010438 heat treatment Methods 0.000 claims 4
- 150000002500 ions Chemical class 0.000 claims 4
- 238000002955 isolation Methods 0.000 claims 4
- 230000002093 peripheral Effects 0.000 claims 4
- 230000001747 exhibiting Effects 0.000 claims 3
- 229910021332 silicide Inorganic materials 0.000 claims 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000002425 crystallisation Methods 0.000 claims 1
- 230000005712 crystallization Effects 0.000 claims 1
- 238000005755 formation reaction Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
Claims (10)
（ｂ）前記分離領域で囲まれた半導体基板主面の活性領域にゲート絶縁膜を形成し、前記半導体基板の全面にシリコン膜を形成する工程、
（ｃ）少なくとも前記第１領域の前記シリコン膜に第１導電型の不純物をイオン注入する工程、
（ｄ）前記シリコン膜上に第１絶縁膜を形成する工程、
（ｅ）ゲート電極パターンにパターニングされた第１フォトレジスト膜を前記第１絶縁膜上に形成する工程、
（ｆ）前記第１フォトレジスト膜の存在下で前記第１絶縁膜およびシリコン膜をエッチングし、キャップ絶縁膜およびゲート電極を形成する工程、
（ｇ）前記ゲート電極およびキャップ絶縁膜を覆い、前記第１絶縁膜に対してエッチング選択比を有する第２絶縁膜を堆積し、異方性エッチングにより前記第２絶縁膜をエッチングして前記ゲート電極およびキャップ絶縁膜の側壁にサイドウォールを形成する工程、
（ｈ）前記キャップ絶縁膜およびサイドウォールの存在下で前記半導体基板を熱処理し、前記活性領域の表面に前記第１絶縁膜に対してエッチング選択比を有する第３絶縁膜を形成する工程、
（ｉ）前記第３絶縁膜およびサイドウォールの存在下で前記キャップ絶縁膜を選択的に除去する工程、
（ｊ）前記第１領域を覆う第２フォトレジスト膜を形成し、前記第２フォトレジスト膜の存在下でエッチング処理を施し、前記第２および第３領域の前記第３絶縁膜を除去する工程、
（ｋ）前記半導体基板の全面に金属膜を堆積する工程、
（ｌ）前記半導体基板を熱処理し、前記第１、第２および第３領域の前記ゲート電極の表面ならびに前記第２および第３領域の前記活性領域の表面に前記金属膜を構成する金属のシリサイド膜を形成する工程、
（ｍ）未反応の前記金属膜を除去する工程、
を含むことを特徴とする半導体装置の製造方法。(A) A first region in which a selection MISFET of a memory cell is formed, a second region in which a first channel type first MISFET of a peripheral circuit or logic circuit is formed, and a second channel second of the peripheral circuit or logic circuit Forming an isolation region on the main surface of the semiconductor substrate having a third region in which the second MISFET is formed;
(B) forming a gate insulating film on an active region of the main surface of the semiconductor substrate surrounded by the isolation region, and forming a silicon film on the entire surface of the semiconductor substrate;
(C) implanting an impurity of a first conductivity type into at least the silicon film of the first region;
(D) forming a first insulating film on the silicon film;
(E) forming a first photoresist film patterned into a gate electrode pattern on the first insulating film;
(F) etching the first insulating film and the silicon film in the presence of the first photoresist film to form a cap insulating film and a gate electrode;
(G) covering the gate electrode and the cap insulating film, depositing a second insulating film having an etching selectivity with respect to the first insulating film, and etching the second insulating film by anisotropic etching; Forming a sidewall on the side wall of the electrode and the cap insulating film,
(H) heat-treating the semiconductor substrate in the presence of the cap insulating film and the sidewalls to form a third insulating film having an etching selectivity to the first insulating film on the surface of the active region;
(I) selectively removing the cap insulating film in the presence of the third insulating film and the sidewalls;
(J) forming a second photoresist film covering the first region, and performing an etching process in the presence of the second photoresist film to remove the third insulating film in the second and third regions ,
(K) depositing a metal film on the entire surface of the semiconductor substrate;
(L) A heat treatment of the semiconductor substrate to form a metal silicide forming the metal film on the surface of the gate electrode in the first, second and third regions and the surface of the active region in the second and third regions Forming a film,
(M) removing the unreacted metal film,
A method of manufacturing a semiconductor device, comprising:
前記（ｇ）工程と（ｈ）工程の間に、前記キャップ絶縁膜およびサイドウォールの存在下で、前記第２領域にｎ型の導電型を示す不純物を高濃度にイオン注入し、また、前記第３領域にｐ型の導電型を示す不純物を高濃度にイオン注入する工程を有することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 1,
Between the step (g) and the step (h), in the presence of the cap insulating film and the sidewall, the second region is ion-implanted with a high concentration of an impurity exhibiting an n-type conductivity type, and A method of manufacturing a semiconductor device, comprising the step of ion-implanting an impurity showing a p-type conductivity type at a high concentration in a third region.
前記（ｈ）工程と（ｊ）工程の間に、前記キャップ絶縁膜またはゲート電極、サイドウォールおよび第３絶縁膜の存在下で、前記第２領域にｎ型の導電型を示す不純物を高濃度にイオン注入し、また、前記第３領域にｐ型の導電型を示す不純物を高濃度にイオン注入する工程を有することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 1,
Between the step (h) and the step (j), the second region has a high concentration of an impurity exhibiting an n-type conductivity in the presence of the cap insulating film or gate electrode, the sidewall, and the third insulating film. A method of manufacturing a semiconductor device comprising the steps of: ion implanting, and ion implanting an impurity exhibiting a p-type conductivity type at a high concentration in the third region.
前記（ｂ）工程におけるシリコン膜はアモルファスシリコン膜であり、前記アモルファスシリコン膜への前記不純物の導入後に熱処理を施し、前記シリコン膜を結晶化することを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to any one of claims 1 to 3 ,
The silicon film in the step (b) is an amorphous silicon film, and heat treatment is performed after introduction of the impurity into the amorphous silicon film to crystallize the silicon film.
（ｂ）前記分離領域で囲まれた半導体基板主面の活性領域にゲート絶縁膜を形成し、前記半導体基板の全面に第１シリコン膜を堆積する工程、
（ｃ）前記第１および第２領域の前記第１シリコン膜に第１導電型の不純物をイオン注入し、前記第３領域の前記第１シリコン膜に第２導電型の不純物をイオン注入する工程、
（ｄ）前記第１シリコン膜上に、第１導電型の不純物を含む第２シリコン膜を形成する工程、
（ｅ）前記第２シリコン膜上に第１絶縁膜を堆積する工程、
（ｆ）ゲート電極のパターンにパターニングされた第１フォトレジスト膜を前記第１絶縁膜上に形成する工程、
（ｇ）前記第１フォトレジスト膜の存在下で前記第１絶縁膜、第１および第２シリコン膜をエッチングし、前記第１絶縁膜からなるキャップ絶縁膜および前記第１および第２シリコン膜からなるゲート電極を形成する工程、
（ｈ）前記ゲート電極およびキャップ絶縁膜を覆い、前記第１絶縁膜に対してエッチング選択比を有する第２絶縁膜を堆積し、異方性エッチングにより前記第２絶縁膜をエッチングして前記ゲート電極およびキャップ絶縁膜の側壁にサイドウォールを形成する工程、
（ｉ）前記キャップ絶縁膜およびサイドウォールの存在下で前記半導体基板を熱処理し、前記分離領域に囲まれた活性領域の表面に前記第１絶縁膜に対してエッチング選択比を有する第３絶縁膜を形成する工程、
（ｊ）前記第３絶縁膜およびサイドウォールの存在下で前記キャップ絶縁膜を選択的に除去する工程、
（ｋ）前記ゲート電極、サイドウォールおよび第３絶縁膜の存在下で、前記第２領域に第１導電型の不純物を高濃度にイオン注入し、また、前記第３領域に第２導電型の不純物を高濃度にイオン注入する工程、
（ｌ）前記第１領域を覆う第２フォトレジスト膜を形成し、前記第２フォトレジスト膜の存在下でエッチング処理を施し、前記第２および第３領域の前記第３絶縁膜を除去する工程、
（ｍ）前記半導体基板の全面に金属膜を堆積する工程、
（ｎ）前記半導体基板を熱処理し、前記第１、第２および第３領域の前記ゲート電極の表面ならびに前記第２および第３領域の前記活性領域の表面に前記金属膜を構成する金属のシリサイド膜を形成する工程、
（ｏ）未反応の前記金属膜を選択的に除去する工程、
を含むことを特徴とする半導体装置の製造方法。(A) A first region in which a selection MISFET of a memory cell is formed, a second region in which a first channel type first MISFET of a peripheral circuit or logic circuit is formed, and a second channel second of the peripheral circuit or logic circuit Forming an isolation region on the main surface of the semiconductor substrate having a third region in which the second MISFET is formed;
(B) forming a gate insulating film on an active region of the main surface of the semiconductor substrate surrounded by the isolation region, and depositing a first silicon film on the entire surface of the semiconductor substrate;
(C) implanting ions of a first conductivity type impurity into the first silicon film of the first and second regions, and ion implanting a second conductivity type impurity into the first silicon film of the third region ,
(D) forming a second silicon film containing an impurity of the first conductivity type on the first silicon film;
(E) depositing a first insulating film on the second silicon film;
(F) forming a first photoresist film patterned in a pattern of a gate electrode on the first insulating film;
(G) etching the first insulating film and the first and second silicon films in the presence of the first photoresist film to form a cap insulating film made of the first insulating film and the first and second silicon films Forming a gate electrode
(H) A second insulating film covering the gate electrode and the cap insulating film and having an etching selectivity to the first insulating film is deposited, and the second insulating film is etched by anisotropic etching to form the gate Forming a sidewall on the side wall of the electrode and the cap insulating film,
(I) A third insulating film having an etching selectivity with respect to the first insulating film on the surface of an active region surrounded by the separation region, wherein the semiconductor substrate is heat-treated in the presence of the cap insulating film and the sidewalls. Forming the
(J) selectively removing the cap insulating film in the presence of the third insulating film and the sidewalls;
(K) Impurities of a first conductivity type are ion-implanted in the second region at a high concentration in the presence of the gate electrode, sidewalls and a third insulating film, and a second conductivity type is formed in the third region Implanting impurities to a high concentration,
(L) forming a second photoresist film covering the first region, and performing an etching process in the presence of the second photoresist film to remove the third insulating film in the second and third regions ,
(M) depositing a metal film on the entire surface of the semiconductor substrate;
(N) A heat treatment of the semiconductor substrate to form a metal silicide constituting the metal film on the surface of the gate electrode in the first, second and third regions and the surface of the active region in the second and third regions Forming a film,
(O) selectively removing the unreacted metal film;
A method of manufacturing a semiconductor device, comprising:
前記（ｂ）工程における第１シリコン膜はアモルファスシリコン膜であり、前記アモルファスシリコン膜への前記不純物の導入後であって前記第２シリコン膜の形成前に熱処理を施し、前記第１シリコン膜を結晶化することを特徴とする半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5 , wherein
The first silicon film in the step (b) is an amorphous silicon film, and a heat treatment is performed after the introduction of the impurity into the amorphous silicon film and before the formation of the second silicon film, thereby forming the first silicon film. A method of manufacturing a semiconductor device characterized by crystallization.
（ｂ）前記シリコン膜上に第１絶縁膜を堆積する工程、
（ｃ）前記第１絶縁膜上にゲート電極パターンにパターニングされたフォトレジスト膜を形成し、前記フォトレジスト膜の存在下で前記第１絶縁膜およびシリコン膜をエッチングし、ゲート電極および前記ゲート電極上のキャップ絶縁膜を形成する工程、
（ｄ）前記半導体基板の全面に前記第１絶縁膜に対してエッチング選択比を有する第２絶縁膜を堆積し、前記第２絶縁膜を異方性エッチングすることにより前記キャップ絶縁膜およびゲート電極の側壁にサイドウォールを形成する工程、
（ｅ）前記キャップ絶縁膜およびサイドウォールの存在下で前記半導体基板に熱処理を施し、分離領域に囲まれた活性領域の表面に前記第１絶縁膜に対してエッチング選択比を有する第３絶縁膜を形成する工程、
（ｆ）前記第３絶縁膜およびサイドウォールの存在下で前記キャップ絶縁膜を選択的に除去する工程、
（ｇ）前記半導体基板の全面に金属膜を堆積する工程、
（ｈ）前記半導体基板を熱処理し、前記ゲート電極の表面に前記金属膜を構成する金属のシリサイド膜を形成する工程、
（ｉ）未反応の前記金属膜を除去する工程、
を含むことを特徴とする半導体装置の製造方法。(A) sequentially forming a gate insulating film and a polycrystalline or amorphous silicon film on the main surface of the semiconductor substrate;
(B) depositing a first insulating film on the silicon film;
(C) forming a photoresist film patterned into a gate electrode pattern on the first insulating film, etching the first insulating film and the silicon film in the presence of the photoresist film, and forming a gate electrode and the gate electrode Forming an upper cap insulating film,
(D) depositing a second insulating film having an etching selectivity to the first insulating film over the entire surface of the semiconductor substrate, and anisotropically etching the second insulating film to form the cap insulating film and the gate electrode Forming a sidewall on the sidewall of the
(E) A third insulating film having an etching selectivity with respect to the first insulating film on the surface of the active region surrounded by the separation region, the semiconductor substrate being heat-treated in the presence of the cap insulating film and the sidewalls. Forming the
(F) selectively removing the cap insulating film in the presence of the third insulating film and the sidewalls;
(G) depositing a metal film on the entire surface of the semiconductor substrate;
(H) heat treating the semiconductor substrate to form a silicide film of a metal forming the metal film on the surface of the gate electrode;
(I) removing the unreacted metal film,
A method of manufacturing a semiconductor device, comprising:
前記第１絶縁膜はシリコン窒化膜であり、前記第２および第３絶縁膜はシリコン酸化膜であることを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to any one of claims 1 to 5 ,
A method of manufacturing a semiconductor device, wherein the first insulating film is a silicon nitride film, and the second and third insulating films are silicon oxide films.
（ａ）前記選択ＭＩＳＦＥＴならびに第１および第２ＭＩＳＦＥＴを覆う第１層間絶縁膜を形成し、前記選択ＭＩＳＦＥＴの一方のソース・ドレイン領域に接続する第１プラグを前記第１層間絶縁膜に形成する工程、
（ｂ）前記第１層間絶縁膜上に、前記第１プラグに接続するビット線を形成する工程、
（ｃ）前記ビット線を覆う第２層間絶縁膜を形成し、前記選択ＭＩＳＦＥＴの他方のソース・ドレイン領域に接続する第２プラグを前記第１および第２層間絶縁膜に形成する工程、
（ｄ）前記第２層間絶縁膜上に、前記第２プラグに接続する前記メモリセルのキャパシタ下部電極を形成する工程、
を有することを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to any one of claims 1 to 5 , further comprising:
(A) forming a first interlayer insulating film covering the selection MISFET and the first and second MISFETs, and forming a first plug connected to one of the source / drain regions of the selection MISFET in the first interlayer insulating film ,
(B) forming a bit line connected to the first plug on the first interlayer insulating film;
(C) forming a second interlayer insulating film covering the bit line, and forming a second plug connected to the other source / drain region of the selection MISFET in the first and second interlayer insulating films;
(D) forming a capacitor lower electrode of the memory cell connected to the second plug on the second interlayer insulating film;
A method of manufacturing a semiconductor device, comprising:
（ａ）多結晶シリコン膜からなるキャパシタ下部電極を形成する工程、
（ｂ）前記キャパシタ下部電極上にシリコン窒化膜からなるキャパシタ絶縁膜を形成する工程、
を有することを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to any one of claims 1 to 5 , further comprising:
(A) forming a capacitor lower electrode made of a polycrystalline silicon film;
(B) forming a capacitor insulating film made of a silicon nitride film on the capacitor lower electrode;
A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36968698A JP4077966B2 (en) | 1998-12-25 | 1998-12-25 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36968698A JP4077966B2 (en) | 1998-12-25 | 1998-12-25 | Manufacturing method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2000196017A JP2000196017A (en) | 2000-07-14 |
| JP2000196017A5 true JP2000196017A5 (en) | 2005-04-21 |
| JP4077966B2 JP4077966B2 (en) | 2008-04-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36968698A Expired - Fee Related JP4077966B2 (en) | 1998-12-25 | 1998-12-25 | Manufacturing method of semiconductor device |
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| JP (1) | JP4077966B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002100749A (en) * | 2000-09-25 | 2002-04-05 | Sony Corp | Semiconductor device and its manufacturing method |
| JP4928675B2 (en) * | 2001-03-01 | 2012-05-09 | エルピーダメモリ株式会社 | Semiconductor device |
| JP2002324850A (en) | 2001-04-25 | 2002-11-08 | Mitsubishi Electric Corp | Semiconductor memory device and its manufacturing method |
| KR100399440B1 (en) * | 2001-06-30 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of Manufacturing MDL Semiconductor Device |
| JP4334811B2 (en) | 2002-03-28 | 2009-09-30 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
| JP6246664B2 (en) * | 2014-06-04 | 2017-12-13 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
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1998
- 1998-12-25 JP JP36968698A patent/JP4077966B2/en not_active Expired - Fee Related
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