JP2000022103A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce difference on a semiconductor substrate by patterning the thickness of a dummy pattern of a capacitor structure formed near a lower electrode storage node of a capacitor so as to become thinner as it comes close to the memory cell side. SOLUTION: A storage node (ST) 9 is a storage node as the lower electrode of a capacitor. A first dummy pattern 19 is formed parallel to along ST9 of the capacitor at the end of memory side. The first dummy pattern 19 is in the same layer as the ST9 and has a thin-film part 19A whose thickness is thinned by removing patterning the upper surface at the end of memory cell side near the first dummy pattern 19. A second dummy pattern 29 is formed at the end of the memory cell side. An interlayer insulation film 23 coats a capacitor 22, the first dummy pattern 19 and the second dummy pattern 29. The inclined upper surface of the interlayer insulation film 23 is sloped in the direction of the end of the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a DRAM (Dynanic Rand).
om Access Memory).

[0002]

2. Description of the Related Art A conventional semiconductor device and a method of manufacturing the same will be described below with reference to the drawings.

FIG. 8 is a sectional view of a conventional semiconductor device.
1 is a semiconductor substrate, 2 is an element isolation film, 3 is an impurity layer, 4 is a gate electrode, and 5 is a wiring.

Reference numeral 6 denotes an insulating film covering the gate electrode 4, 7 denotes a bit line contacted with the impurity layer 3, and 8 denotes an insulating film covering the bit line 7.

Further, reference numeral 9 denotes a storage node (hereinafter referred to as ST) as a capacitor lower electrode contacting the impurity layer 3; 10 a capacitor dielectric film;
1 is a cell plate (hereinafter, referred to as a capacitor upper electrode)
Called SP. ), And a capacitor 1 at 9, 10, 11
2.

Reference numeral 13 denotes an interlayer insulating film that covers the capacitor 12, and each contact portion is formed via the interlayer insulating film 13. That is, for example, a contact portion 14A that contacts the substrate 1 and a contact portion 14B that contacts the SP11 are formed.

At this time, the difference between the depth of the shallowest contact portion (for example, the contact portion 14B on the SP11) and the deepest contact portion (for example, the contact portion 14A that contacts the substrate 1) is large. Become.

Therefore, if the etching necessary for opening the deepest contact portion is performed, the shallowest contact portion considerably over-etches the underlying polysilicon film of SP11.

Therefore, it is necessary to make the polysilicon film thicker than necessary. However, in this case, the absolute step between the memory cell section and the peripheral circuit section is further increased.

[0010] A method of dividing the contact portion into a plurality of steps according to the depth of the contact portion is also conceivable. However, in this case, the productivity is reduced.

Therefore, the present inventors formed a dummy pattern 19 having a capacitor structure in the vicinity of a capacitor in a semiconductor device having a stacked capacitor cell structure as shown in FIG.
A technology for reducing the difference in contact depth between the contact portions 14A and 24B by forming the contact portions 24B in the interlayer insulating film 23 whose thickness is increased by the above method has been developed.

Then, as shown in FIG.
A tungsten plug 26 is formed in 4A and 24B via a barrier metal film 25, and an Al wiring 27 is formed.

[0013]

Here, the following problems have occurred in the above-described step of forming the tungsten plug. That is, as shown in FIG.
A, a barrier metal film 25A is formed on the entire surface including the inside of the semiconductor device, and a tungsten film 26A is formed on the barrier metal film 25A.
To form

Then, the tungsten film 26A is etched back, and as shown in FIG.
When the tungsten plugs 26 are formed in the 4A and 24B via the barrier metal film 25A, the inclination angle ∠θ2 of the upper surface of the interlayer insulating film 23 at the end of the memory cell becomes strict because the dummy pattern 19 is interposed. As a result, a defect such as the tungsten film 26A remaining on the inclined surface may occur as shown in FIG.

Accordingly, it is an object of the present invention to provide a semiconductor device with reduced steps and a method for manufacturing the same.

[0016]

SUMMARY OF THE INVENTION The present invention provides a semiconductor device having a stacked capacitor cell structure.
The dummy pattern 19 of the capacitor structure formed near the lower electrode ST9 of the capacitor is patterned so that the film thickness becomes thinner toward the memory cell end side.

Then, the manufacturing method is such that a first conductive film is formed and patterned on the upper surfaces of the insulating films 6 and 8 and in the contact portions 30 to form the lower electrode ST9 of the capacitor and the lower electrode ST9 of the capacitor. A dummy pattern 19 having a capacitor structure is formed on the insulating films 6 and 8 in the vicinity. Next, a capacitor dielectric film 20 is formed to cover the lower electrode ST9 and the dummy pattern 19 of the capacitor, and a second conductive film is formed to cover the capacitor dielectric film 20. Next, after forming a photoresist film having a termination in the middle of the memory cell end side on the upper surface of the dummy pattern 19 on the second conductive film, the second conductive film is patterned using the photoresist film as a mask to form a capacitor. Of the upper electrode SP21, and
Patterning and removing a predetermined amount of the upper surface of the dummy pattern that is not masked by the photoresist film.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings. The same components as those of the conventional structure are denoted by the same reference numerals, and the description will be simplified.

FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention, wherein 1 is a semiconductor substrate of one conductive film type, for example, a P type, 2 is an element isolation film, and 3 is a reverse conductive film type, for example, an N + type. 4 is a gate electrode and 5 is a wiring. The impurity layer 3 may be an impurity layer having an LDD or DDD structure including a conventionally known low concentration impurity layer and a high concentration impurity layer. Reference numeral 6 denotes an oxide film covering the gate electrode 4 and the like, 7 denotes a bit line in contact with the impurity layer 3, and 8 denotes an oxide film covering the bit line 7.

Reference numeral 9 denotes a storage node (hereinafter, referred to as ST) as a capacitor lower electrode. Reference numeral 19 denotes the same layer as ST9 of the capacitor, which is a feature of the present invention, and the upper surface on the memory cell end side has This is a first dummy pattern having a thin film portion 19A whose thickness has been reduced by patterning. The first dummy pattern is located closer to the memory cell end than ST9 of the capacitor and along the capacitor ST9 (in the front-back direction of the paper surface of FIG. 1). They are formed in parallel.

Reference numeral 20 denotes a capacitor dielectric film that covers the capacitor ST9 and the first dummy pattern 19. Reference numeral 21 denotes a cell plate (hereinafter, referred to as SP) as a capacitor upper electrode. , 21 constitute a capacitor 22. In addition, in this embodiment, a capacitor having the same configuration as the capacitor ST9 is referred to as a first dummy pattern 19,
It can be said that this constitutes the first dummy pattern.

Reference numeral 29 denotes a second dummy pattern formed on the end of the memory cell near the first dummy pattern 19, and the capacitor dielectric film 20 and the capacitor SP21 are formed.
A laminated film for forming is formed by patterning,
As in the case of the first dummy pattern, the S
It is formed in parallel along T9 (in the front-back direction on the paper surface of FIG. 1).

Reference numeral 23 denotes an interlayer insulating film which covers the capacitor 22, the first dummy pattern 19, and the second dummy pattern 29. Each contact portion is formed via the interlayer insulating film 23. That is, for example, the contact portion 24 that contacts the substrate 1 or the SP 21
A contact portion (not shown) for contacting the upper portion, a tungsten plug 26 is buried in each contact portion 24 via a barrier metal film 25, and an Al wiring 27 is formed on each tungsten plug 26.

At this time, the first dummy pattern 19 and the second
By forming the dummy pattern 29 of FIG.
The inclination of the upper surface of the device 3 becomes gentler toward the end of the memory cell as shown in FIG. 1 than the inclination of the conventional device as shown in FIG. 9 (inclination angle ∠θ1 <inclination angle ∠θ).
2).

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described.

First, as shown in FIG. 2, an element isolation film 2 is formed in a region other than an active region on a semiconductor substrate 1 of one conductive film type, for example, a P type, and a gate insulating film is formed in a region other than the element isolation film 2. A film is formed, and a conductive film made of a polysilicon film or the like is patterned on the gate insulating film to form the gate electrode 4 and the wiring 5. Incidentally, the gate electrode 4 and the wiring 5 are not limited to the polysilicon film, but may be a laminated film composed of, for example, a polysilicon film and a tungsten polycide (WSix) film.

Using the gate electrode 4 as a mask, a reverse conductive film type, for example, phosphorus ions are ion-implanted to form an N + type impurity layer 3 in the surface layer of the substrate 1 adjacent to the gate electrode 4. An oxide film 6 to be coated is formed. Further, after forming a contact portion that contacts the impurity layer 3 via the oxide film 6, a bit line 7 is formed in the contact portion, and an oxide film 8 that covers the bit line 7 is formed.

Then, a contact portion 30 for forming a capacitor is formed on the portion of the oxide films 6 and 8 on the impurity layer 3 not on the bit line 7 side.

Next, as shown in FIG.
Lower electrode S of capacitor in contact with impurity layer 3 of
A first conductive film for forming T9 is formed, and the conductive film is patterned to form a dummy pattern 19 in the same layer as ST9 of the capacitor. Note that, as the conductive film, for example, a polysilicon film is used to form a capacitor ST9 and a dummy pattern 19 having a thickness of about 6000 °.

Subsequently, as shown in FIG. 4, a capacitor dielectric film 20 having a thickness of about 80 to 100 ° and a capacitor having a thickness of about 1000 to 1500 ° are formed on the entire surface of the substrate so as to cover the capacitor ST9 and the dummy pattern 19. The second conductive film 21A for forming the upper electrode SP is formed. The capacitor dielectric film 20 is, for example, a laminated film of a SiN film and a SiO2 film, and the second conductive film 21A is, for example, a polysilicon film.

Next, as shown in FIG. 5, a first photoresist film 40A having an end on the upper side of the dummy pattern 19 on the memory cell end side is formed, and further formed at a desired position on the memory cell end side. The second conductive film 21A
After a second photoresist film 40B is formed thereon, the second conductive film 21A is patterned by using the first and second photoresist films 40A and 40B as a mask to form the capacitor SP21, and The upper surface of the first dummy pattern 19, which is not masked by the photoresist film 40A, is patterned and removed by a predetermined amount (for example, about 1500 °) to form a thin film portion 19A having a reduced thickness. Further, a second dummy pattern 29 made of a laminated film of the capacitor dielectric film 20 and the second conductive film 21A is formed under the second photoresist film 40B.

Subsequently, as shown in FIG. 6, an interlayer insulating film 23 made of, for example, a TEOS film or a BPSG film is formed on the entire surface so as to cover the capacitor SP9 and the first and second dummy patterns 19 and 29. Then, contact portions 24A and 24B (see FIG. 10) and the like are formed via the interlayer insulating film 23.

Next, as shown in FIG. 7, a barrier metal film 25 is formed on the entire surface of the substrate including the insides of the contact portions 24A and 24B.
A and a tungsten film 26A are formed.

Then, the tungsten film 26A is etched back to form a tungsten plug 26 in the contact portions 24A and 24B via a barrier metal film 25, and then an Al wiring 27 is formed on the tungsten plug 26.
Is formed, thereby forming the semiconductor device shown in FIG.

At this time, the first and second dummy patterns 19 and 29 (thickness of the first dummy pattern 19> second dummy pattern) are closer to the end of the memory cell than ST9 of the capacitor, which is a feature of the present invention. 29 is formed in parallel along the capacitor ST9, the step at the end of the memory cell can be gradually reduced, and the interlayer insulating film 23 is formed.
Since the inclination of the upper surface becomes gentler than the inclination of the conventional device,
In the above-described etch-back step of the tungsten film 26A, the tungsten film 26A does not remain in such an inclined portion.

As described above, according to the present invention, in the semiconductor device having the first dummy pattern 19 in the same layer as the capacitor ST9 near the capacitor ST9, the memory cell on the upper surface of the first dummy pattern 19 is provided. By reducing the film thickness on the end side, steps can be reduced, and moreover,
Since the step of reducing the thickness of the first dummy pattern 19 for reducing the step can be performed at the time of patterning the SP21 of the capacitor, the number of manufacturing steps does not increase.

In the present embodiment, the structure has both the first and second dummy patterns 29. However, the present invention is not limited to this, and a structure having only the first dummy pattern 19 may be used. If it is not so severe, a configuration having only the second dummy pattern 29 may be used. Further, if the configuration has the second dummy pattern 29, the upper surface of the first dummy pattern 19 on the memory cell end side can be removed. There is a possibility that the remaining film of the tungsten film can be eliminated.
In short, various dummy patterns may be formed according to the expected steps.

[0038]

According to the present invention, in a semiconductor device having a dummy pattern in the same layer as the capacitor in the vicinity of the capacitor, the step thickness can be reduced by reducing the thickness of the upper surface of the dummy pattern on the side of the memory cell. I can do it.

In addition, the step of reducing the thickness of the dummy pattern for reducing the step is performed simultaneously with the patterning of the capacitor SP, so that the number of manufacturing steps does not increase.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a sectional view showing a conventional semiconductor device.

FIG. 9 is a cross-sectional view showing a conventional semiconductor device.

FIG. 10 is a schematic plan view showing the conventional semiconductor device shown in FIG.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 12 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

Claims (4)

[Claims] An upper surface of an underlying insulating film formed to cover the underlying pattern and having a contact portion, a capacitor formed in the contact portion, and a capacitor formed on the underlying insulating film near the capacitor A semiconductor device having a stacked capacitor cell structure having a dummy pattern having a structure, wherein the dummy pattern having the capacitor structure is patterned so that the film thickness of the dummy pattern decreases toward the end of the memory cell. 2. A capacitor formed so as to cover an underlying pattern and having a contact portion and an upper surface of the underlying insulating film and a capacitor formed in the contact portion, and a capacitor formed on the underlying insulating film near the capacitor. In a semiconductor device having a stacked capacitor cell structure having a dummy pattern having a structure, a base insulating film formed so as to cover a base pattern and having a contact portion; and an upper surface of the base insulating film and formed in the contact portion. A lower electrode of the capacitor, a dummy pattern having a capacitor structure formed on the base insulating film near the lower electrode of the capacitor, the thickness of which is thinner toward the memory cell end; and a lower electrode of the capacitor. A capacitor dielectric film formed on the substrate, and so as to cover the capacitor dielectric film. The semiconductor device according to claim and made the upper electrode of the capacitor, to have a an interlayer insulating film formed so as to cover the upper electrode of the capacitor. 3. A capacitor formed so as to cover an underlying pattern and having a contact portion, an upper surface of the underlying insulating film and a capacitor formed in the contact portion, and a capacitor formed on the underlying insulating film near the capacitor. A method of manufacturing a semiconductor device having a stacked capacitor cell structure having a dummy pattern having a structure, comprising: forming a base insulating film so as to cover a base pattern; and forming a first conductive film on an upper surface of the base insulating film and in a contact portion. Forming and patterning a film to form a lower electrode of the capacitor and forming a dummy pattern having a capacitor structure on the underlying insulating film near the lower electrode of the capacitor; and covering the lower electrode and the dummy pattern of the capacitor. Forming a capacitor dielectric film as follows: Forming a second conductive film so as to cover the first conductive film, forming a photoresist film having a termination on the memory cell end side of the upper surface of the dummy pattern on the second conductive film, and then using the photoresist film as a mask to form the second conductive film. Patterning a second conductive film to form an upper electrode of the capacitor, and patterning and removing a predetermined amount of an upper surface portion of the dummy pattern that is not masked by the photoresist film; and interlayer insulating so as to cover the upper electrode of the capacitor. Forming a film. 4. A capacitor formed to cover an underlying pattern and having an upper surface of an underlying insulating film having a contact portion and a capacitor formed in the contact portion, and a capacitor formed on the underlying insulating film near the capacitor. A method of manufacturing a semiconductor device having a stacked capacitor cell structure having a dummy pattern having a structure, comprising: forming a base insulating film so as to cover a base pattern; and forming a first conductive film on an upper surface of the base insulating film and in a contact portion. Forming and patterning a film to form a lower electrode of the capacitor, and forming a first dummy pattern of a capacitor structure on the base insulating film near the lower electrode of the capacitor; Forming a capacitor dielectric film so as to cover said dummy pattern; Forming a second conductive film so as to cover the first dielectric film; and a first photoresist film having an end on the memory cell end side of the upper surface of the first dummy pattern on the second conductive film; Forming a second photoresist film on the second conductive film on the memory cell end side near the first dummy pattern, and using the first and second photoresist films as a mask to form the second conductive film; By patterning to form an upper electrode of the capacitor, the upper surface of the first dummy pattern not masked by the first photoresist film is patterned and removed by a predetermined amount, and the upper end of the memory cell near the first dummy pattern is removed. A method of manufacturing a semiconductor device, comprising: forming a second dummy pattern; and forming an interlayer insulating film so as to cover an upper electrode of the capacitor. .