JP2000003912A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the errosion or dishing in the case of forming a wiring or a plug by CMP process. SOLUTION: The stopper films 26 in lower polishing rate by CMP process than that of the copper film 25 are formed on the surface of the copper film 24 (a) and (d) so as to polish the copper film 25 and the stopper films 26. At this time, the stopper films 26 are selected out of titanium (Ti) film, tantalum film (Ta) film, tungsten (W) film, tungsten nitride (WN) film, tantalum nitride (TaN) film. In a region in high wiring density (b), the quantity of the copper film 25 to be polished is small but the quantity of the stopper films 26 is large, while in a region in low wiring density (e), the quantity of the copper film 25 to be polished is large but the quantity of the stopper films is small so that almost the same quantities may be polished thereby permitting the just etched state wherein the polishings of both films are finished to be almost simultaneously attained (c) and (f).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a wiring or a connection member having a metal film such as copper formed by a so-called damascene method as a main conductive layer. It is about technology that is effective to apply.

[0002]

2. Description of the Related Art Conventionally, wiring layers in a semiconductor integrated circuit are formed, for example, on November 30, 1984, by Ohm Co., Ltd., "LSI Handbook", p.
292, a high-melting-point metal thin film such as an aluminum (Al) alloy or tungsten (W) is formed on an insulating film, and a photolithography process is used to form a thin film having the same shape as the wiring pattern on the wiring thin film. A resist pattern is formed, and a wiring pattern is formed by a dry etching process using the resist pattern as a mask.

However, in the method using this aluminum alloy, the wiring resistance is remarkably increased as the wiring is miniaturized, and the delay of a signal transmitted to the wiring is increased accordingly.
There have been problems such as a decrease in the performance of the semiconductor device. Particularly in a high-performance logic LSI, a major problem has occurred as a factor that hinders performance. In addition, there is a limit in microfabrication associated with miniaturization of a semiconductor device, and a higher degree of perfection is required for a flattening technique for embedding a patterned wiring with an insulating film. That is, due to the demand for fine processing, the wavelength of the light source used for photolithography is shortened, and the margin in the photolithography process is reduced. If the flatness of the substrate to be processed is not high, the predetermined fine processing is performed under a sufficient margin. May not be able to perform.

For this reason, recently, 1993 VMIC
(VLSI Multilevel Interconnection Conference) As described in Proceedings, pp. 15 to 21, after a wiring metal having copper (Cu) as a main conductor layer is buried in a groove formed in an insulating film, an extra part outside the groove is buried. A method of forming a wiring pattern in a groove by removing a metal by a chemical mechanical polishing (CMP) method, that is, a technique of forming a wiring by a so-called damascene method has been studied. According to the technique of wiring formation using the damascene method, the conductivity is improved because copper is used for the main conductive layer,
Since the metal film is not patterned by photolithography and etching, the limit of microfabrication can be extended. Further, since the surface after wiring is flat in principle, there is no problem of flattening the insulating film. In addition,
This technique can also be applied to connection members (plugs) that connect between wires.

Also, in 1995 VMIC (VLSI Multile
vel Interconnection Conference) Proceedings, p308-
As described on page 314, a technique is known in which a copper film is sputtered, a substrate is heat-treated, the copper film is fluidized, the fluidized copper film is moved into the groove, and the copper film is embedded in the groove. I have. By fluidizing the copper film in this way, it becomes possible to reflow and bury the copper film, which cannot be buried in the groove only by the sputtering method, in the groove.

[0006]

However, the present inventors have recognized that the above prior art has the following problems.

In general, when the formation density of wiring grooves or connection holes formed in an insulating film differs depending on the region of a substrate,
That is, there is a case where the wiring groove or the connection hole in a certain region is formed densely, and the wiring groove or the connection hole in another certain region is formed sparsely. In such a case, the removal amount of the metal film by the CMP method differs between the dense region and the sparse region. That is, in a dense region, a larger amount of metal film is buried in a wiring groove or a connection hole than in a sparse region. Therefore, the amount of metal to be removed by the CMP method is small. More. As a result, an erosion phenomenon occurs in which the thickness of the remaining insulating film differs between the regions of the substrate. Further, since the polishing rate by the CMP method is different by about 100 times between the metal film and the insulating film such as a silicon oxide film, the metal portion, that is, the wiring groove or the connection hole portion is excessively polished.
ing) The phenomenon occurs. This will be described below with reference to the drawings.

FIGS. 24A and 24B are cross-sectional views for explaining erosion and dishing that occur after polishing by the CMP method. FIG. 24A shows a wiring groove 10 of an insulating film 100 made of, for example, a silicon oxide film.
1 shows a schematic cross-sectional view when a wiring 102 made of, for example, copper is formed by the CMP method, and FIG. 24B is a partial cross-sectional view showing a part of FIG. It is.

The wiring 102 is formed by forming a wiring groove 101 on the surface of the insulating film 100, depositing a metal film such as a copper film to be the wiring 102, and removing the copper film in a region other than the wiring groove 101 by a CMP method. It is formed by doing. FIG.
As shown in FIG. 4A, the wiring 102 and the insulating film 100
Is almost flat because it is polished by the CMP method, but not exactly completely as shown in FIG. In other words, erosion 103 corresponding to the difference between the actual surface position Y of the insulating film 100 and the actual surface position Y slightly polished, and dishing 104, which is a depression in the surface portion of the wiring 102, occur. Since the erosion 103 and the dishing 104 occur, the cross-sectional area of the wiring 102 becomes smaller than the cross-sectional area at the time of design, and the resistance of the wiring 102 becomes larger than the designed value. Actual dishing is wiring 10
2, the total dishing 105 is further increased because it occurs not only in the dishing 104 on the surface portion of the insulating film 100 but also in the vicinity of the wiring, and the reduction rate of the cross-sectional area of the wiring 102 is further increased.

[0010] Erosion 103, dishing 104
The mechanism for generating the total dishing 105 is considered as follows. FIG. 25 is a conceptual cross-sectional view shown in a table format for describing the mechanism of generation of erosion 103. As described above, in a general semiconductor device, the wiring density varies in density. FIGS. 25A to 25C show cross sections of a region having a high wiring density, and FIGS. 3 shows a cross section of a sparse region. The surface shape of the copper film before polishing by the CMP method differs in regions where the wiring density is large and small, depending on the density of the wiring groove, as shown in FIGS. The amount of copper film to be reduced is smaller in a region where the wiring density is high than in a region where the wiring density is small. For this reason,
During polishing, a region where the wiring density is high is in a just-etched state (FIG. 25B), and a copper film to be polished still remains in a region where the wiring density is low (FIG. 25 (B)). e)). When the polishing is completed, it is necessary to remove the copper film to be removed over the entire surface of the insulating film. Therefore, it is necessary to continue the polishing, and the copper film in the region where the wiring density is low is removed, and the just etching is performed. (FIG. 25F), the polishing by the CMP method ends. However, in a region where the wiring density is high, the insulating film 100 and the wiring 102 are polished more than the just-etched state, and the insulating film 100 and the wiring 102 are over-polished (FIG. 25C). This overpolished portion is observed as erosion 103.

Further, the dishing 104 is
The polishing rate of copper constituting the insulating film 100 and the polishing rate of the silicon oxide film constituting the insulating film 100 generally differ by about 100 times, and this is caused by excessive polishing of the wiring portion. Further, as a result of the wiring 102 being polished quickly, the pressure from the pad of the CMP polishing concentrates on the opening of the wiring groove 101, and the opening area of the wiring groove 101 is excessively polished, resulting in total dishing 105. .

FIG. 26 is a graph showing the experimental results examined by the present inventors and evaluating the erosion, dishing, and total dishing when the line ratio is changed for the line and space pattern. It can be seen that the erosion increases as the line ratio increases, that is, as the wiring density increases. On the other hand, dishing and total dishing do not depend on the line ratio, that is, the wiring density, and are constant within the range of variation.

As described above, the erosion occurs depending on the wiring density, and the erosion and dishing cause the problem that the cross-sectional area of the wiring deviates from the designed value, as described above. For this reason, as a method of suppressing the occurrence of erosion and dishing, a countermeasure can be considered in which an additive such as an organic acid is mixed with a polishing liquid (slurry) and the polishing liquid is used to improve the polishing characteristics of CMP. However, the improvement of the polishing liquid needs to be individually developed for the material to be polished, and it is difficult to solve the problem with only the polishing agent because it is closely related to the polishing conditions. On the other hand, if the countermeasure can be taken by adding an auxiliary material or a process without using the abrasive, it is simple as long as the addition of the material or the process is easy, and there is no need to develop a difficult abrasive, which is preferable. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for suppressing erosion or dishing without improving a polishing agent when forming a wiring or a plug by a CMP method.

Another object of the present invention is to provide a technique for making the thickness of a conductive member such as a wiring or a plug formed by a CMP method close to a design value. Thereby, the resistance value of the wiring and the like is made closer to the design resistance value, and the reliability and the yield of the semiconductor device are improved.

Still another object of the present invention is to provide a technique for improving the flatness without depending on the wiring density of the base when the unevenness on the surface of the thin film caused by the base unevenness is flattened by the CMP method. To provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The method of manufacturing a semiconductor device according to the present invention comprises:
A substrate made of a semiconductor having a circuit element formed on its main surface or a substrate having a semiconductor layer; and a first film formed on any of the coating layers on the main surface of the substrate and having an uneven shape on its surface. A method for manufacturing a semiconductor device, comprising: a coating; and an embedding member formed by embedding in a concave portion of the first coating, or a planarization layer that covers the first coating and has a planarized surface. A first step of forming a second coating to be an embedded member or a planarization layer, a second step of depositing a third coating having a lower polishing rate by a CMP method than the second coating on the second coating, and a third coating And a third step of polishing the second coating by a CMP method to form an embedded member or a planarization layer.

According to such a method of manufacturing a semiconductor device, the third film can function as a stopper film when the second film is planarized by the CMP method, and the third film can be formed without depending on the unevenness of the base. 2 The coating can be flattened. In addition, even when the second coating is embedded in the recess of the first coating, the flatness of the entire substrate can be improved without excessively polishing the first coating. That is, erosion can be suppressed.

In this case, the thickness of the third film is determined by the polishing amount of the second film (K2) and the polishing amount of the third film (V2). A first condition that a sum (K2 + K3.R) of a value (K3.R) multiplied by a ratio (R = V2 / V3) to a speed (V3) is substantially equal in an arbitrary region of the substrate, or The polishing speed (V3) of the third coating (V3) of the polishing speed (V2) of the second coating is determined by the volume W of the concave portion of the second coating and the volume W3 of the third coating formed on the side wall of the concave portion. ) To the ratio (R
= V2 / V3) can be formed under any one of the second conditions in which the value (W3.R) multiplied by (V3 / R3) is substantially equal.

According to the first condition, since the sum of the polishing amounts of the second film and the third film can be substantially equal in an arbitrary region of the substrate, the surface of the second film can be flattened. According to the method, the amount of reduction in the polishing amount of the second coating (the volume W of the concave portion of the second coating) with respect to the concave portion of the second coating due to the base concave portion, that is, the virtual flat surface, can be compensated for by the third coating. The surface of the coating can be flattened. In the case where the second coating is buried in the base recess, the surfaces of the second coating and the first coating can be similarly flattened, and erosion can be suppressed.

The first film is an insulating film, the concave portion of the first film is a wiring groove or a connection hole, the second film is a copper film containing copper or a copper alloy as a main component, and the embedded member is a metal film. The third film is a metal film selected from a titanium film, a tantalum film, a tungsten film, a tungsten nitride film, and a tantalum nitride film. In this case, suppress erosion and
Wiring or plugs having a film thickness close to the designed value can be formed in the wiring grooves or connection holes of the insulating film as the first coating. As a result, the semiconductor device can be manufactured according to the design values, and the reliability and the yield of the semiconductor device can be improved by eliminating the cause of the decrease in the reliability and the yield due to the decrease in the thickness of the wiring or the plug.

Further, a barrier film for suppressing the reaction between the copper film and the metal film can be formed at the interface between the copper film and the metal film. In this case, the reaction between copper and the metal film is prevented, the conductivity of copper is maintained, and the reliability of the semiconductor device can be improved.

(2) The method of manufacturing a semiconductor device according to the present invention
A substrate made of a semiconductor having a circuit element formed on its main surface or a substrate having a semiconductor layer; and a first film formed on any of the coating layers on the main surface of the substrate and having an uneven shape on its surface. A method for manufacturing a semiconductor device, comprising: a coating; and an embedding member formed by embedding in a concave portion of the first coating, or a planarization layer that covers the first coating and has a planarized surface. A first step of forming a second coating to be an embedding member or a planarizing layer;
A second step of forming a third coating having a polishing rate substantially equal to that of the second coating and having a planarized surface after the formation, and polishing the third coating and the second coating by a CMP method to form an embedded member. Or a third step of forming a flattening layer.

According to such a method of manufacturing a semiconductor device, the third film can function as a sacrificial film, and the second film can be planarized without depending on the irregularities of the base. Erosion can be similarly suppressed when the second coating is embedded in the concave portion of the first coating.

In this case, the first film is an insulating film, the second film is a copper film mainly composed of copper or a copper alloy, and the third film is mainly copper or a copper alloy formed by plating. It can be a copper film or SOG film as a component. In this case, erosion can be suppressed and a wiring or plug having a film thickness close to the designed value can be formed in the wiring groove or the connection hole of the insulating film as the first coating. As a result, the semiconductor device can be manufactured according to the design values, and the reliability and the yield of the semiconductor device can be improved by eliminating the cause of the decrease in the reliability and the yield due to the decrease in the thickness of the wiring or the plug.

In the above-described method (1) or (2), the third coating may be entirely removed or the third coating may be left in the recess of the first coating. In the case where the third coating is left in the concave portion of the first coating, and the polishing rate of the third coating is lower than that of the second coating and equal to that of the first coating, dishing can be effectively suppressed.

(3) The semiconductor device according to the present invention is formed on a substrate made of a semiconductor or a substrate having a semiconductor layer on which a circuit element is formed on its main surface, and on a layer on the main surface of the substrate, An insulating film having a wiring groove or a connection hole and a wiring or plug embedded in the wiring groove or the connection hole are formed, and the surface of the insulating film on which the wiring or the plug is formed is planarized by a CMP method. A semiconductor device,
A film formed of a material having a polishing rate lower than the polishing rate of the metal material forming the wiring or plug by a CMP method is formed on the wiring or plug by embedding the wiring or plug together with the wiring groove or connection hole. is there.

Such a semiconductor device has the above-mentioned (1)
It is manufactured when the third coating is left in the manufacturing method of the above. In this case, as described above, dishing of the wiring or the plug is effectively suppressed, so that the effect of the erosion and the film thickness (cross-sectional area) of the wiring or the plug are obtained.
Can be made closer to the design value. Therefore, the reliability and yield of the semiconductor device can be improved.

The wiring or plug is made of a copper film containing copper or a copper alloy as a main component, and the film is made of any one selected from a titanium film, a tantalum film, a tungsten film, a tungsten nitride film, and a tantalum nitride film. It can be a metal film.

Further, a barrier film for suppressing the reaction between the copper film and the metal film may be formed at the interface between the copper film and the metal film.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a sectional view showing an example of a semiconductor device according to an embodiment of the present invention.

The semiconductor device according to the first embodiment has an n-channel MISFET Qn and a p-channel MISFET Qp formed on a semiconductor substrate 1. n-channel MI
The SFET Qn and the p-channel MISFET Qp
A semiconductor integrated circuit can be formed by forming a MISFET (Complimentary-MISFET). Although not shown, the semiconductor integrated circuit can include passive elements such as a resistor and a capacitor. In the present embodiment, CMIS
An FET is illustrated, but a single-channel MIS of an n-channel MISFET Qn or a p-channel MISFET Qp
The semiconductor integrated circuit may be constituted by the FET. Further, in this embodiment, a MISFET is illustrated, but a semiconductor integrated circuit may be formed using an element having another transistor structure such as a bipolar transistor or a Bi-CMISFET.

An element isolation region 2 is formed in the vicinity of the main surface of semiconductor substrate 1, and an active region surrounded by element isolation region 2 contains a low concentration of p-type impurities (for example, boron (B)). The introduced p-type well 3 and the n-type well 4 into which n-type impurities (for example, phosphorus (P) and arsenic (As)) are introduced at a low concentration are formed. n-channel MISFE
TQn is provided on the main surface of the active region of the p-type well 3 by a p-channel M
ISFET Qp is formed on the main surface of the active region of n-type well 4. Element isolation region 2 is formed in a shallow groove on the main surface of semiconductor substrate 1 and is made of, for example, a silicon oxide film.
In the first embodiment, a semiconductor substrate is exemplified as the semiconductor substrate 1. However, an SOI substrate having a single-crystal semiconductor layer on the surface or a glass substrate having a polycrystalline silicon film on the surface may be used. Good.

The n-channel MISFET Qn has a gate electrode 6 formed on the main surface of the p-type well 3 via a gate insulating film 5 and an impurity semiconductor formed on the main surface of the semiconductor substrate 1 on both sides of the gate electrode 6. And a region 7. The p-channel MISFET Qp includes a gate electrode 6 formed on the main surface of the n-type well 4 via the gate insulating film 5 and an impurity semiconductor region formed on the main surface of the semiconductor substrate 1 on both sides of the gate electrode 6. 8 is provided.

The gate insulating film 5 is made of a silicon oxide film having a thickness of several nm and can be formed by, for example, a thermal CVD method. The gate electrode 6 is made of, for example, a low-resistance polycrystalline silicon film, and a silicide layer such as tungsten (W) or cobalt (CO) or a barrier metal such as titanium nitride (TiN) or tungsten nitride (WN) is formed thereon. A low resistance may be achieved by forming a metal layer of tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or the like.

The impurity semiconductor regions 7 and 8 have an n-channel M
It functions as the source / drain region of the ISFET Qn and the p-channel MISFET Qp. An n-type impurity (eg, phosphorus or arsenic) is introduced into impurity semiconductor region 7, and a p-type impurity (eg, boron) is introduced into impurity semiconductor region 8. The impurity semiconductor regions 7 and 8
A so-called LDD (Lightly Doped Drain) comprising a low-concentration impurity semiconductor region in which impurities are introduced at a low concentration and a high-concentration impurity semiconductor region in which impurities are introduced at a high concentration.
It may have a structure. Further, the upper portion of the impurity semiconductor regions 7,8, tungsten silicide (WSi _x), molybdenum silicide (MoSi _x), titanium silicide (T
i Si _x), a refractory metal silicide film such as tantalum silicide (TaSi _x) may be formed.

A side wall spacer 9 and a cap insulating film 10 are formed on the side and upper surfaces of the gate electrode 6, respectively. The sidewall spacer 9 and the cap insulating film 10 can be, for example, a silicon oxide film or a silicon nitride film. When a silicon nitride film is used, the side wall spacer 9 and the cap insulating film 10 made of the silicon nitride film are used. A connection hole can be opened in a self-aligned manner in an interlayer insulating film described later by using the mask as a mask.

Semiconductor substrate 1, n-channel MISFET Q
An interlayer insulating film 11 is formed on the upper surfaces of the n and p channel MISFETs Qp. B as the interlayer insulating film 11
PSG (Boro-Phospho-Silicate Glass) membrane or PS
G (Phospho-Silicate Glass)
Although a reflow film such as a film can be used, a silicon oxide film and SOG (SpinOn) formed by CVD or sputtering below or above the interlayer insulating film 11 can be used.
Glass) film.

Interlayer insulating film 1 on impurity semiconductor regions 7 and 8
1 is provided with a connection hole 12, and the connection hole 12 has a tungsten film 13 formed by, for example, a sputtering method.
a and a plug 13 made of, for example, a tungsten film 13b formed by a blanket CVD method or a selective CVD method.

On the upper layer of the interlayer insulating film 11, a first layer wiring M
1 is formed on the wiring forming insulating film 14. Further, a wiring groove 15 is formed in the wiring forming insulating film 14, and a first layer wiring M <b> 1 is formed in the wiring groove 15. The wiring forming insulating film 14 can be, for example, a silicon oxide film formed by a CVD method.

The first layer wiring M1 includes a barrier layer 16a made of, for example, titanium nitride (TiN) and a copper (C)
u) of the main conductive layer 16b. As described above, since the material such as copper having a small resistivity is used for the main conductive layer 16b, the resistance value of the first layer wiring M1 can be reduced, the wiring resistance between the integrated circuit elements is reduced, and the circuit delay time is reduced. The response speed of the semiconductor device can be improved to improve its performance.

The barrier layer 16a is made of tantalum (Ta) or tungsten nitride (W) instead of titanium nitride.
N), tantalum nitride (TaN), tantalum oxide (Ta
O) and silicon oxynitride (SiON). In addition, aluminum (Al) and tungsten (W) can be used for the main conductive layer 16b instead of copper. The barrier layer 16a has a function of preventing diffusion of a metal element constituting the main conductive layer 16b, securing insulation between wirings, and maintaining high performance and reliability of the semiconductor device.

First-layer wiring M1 and wiring-forming insulating film 1
An interlayer insulating film 17 for insulating between the first layer wiring M1 and a second layer wiring M2 to be described later is formed in the upper layer of the fourth layer. The interlayer insulating film 17 can be configured in the same manner as the interlayer insulating film 11, but since the interlayer insulating film 17 is formed in a state where the main conductive layer 16b made of copper having poor heat resistance has already been formed, the BPSG film is formed. Alternatively, it is not preferable to use a reflow film such as a PSG film, and it is preferable to use a silicon oxide film formed by a CVD method or a sputtering method or a stacked film of a silicon oxide film and an SOG film. SO
By using the G film, this SOG film functions as a flattening layer, and the surface of the interlayer insulating film 17 can be made uneven. This can prevent the unpolished portion when the plugs and the like formed in the interlayer insulating film 17 are formed by polishing by the CMP method, thereby improving the insulation between the wirings.

A connection hole 18 is formed in the interlayer insulating film 17, and a plug 19 similar to the plug 13 is formed in the connection hole 18. That is, plug 19 is formed of a tungsten film 19a formed by, for example, a sputtering method and a tungsten film 19b formed by, for example, a blanket CVD method or a selective CVD method.

On the interlayer insulating film 17, a wiring forming insulating film 20 for forming the second layer wiring M2 is formed. Further, a wiring groove 21 is formed in the wiring forming insulating film 20, and a second layer wiring M2 is formed in the wiring groove 21. The second layer wiring M2 includes a barrier layer 22a and a main conductive layer 22b, like the first layer wiring M1. For other configurations of the wiring forming insulating film 20, the wiring groove 21, and the second layer wiring M2, the wiring forming insulating film 14, the wiring groove 1
5, since it is the same as the first layer wiring M1, the description is omitted.

Here, the semiconductor device of the present embodiment will be described with reference to the second layer wiring M2. However, similarly, a third or higher wiring layer is formed to obtain a multilayer semiconductor device. It goes without saying that it can be done.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 2 to 17 are cross-sectional views or plan views illustrating an example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps.

Firstly, p ^- and a semiconductor substrate 1 made of the form of single crystal silicon, patterning the photoresist film having an opening in a region where the element isolation region 2 is formed, to form a shallow trench in the semiconductor substrate 1 . Next, the photoresist film is removed, a silicon oxide film filling the shallow groove is deposited on the entire surface of the semiconductor substrate 1, and this silicon oxide film is
Polishing by the method. As a result, the silicon oxide film on the semiconductor substrate 1 in a region other than the shallow groove is removed, and an element isolation region 2 is formed in the shallow groove.

Next, a photoresist film having an opening in a region where the p-type well 3 is to be formed is patterned, and using this photoresist film as a mask, an impurity such as boron is ion-implanted into a p-type conductivity type. I do. After removing the photoresist film, a photoresist film having an opening in a region where the n-type well 4 is to be formed is patterned, and using this photoresist film as a mask, an impurity for forming an n-type conductivity type, for example, phosphorus. Is ion-implanted. Further, after removing the photoresist film, a heat treatment is performed on the semiconductor substrate 1 to activate the impurities, thereby forming a p-type well 3 and an n-type well 4 (FIG. 2).

Next, a silicon oxide film serving as a gate insulating film 5, a polycrystalline silicon film serving as a gate electrode 6, and a silicon oxide film serving as a cap insulating film 10 are sequentially deposited on the main surface of the semiconductor substrate 1 to form a laminated film. Is formed, and the laminated film is etched using a photoresist film patterned by photolithography as a mask to form a gate insulating film 5, a gate electrode 6, and a cap insulating film 10 (FIG. 3). The gate insulating film 5 can be deposited by, for example, a thermal CVD method, and the gate electrode 6 can be formed by a CVD method. However, in order to reduce the resistance value, an n-type impurity (for example, P) is doped. Is also good. Tungsten silicide on top of the gate electrode 6 (WSi _x),
Molybdenum silicide (MoSi _x), titanium silicide (TiSi _x), tantalum silicide (TaSi _x)
Or a high melting point metal silicide film such as tungsten (W) or molybdenum (M) through a barrier layer such as titanium nitride (TiN) or tungsten nitride (WN).
o), a metal layer such as titanium (Ti) or tantalum (Ta) may be formed. The cap insulating film 10 is formed, for example, by CVD.
It can be deposited by a method.

Next, a photoresist film having an opening in a region where the n-channel MISFET Qn is to be formed is patterned, and using this photoresist film and the cap insulating film 10 as a mask, an n-type conductive impurity such as phosphorus is ionized. Implantation is performed to form the impurity semiconductor region 7 in a self-aligned manner with respect to the gate electrode 6. After removing the photoresist film, a photoresist film having an opening in a region where the p-channel MISFET Qp is formed is patterned,
Using the photoresist film and the cap insulating film 10 as a mask, a p-type impurity such as boron is ion-implanted to form an impurity semiconductor region 8 in a self-aligned manner with respect to the gate electrode 6. Further, the CVD is performed on the semiconductor substrate 1.
After depositing a silicon oxide film by the method, the silicon oxide film is anisotropically etched by a reactive ion etching (RIE) method to form a sidewall spacer 9 on the side wall of the gate electrode 6 (FIG. 4). Furthermore, impurities corresponding to the conductivity type are ion-implanted into the impurity semiconductor region 7 or the impurity semiconductor region 8 at a high concentration using the photoresist film, the cap insulating film 10 and the sidewall spacers 9 as a mask, thereby forming a so-called LDD-structure impurity. A semiconductor region may be formed. At this stage, a tungsten or cobalt silicide film may be formed on the surfaces of the impurity semiconductor regions 7 and 8 to reduce the sheet resistance of the impurity semiconductor regions 7 and 8 and the contact resistance with the plug 13. .

Next, a silicon oxide film is deposited on the semiconductor substrate 1 by a sputtering method or a CVD method to form an interlayer insulating film 11. The surface of the interlayer insulating film 11 can be planarized by using the CMP method. Further, a connection hole 12 is formed in the interlayer insulating film 11 on the impurity semiconductor regions 7 and 8 on the main surface of the semiconductor substrate 1 by using a photolithography technique and an etching technique (FIG. 5).

Next, the tungsten film 1 is formed by sputtering.
3a, and a tungsten film 13b is further deposited by blanket CVD (FIG. 6).

Next, the tungsten film 13b and the tungsten film 13a on the interlayer insulating film 11 other than the connection holes 12 are removed by the CMP method to form the plug 13 (FIG. 7).

Next, an insulating film 14 for forming a wiring is deposited on the interlayer insulating film 11 and the plug 13. The wiring forming insulating film 14 is formed to form the first layer wiring M1 by a CMP method, and may be a silicon oxide film formed by, for example, a CVD method or a sputtering method. The thickness of the wiring forming insulating film 14 is, for example, 0.5 μm.
Alternatively, it can be slightly thicker.

Next, a photoresist film having an opening in a region where the first layer wiring M1 is formed is formed, and the wiring forming insulating film 14 is etched using the photoresist film as a mask to form a wiring groove 15. (FIG. 8).

Next, a titanium nitride film 23 serving as a barrier layer 16a is deposited on the surface of the wiring forming insulating film 14 including the inside of the wiring groove 15 (FIG. 9). The titanium nitride film 23 can be deposited by, for example, a CVD method or a sputtering method. The deposition of the titanium nitride film 23 is performed for improving the adhesion of the copper film and preventing the diffusion of copper, which will be described later. Note that a metal film such as tantalum or a tantalum nitride film may be used instead of the titanium nitride film. It is also possible to sputter-etch the surface of the titanium nitride film 23 immediately before the next step of depositing the copper film. By such sputter etching, water adsorbed on the surface of the titanium nitride film 23,
Oxygen molecules and the like can be removed, and the adhesiveness of the copper film can be improved.

Next, a metal to be the main conductive layer 16b, for example, a copper film 24 is deposited by a sputtering method (FIG. 10). As an example of the conditions for depositing the copper film 24 by the sputtering method, the reaction pressure can be set to 0.2 mTorr or less, and the distance from the copper target to the substrate can be set to 20 cm or more. By using the sputtering method as described above, CVD
High quality copper film is stably formed using technically stable process without employing complicated process such as deposition method and plating process, or process that may cause problems in film quality such as conductivity. be able to. Since the step coverage of the copper film 24 deposited by the sputtering method is not good, the copper film 24 is not completely buried in the wiring groove 15 at this stage.

Next, a heat treatment is performed on the semiconductor substrate 1 to reflow the copper film 24 to form a copper film 25 completely embedded in the wiring groove 15 (FIG. 11). Examples of the heat treatment conditions include heating at 450 ° C. for 5 minutes under a reduced pressure of about 20 Torr in an inert gas or hydrogen atmosphere.

Next, a stopper film 26 is formed on the surface of the copper film 25 (FIG. 12), and the extra stopper film 26, copper film 25 and titanium nitride film 23 on the wiring forming insulating film 14 are removed. A first layer including a conductive layer 16b and a barrier layer 16a;
The layer wiring M1 is formed (FIG. 13). The CMP method is used to remove the stopper film 26, the copper film 25, and the titanium nitride film 23. Further, since the stopper film 26 is formed during the polishing by the CMP method, erosion of the wiring forming insulating film 14 and the first layer wiring M1 can be suppressed. This will be described with reference to FIG.

FIGS. 14A to 14C show the first layer wiring M1.
FIG. 14 shows a partial cross section of a region where the wiring density is high (dense).
(D) to (f) show partial cross sections of a region where the wiring density of the first layer wiring M1 is low (sparse). The surface shape of the copper film 25 before polishing by the CMP method is the same as that of the wiring-forming insulating film 14.
The unevenness is formed according to the wiring groove 15. Since the stopper film 26 has a relatively small thickness, it is formed along the surface shape of the copper film 25 (FIG. 1).
4 (a) and (d)).

The stopper film 26 is made of a material whose polishing rate by the CMP method is lower than that of the copper film 25. For example, a titanium (Ti) film, a tantalum (Ta) film,
Tungsten (W) film, tungsten nitride (WN) film,
It is selected from a tantalum nitride (TaN) film. Although the stopper film 26 can be formed by a sputtering method, it may be formed by a CVD method. In addition, when the polishing rate by a general CMP method is exemplified, a copper film is 130 nm / min, and a titanium nitride film is 10 nm / min.
While it is 0 nm / min, the titanium film and the tantalum film are as low as 40 nm / min and 30 nm / min, respectively.

Since the stopper film 26 is formed with a uniform film thickness over the entire surface of the substrate, a region where the wiring density is high (FIG. 14)
The amount of the stopper film 26 to be polished by the CMP method differs between (a)) and the region where the wiring density is low (FIG. 14 (d)). That is, in a region where the wiring density is high, the amount of the stopper film 26 to be polished is increased by an amount corresponding to the side wall of the concave portion. On the other hand, in a region where the wiring density is low, the amount of the copper film 25 to be polished by the CMP method increases. Therefore, if the stopper film 26 is formed so that the sum of the polishing amounts of the copper film 25 and the stopper film 26 substantially matches the polishing rate in an arbitrary region of the semiconductor substrate 1, the polishing by the CMP method is completed. Therefore, even if the wiring density is large or small, it is possible to achieve just etch in each region almost simultaneously.

FIG. 14B shows this situation.
(C), (e), and (f). In the region where the wiring density is high during the polishing (FIG. 14B), the amount of the copper film 25 to be polished is small but the amount of the stopper film 26 is large.
In the region where the wiring density is low (FIG. 14E), since the amount of the copper film 25 to be polished is large but the amount of the stopper film 26 is small, the polishing is performed by almost the same amount, and the polishing of both ends. The just-etch condition is achieved almost simultaneously (FIG. 1
4 (c) and (f)).

FIG. 15 shows an example of a region where the wiring density is high (FIG. 15 (a)) and a region where the wiring density is low (FIG. 15 (b)). FIGS. 14A to 14C show cross sections taken along line -A, and FIG.
FIGS. 14D to 14F show cross sections taken along line -B.

The thickness of the stopper film 26 depends on the polishing rate ratio R (R = polishing rate V2 of the copper film 25 / stopper) to the polishing amount K2 of the copper film 25 and the polishing amount K3 of the stopper film 26. The sum of the values multiplied by the polishing rate V3 of the film 26 (K2 +
K3.R) can be formed to be substantially equal in any region. Alternatively, as shown in FIG.
The volume W of the concave portion of the copper film 25 due to the shape of the wiring groove 15
And the volume W3 of the stopper film 26 formed on the side wall of the concave portion.
And a value W3 · R obtained by multiplying the above by the polishing rate ratio R are substantially equal to each other.

Since the stopper film 26 is formed, the insufficient polishing amount of the copper film 25 is compensated by the stopper film 26, and the stopper film 2 is uniformly formed over the entire surface of the semiconductor substrate 1.
6 and the copper film 25 can be polished to suppress erosion caused by a difference in wiring density. As a result, the thickness (cross-sectional area) of the first layer wiring M1 of the semiconductor device can be formed as designed, and the reliability and yield can be improved.

A barrier film for suppressing the reaction can be formed at the interface between the copper film 25 and the stopper film 26. An example of the barrier film is a titanium nitride film. The barrier film can be formed by a sputtering method or a CVD method.

As a polishing agent used for polishing by the CMP method, a general polishing agent for polishing copper can be used, and it is not necessary to use a polishing agent which particularly improves polishing characteristics. For example, hydrogen peroxide and benzotriazole (BTA) can be used for QCTT1010 manufactured by Rodale.

If the stopper film (barrier film) on the upper surface of the projection is removed by metal dry etching of the stopper film before performing the CMP, the CMP time is shortened, and the characteristics are improved in the measures against erosion and dishing.

Next, an interlayer insulating film 17 is formed in the same manner as the interlayer insulating film 11, and a plug 19 composed of a tungsten film 19a and a tungsten film 19b is formed in the connection hole 18 as in the case of the plug 13 (FIG. 16).

Further, similarly to the wiring forming insulating film 14,
Wiring forming insulating film 20 for forming second layer wiring M2
Is formed, and the wiring groove 21 is formed in the same manner as the wiring groove 15.
Further, as in the case of the first layer wiring M1, the second layer wiring M
Forming a titanium nitride film 27 to be the second barrier layer 22a;
After the copper film is deposited, the copper film is reflowed to form a copper film 28 to be the main conductive layer 22b of the second-layer wiring M2. Further, a stopper film 29 is formed on the copper film 28 (FIG. 17).

Thereafter, as in the case of the first layer wiring M1,
Stopper film 29, copper film 28 and titanium nitride film 27
The barrier layer 22a and the main conductive layer 22b are removed by the MP method.
Are formed, and the semiconductor device shown in FIG. 1 is almost completed. At this time, needless to say, the same effect as the stopper film 26 in the case where the stopper film 29 is the first layer wiring M1 is obtained.

According to the method of manufacturing a semiconductor device of the present embodiment, erosion on wiring can be suppressed, and the reliability and yield of the semiconductor device can be improved.

(Embodiment 2) FIG. 18 and FIG.
FIG. 14 is a cross-sectional view showing the method for manufacturing the semiconductor device of the second embodiment. In the manufacturing method according to the second embodiment, the stopper film 26 in the first embodiment is replaced with a sacrificial film 30. Therefore, description of other steps and configurations similar to those of the first embodiment will be omitted.

The manufacturing method of the second embodiment is the same as the steps up to FIG. 11 in the first embodiment. Thereafter, as shown in FIG. 18, a sacrificial film 30 is formed on the copper film 25. The sacrificial film 30 is made of a material having a polishing rate substantially the same as that of the copper film 25 by the CMP method, and its surface is planarized in an as-deposited state. For example,
Copper film formed by plating method or SOG (Spin On
Glass) film can be exemplified. The plating method may be either electroless plating or electrolytic plating.

Thus, the surface is flattened in the as-deposited state,
Further, by forming the sacrificial film 30 having a polishing rate equivalent to that of the copper film 25 by the CMP method, the sacrificial film 30 and the copper film 25 can be polished flat without depending on the wiring density.
Erosion of the layer wiring M1 can be prevented. Thereby, the reliability and the yield of the semiconductor device can be improved.

The subsequent steps are the same as in the first embodiment.

FIG. 19 shows how the sacrificial film 30 and the copper film 25 are polished in the case of the present embodiment. FIG.
(A) to (c) show partial cross sections of a region where the wiring density of the first layer wiring M1 is large (dense), and FIGS.
A partial cross section of a region where the wiring density of the first layer wiring M1 is small (sparse) is shown. Since the sacrificial film 30 is formed by flattening, the surface thereof is flat even if the wiring density is different (FIGS. 19A and 19D). The CMP of the sacrificial film 30
Since the polishing rate by the method is equal to the polishing rate of the copper film 25, the same polishing amount is obtained regardless of the wiring density even during the polishing (FIGS. 19B and 19E). Therefore, even if the wiring density is large or small, the just etch in each region can be achieved almost at the same time, and the just etch state in which the polishing of both is completed is achieved almost at the same time (FIG. 19). (C) and (f)).

(Third Embodiment) FIGS. 20 to 23 are sectional views showing a method of manufacturing a semiconductor device according to a third embodiment in the order of steps. The manufacturing method according to the third embodiment corresponds to the manufacturing method according to the first embodiment.
However, an example in which the stopper film 26 is left at the end of the polishing by the CMP method is shown.

When the stopper film 26 is formed of an insulating film, there is no problem even if the stopper film 26 is left. However, when the stopper film 26 is formed of a conductive metal film as in the first embodiment. If all of these are not removed, there is a problem that the wiring is short-circuited. Therefore, in the case of the first embodiment, it is a rule that the stopper film 26 is entirely removed.

However, as shown in FIG. 20, the copper film 31 is deposited thinner than the copper film 24 in the first embodiment, and is reflowed as shown in FIG.
The reflowed copper film 32 can be formed at an altitude lower than the upper surface of the substrate. In FIG. 21, the height difference between the upper surface of the copper film 32 and the upper surface of the wiring groove 15 is shown as d.

A stopper film 33 similar to that of the first embodiment is deposited on such a copper film 32 (FIG. 22).
When the polishing is performed by the CMP method in the same manner as described above, the stopper film 33 can be partially left on the upper surface of the first layer wiring M1 as shown in FIG.

As described above, by leaving the stopper film 33 partially on the upper surface of the first layer wiring M1, dishing can be prevented in addition to the effect of suppressing erosion described in the first embodiment. . That is, the polishing rate of the stopper film 33 by the CMP method is lower than that of the copper film 32 as described above, so that excessive polishing of the copper film 32 can be prevented. As a result of preventing the copper film 32 from being excessively polished, total dishing can be suppressed, and the cross-sectional area of the first layer wiring can be made closer to the design value. Thereby, the reliability and the yield of the semiconductor device can be improved.

The subsequent steps are the same as in the first embodiment, and can be applied to the case of the second-layer wiring M2.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, the case where the present invention is applied to the first-layer wiring M1 or the second-layer wiring M2 has been described. However, it is needless to say that the present invention can be applied to an upper wiring layer.

The present invention is applicable not only to wiring but also to a case where another conductive member such as a plug is embedded in a connection hole or the like and formed by a CMP method.

The present invention can be applied to other than the formation of a conductive member such as a wiring or a plug. In other words, when an uneven shape is formed on the surface to be processed due to the uneven shape of the base, the surface to be processed is not affected by the density of the unevenness.
The present invention can be applied to the case where the planarization is performed by the MP method.

[0093]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) It is possible to provide a technique for suppressing erosion or dishing without improving a polishing agent when forming a wiring or a plug by the CMP method.

(2) The thickness of a conductive member such as a wiring or a plug formed by the CMP method can be made close to a designed value. Thereby, the resistance value of the wiring and the like can be made closer to the design resistance value, and the reliability and yield of the semiconductor device can be improved.

(3) Irregularities on the surface of the thin film caused by irregularities in the underlayer can be flattened by the CMP method without depending on the wiring density of the underlayer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating an example of a method for manufacturing the semiconductor device of the first embodiment in the order of steps.

FIG. 3 is a sectional view illustrating an example of a method for manufacturing the semiconductor device of the first embodiment in the order of steps.

FIG. 4 is a cross-sectional view showing an example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 5 is a sectional view illustrating an example of a method for manufacturing the semiconductor device of the first embodiment in the order of steps.

FIG. 6 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device of the first embodiment in the order of steps.

FIG. 7 is a cross-sectional view showing one example of the method of manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 8 is a cross-sectional view showing one example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 9 is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device of First Embodiment in the order of steps;

FIG. 10 is a sectional view illustrating an example of the method of manufacturing the semiconductor device of the first embodiment in the order of steps.

FIG. 11 is a sectional view illustrating an example of a method of manufacturing the semiconductor device of First Embodiment in the order of steps.

FIG. 12 is a sectional view illustrating an example of the method of manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 13 is a cross-sectional view showing one example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 14 is a cross-sectional view showing one example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 15 is a plan view showing one example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 16 is a cross-sectional view showing one example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 17 is a sectional view illustrating an example of the method of manufacturing the semiconductor device of the first embodiment in the order of steps.

FIG. 18 is a sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment.

FIG. 19 is a cross-sectional view showing the method for manufacturing the semiconductor device of the second embodiment.

FIG. 20 is a sectional view illustrating the method of manufacturing the semiconductor device of the third embodiment in the order of steps;

FIG. 21 is a sectional view illustrating the method of manufacturing the semiconductor device of the third embodiment in the order of steps;

FIG. 22 is a sectional view illustrating the method of manufacturing the semiconductor device of the third embodiment in the order of steps;

FIG. 23 is a sectional view illustrating the method of manufacturing the semiconductor device of the third embodiment in the order of steps;

FIG. 24 is a cross-sectional view for explaining erosion and dishing.

FIG. 25 is a conceptual cross-sectional view for explaining an erosion generation mechanism.

FIG. 26 is a graph showing experimental results examined by the present inventors.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation region 3 p-type well 4 n-type well 5 gate insulating film 6 gate electrode 7, 8 impurity semiconductor region 9 sidewall spacer 10 cap insulating film 11, 17 interlayer insulating film 12, 18 connection hole 13, 19 Plugs 13a, 13b, 19a, 19b Tungsten film 14, 20 Wiring forming insulating film 15, 21 Wiring groove 16a, 22a Barrier layer 16b, 22b Main conductive layer 23, 27 Titanium nitride film 24, 25, 28, 31, 32 Copper Films 26, 29, 33 stopper film 30 sacrificial film 100 insulating film 101 wiring groove 102 wiring 103 erosion 104 dishing 105 total dishing M1 first layer wiring M2 second layer wiring Qn n-channel MISFET Qp p-channel MISFET

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naofumi Ohashi 6-16-16, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Hiji Yamaguchi 6-16, Shinmachi, Ome-shi, Tokyo (2) Inventor Seiichi Kondo 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo F-term (reference) 5F033 AA02 AA04 AA19 AA23 AA66 BA15 BA17 BA25 BA41 EA05 EA25

Claims (10)

[Claims] 1. A substrate made of a semiconductor having a circuit element formed on a main surface thereof or a substrate having a semiconductor layer, and a film formed on any film layer on the main surface of the substrate, A method of manufacturing a semiconductor device, comprising: a first film having an uneven shape; and an embedding member formed by embedding in a concave portion of the first film, or a planarization layer that covers the first film and has a planarized surface. A first step of forming a second coating to be the embedded member or the flattening layer on the first coating; and a third step having a lower polishing rate by a CMP method than the second coating on the second coating.
A method of manufacturing a semiconductor device, comprising: a second step of depositing a film; and a third step of polishing the third film and the second film by a CMP method to form the embedded member or the planarization layer. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the third coating is a polishing amount (K2) of the second coating and a polishing amount (K3) of the third coating.
) Is multiplied by the ratio (R = V2 / V3) of the polishing rate (V2) of the second coating to the polishing rate (V3) of the third coating (K3.R), and the sum (K2 + K3.R) is: A first condition that is substantially equal in an arbitrary region of the substrate, or a volume W of a concave portion of the second film caused by the uneven shape of the first film, and the third film formed on a side wall of the concave portion. The ratio (R = V2 / V3) of the polishing rate (V2) of the second coating to the polishing rate (V3) of the third coating in the volume W3 of
) Is substantially equal to the value (W3 · R)
A method for manufacturing a semiconductor device, characterized by being formed under any one of the following conditions: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first coating is an insulating film, a concave portion of the first coating is a wiring groove or a connection hole, and the second coating is Is a copper film containing copper or a copper alloy as a main component, the embedded member is a wiring or a plug made of the metal film, and the third film is a titanium film, a tantalum film, a tungsten film, a tungsten nitride film, a tantalum nitride film. A method for manufacturing a semiconductor device, comprising a metal film selected from films. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a barrier film for suppressing a reaction between the copper film and the metal film is formed at an interface between the copper film and the metal film. Manufacturing method of a semiconductor device. 5. A substrate made of a semiconductor having a circuit element formed on a main surface thereof or a substrate having a semiconductor layer, and a film formed on any film layer on the main surface of the substrate, A method for manufacturing a semiconductor device, comprising: a first coating having an uneven shape; and an embedding member formed by being embedded in a concave portion of the first coating, or a planarization layer that covers the first coating and has a planarized surface. A first step of forming a second coating serving as the embedding member or a planarizing layer on the first coating; and forming a C on the second coating.
A second step of forming a third coating having a polishing rate substantially equal to that of the second coating by the MP method and having a flat surface after formation; and polishing the third coating and the second coating by a CMP method. Forming a buried member or a planarization layer by using the method described above. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the first film is an insulating film, the second film is a copper film containing copper or a copper alloy as a main component, A method of manufacturing a semiconductor device, wherein the third film is a copper film or a SOG film containing copper or a copper alloy as a main component formed by a plating method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the third film is entirely removed by polishing the third film and the second film by a CMP method. The first method, or
A method of manufacturing a semiconductor device, comprising: any one of the second methods of leaving the third coating in the concave portion of the first coating. 8. A substrate having a semiconductor element or a semiconductor layer having a circuit element formed on a main surface thereof, and a wiring groove or a connection hole formed on any layer on the main surface of the substrate. A semiconductor device comprising: an insulating film; and a wiring or a plug formed by being embedded in the wiring groove or the connection hole, wherein a surface of the insulating film on which the wiring or the plug is formed is planarized by a CMP method. A coating made of a material having a polishing rate smaller than the polishing rate of the metal material forming the wiring or plug by a CMP method is embedded in the wiring groove or connection hole together with the wiring or plug on the wiring or plug. A semiconductor device characterized by being formed. 9. The semiconductor device according to claim 8, wherein the wiring or the plug is made of a copper film containing copper or a copper alloy as a main component, and the coating is a titanium film, a tantalum film,
A semiconductor device comprising any one of a metal film selected from a tungsten film, a tungsten nitride film, and a tantalum nitride film. 10. The semiconductor device according to claim 9, wherein a barrier film for suppressing a reaction between the copper film and the metal film is formed at an interface between the copper film and the metal film. Semiconductor device.