JP2000059999A - System linkage inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter whose operation is securely discontinued at the time of a single operation while the power supply abnormality, etc., of a system which normally occurs at the time of system linkage is not mistakenly detected as a single operation. SOLUTION: An output voltage detecting means 27 which detects the output voltage of an inverter means 26, a zero voltage phase synchronization signal means 28 which outputs a signal synchronized with the zero point voltage phase of the output voltage of the inverter means 26, and a control means 29 which controls the zero point of the output current of the inverter means so as to be outputted with a certain phase angle from the zero point of the output voltage and, if the frequency of the output voltage of the inverter means 26 exceeds an allowable value, discontinues the operation of the inverter means 26, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the prevention of isolated operation in a grid-connected inverter for converting an input power supply into a specification suitable for a system power supply and supplying power to the system.

[0002]

2. Description of the Related Art An example of a conventional grid-connected inverter will be described with reference to a block diagram of FIG.

[0003] The system interconnection inverter 1 converts the voltage of the DC power supply 2 to 100 V and the frequency of 60 Hz so as to conform to the power supply specification of the system 3 and supplies power to the system.
Reference numeral 4 denotes a load connected to the system, and reference numeral 5 denotes a switch for separating the system 3 from the system interconnection inverter 1. The system interconnection inverter 1 includes inverter means 6, output current detection means 7, zero current phase synchronization signal means 8, output voltage detection means 9, zero voltage phase synchronization signal means 10, and control means 11. The inverter means 6 converts the DC power supply 2 into an AC power supply and supplies power to the system 3. The output current detection means 7 detects the output current of the inverter means 6 and outputs a detection signal to the zero current phase synchronization signal means 8.
To enter. The zero current phase synchronizing signal means 8 outputs a signal synchronized with the zero point current phase of the output current of the inverter means 6. The output voltage detecting means 9 detects the output voltage of the inverter means 6 and inputs a detection signal to the zero voltage phase synchronization signal means 10. The zero voltage phase synchronization signal means 10 outputs a signal synchronized with the zero voltage phase of the output voltage of the inverter means 6. The control means 11 inputs the outputs of the zero current phase synchronization signal means 8 and the zero voltage phase synchronization signal means 10 and controls the inverter means 6.

[0004] The operation of the control means 11 will be described with reference to the flowchart of FIG. In step 1, control means 11
Inputs the outputs of the zero current phase synchronizing signal means 8 and the zero voltage phase synchronizing signal means 10 and detects the zero point of the output current and output voltage of the inverter means 6. In step 2, the phase difference between the zero point of the output current and the output voltage is determined, and it is determined whether or not the phase difference deviates from a normal value when the system is linked to the system. If it is within the normal value range, the process proceeds to step 3 and the operation of the inverter means 6 is continued, and the process returns to step 1. Conversely, if it exceeds the range of the normal value, the process proceeds to step 4. Step 4
Then, the operation of the inverter means 6 is stopped, and the routine proceeds to step 5. In step 5, after a certain period of time after stopping the inverter means 6, automatic return is performed, and the process returns to step 1 to repeat the above operations.

The normal value range described in step 2 will be described with reference to FIGS. 12 (b) and 12 (c). FIG.
As shown in (b), the control means 11 is connected to the inverter means 6.
The inverter means 6 is controlled such that the output current i is output at a constant leading phase with respect to the output voltage V. That is, in FIG. 12C in which the portion A in FIG. 12B is enlarged, when the system is connected, the output current i of the inverter means 6 is in a hatched portion, and this is set to a normal value range. Here, in the case of the single operation, the output current i of the inverter means 6 moves to a position determined by the phase characteristic of the load 4. In the case of FIG. 12C, the load 4 is capacitive. As described above, when the value exceeds the normal value range, the control means 11 determines that the operation is the islanding operation.

[0006]

However, in the conventional grid-connected inverter, the voltage phase of the grid 3 suddenly changes.
A phase change between the output current i and the output voltage V of the inverter means 6 occurs due to a power supply abnormality such as frequency fluctuation or power supply distortion, or a sudden change in the output of the DC power supply 2. There was a problem that would stop.

The phase characteristic of the load 4 may fall within a normal range, for example, the range of the dead zone for detecting the isolated operation is large, and the grid-connected inverter 1 keeps supplying power even during the isolated operation, and There is a possibility that an electric shock accident may occur when an electric worker or the like who recognizes that a power failure has occurred due to opening of the container 5 or the like touches.

Further, both the output current i and the output voltage V of the inverter means 6 are detected, and further, respective zero point synchronizing signals are required. Therefore, the circuit configuration is complicated, the cost is increased, and the space on the board is taken up. was there.

[0009]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the conventional configuration, and it is possible to erroneously detect an isolated operation when a grid-connected inverter is grid-connected. When the system-connected inverter is disconnected from the system, the system-connected inverter can be stopped reliably, and the system-connected inverter can be reduced in cost and space can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is an inverter for converting an input power supply into an AC power supply and outputting it to a system, an output voltage detection means for detecting an output voltage of the inverter means, Input the output signal of the detection means,
Zero voltage phase synchronization signal means for outputting a signal synchronized with the zero voltage phase of the output voltage of the inverter means, and the output of the zero voltage phase synchronization signal means is input, and the zero point of the output current of the inverter means is calculated from the zero point of the output voltage. Control means for controlling the inverter means to output at a fixed phase angle, measuring the frequency of the output voltage of the inverter means, and stopping the inverter means when the measured frequency exceeds an allowable value. By setting the allowable value of the frequency to a place that is greatly deviated from the frequency range that can be considered in the system, the inverter means can be reliably stopped during the isolated operation without erroneous detection of the isolated operation during system interconnection. This is a simple grid-connected inverter.

According to a second aspect of the present invention, there is provided a band-pass filter which receives an output of an output voltage detecting means and outputs an output signal to a zero voltage phase synchronizing signal means, and at least a frequency of an output voltage of the inverter means has an allowable value. The system is equipped with phase correction means for correcting the phase shift due to the frequency characteristics of the band-pass filter to the zero-voltage phase synchronization signal means until the power supply exceeds the frequency limit. In addition to removing the frequency components other than the vicinity of the frequency and correcting the phase shift due to the frequency characteristics of the band-pass filter by the phase correction means, the zero point detection accuracy and the frequency accuracy of the zero voltage phase synchronization signal means are improved,
A system-connected inverter that reliably stops the inverter means during the isolated operation without erroneously detecting the isolated operation during the system connection.

According to a third aspect of the present invention, there is provided a configuration including a correction amount setting means for arbitrarily setting a correction amount for phase correction by the phase correction means. It is a system interconnection inverter capable of changing the time at which the frequency of the output voltage of the means changes and changing the detection time.

According to a fourth aspect of the present invention, there is provided a configuration having a correction delay time setting means for setting a time for delaying the phase correction by the phase correction means. In this case, the time when the frequency of the output voltage changes is delayed, and the detection time has a degree of freedom.

According to a fifth aspect of the present invention, there are provided two band-pass filters, one for 50 Hz and the other for 60 Hz.
A system-interconnected inverter having a configuration provided with 50/60 Hz switching means for switching to a band-pass filter for z or 60 Hz, and having improved correction accuracy due to a phase shift of the band-pass filter when the system frequency is 50 Hz and 60 Hz. Things.

[0015]

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of this embodiment. Reference numeral 21 denotes a system interconnection inverter according to the present embodiment, which converts the DC power supply 22 so as to conform to the power supply specification of the system 23 such as a voltage of 100 V and a frequency of 60 Hz, and supplies power to the system 23. 24 is a load connected to the grid, 2
Reference numeral 5 denotes a switch such as a breaker for separating the system 23 from the system interconnection inverter 21. The system interconnection inverter 21 includes inverter means 26, output voltage detection means 27, zero voltage phase synchronization signal means 28, and control means 29. The inverter means 26 converts the DC power supply 22 into an AC power supply and
To supply power. The output voltage detection means 27 detects the output voltage of the inverter means 26 and inputs a detection signal to the zero voltage phase synchronization signal means 28. Zero voltage phase synchronization signal means 2
8 outputs a signal synchronized with the zero-point voltage phase of the output voltage of the inverter means 26. The control means 29 receives the output of the zero-voltage phase synchronization signal means 28 and controls the inverter means 26.

The operation of the control means 29 will be described with reference to the flowchart of FIG. In step 10, the control means 29 receives the output of the zero-voltage phase synchronization signal means 28 and detects the zero point of the output voltage of the inverter means 26. The control means 29 outputs a current such that the zero point of the current has a constant phase angle with respect to the detected zero point of the output voltage of the inverter means 26. In step 11, the control means 29 sets the zero-voltage phase synchronization signal means 2
8 and the output voltage frequency of the inverter means 26 is measured. Next, the routine proceeds to step 12. Step 12 the control unit 29 is a frequency measured in step 11 is determined greater than determination frequency f _H. If it is larger, the operation is determined to be the islanding operation, and the process proceeds to step S13. In step 13, the control means 29 stops the operation of the inverter means 26 and proceeds to step 14. Although the operation of the inverter means 26 is merely stopped in step 13, a switch may be inserted in series in a line connected to the load 24, and may be disconnected by the control means 29. In step 14, the control means 29 performs the operation of the inverter means 26 again after a predetermined time has elapsed, and returns automatically to step 10. Conversely, Step 1
2, the determination frequency measured in step 11 the frequency f _H
If smaller, go to step 15. Step 15 the control unit 29 is a frequency measured in step 11 is determined whether smaller determination frequency f _L. If it is smaller, it is determined that the operation is the islanding operation, and the process proceeds to steps 13 and 14. Conversely, when the frequency measured in step 11 is higher than the judgment frequency f _L in step 15, it is the time of system interconnection, and
Go to 0 and repeat the same operation.

Here, the operation in which the frequency changes during the single operation will be described. The control means 29 controls the zero point of the output current of the inverter means 26 so that the phase angle becomes a constant value θ with reference to the zero point of the output voltage at the time of system interconnection. During the isolated operation, the load phase angle φ with the zero point of the output current based on the zero point of the output voltage of the inverter means 26 is determined by the phase characteristic determined by the load 24. However, even in the single operation, the control means 29 outputs the output current of the inverter means 26 to control the output current of the inverter means 26 to a constant phase angle value θ in response to the signal of the zero-voltage phase synchronization signal means 28, so that the frequency is increased by the difference between θ and φ. Will change. For example, it is assumed that the control means 29 outputs the output current of the inverter means 26 at the phase angle θ ahead of the output voltage at the time of system interconnection. This is the control phase angle θ
And Here, when the phase angle φ of the load 24 is larger than θ, the load 24 tends to be more capacitive than the control phase angle θ, and each time the control unit 29 performs the operation of step 10, the frequency is increased by the difference between θ and φ. Lower.

The frequency of the system 23 at the time of system interconnection is 60 Hz
Then, the operation is performed independently, and the operation in step 10 is performed first. When the frequency is measured in step 11, the value is f1 = 1 / (1/60 Hz− (θ−φ) ° / 360 ° /
F2 = 1 / (1 / f1 Hz− (θ−φ) ° / 360 ° /
f1 Hz) and the frequency is rapidly lowered by repeating this. Conversely, when φ is smaller than θ, the load 24 tends to be more inductive than the control phase angle θ, and the frequency increases by the difference between θ and φ each time the control unit 29 performs the operation of step 10.

When the frequency of the system 23 at the time of system interconnection is 60 Hz
Then, the operation in step 10 is performed first after the isolated operation, and when the frequency is measured in step 11, the value is f1 = 1 / (1/60 Hz− (θ−φ) ° / 360 ° /
F2 = 1 / (1 / f1 Hz− (θ−φ) ° / 360 ° /
f1 Hz) and the frequency is rapidly increased by repeating this. Assuming that the frequency of the system 23 at the time of system interconnection is 50 Hz, the 60 Hz portion of the equation for obtaining f1 may be set to 50 Hz. Also, the amount of change in frequency increases as the difference between φ and θ increases. That is, the larger the difference between φ and θ is, the earlier the islanding detection time is.

Here, when the frequency of the system 23 is, for example, 60 Hz, f _H = 65 Hz, f _L = 55 Hz, and the frequency of the system 23 is 5
When 0Hz is set to a frequency that does not normally occur in the system 23 as such _{f H = 55Hz, f L =} 45Hz. The judgment frequency may be any frequency that does not normally occur. If the difference from the frequency of the system 23 is large, the islanding detection time is long, and the system 2
If the difference from the frequency of No. 3 is small, the islanding detection time will be short. Therefore, if the determination frequency can be set arbitrarily, the islanding detection time can be set arbitrarily. However, if the difference between the judgment frequency and the frequency of the system 23 is too small, erroneous detection of islanding is likely to occur during system interconnection. Therefore, the judgment frequency is determined based on the islanding detection time and the possibility of erroneous detection of islanding. . The output current of the inverter means 26 at the time of system interconnection is output at a constant phase angle θ from the output voltage because a sufficient difference between the control phase angle θ and the phase angle φ of the load 24 occurs even when the load 24 is a resistive load. This is to enable islanding detection.

Next, at the time of system interconnection, the frequency of the system 23 is generally a standard value ± 1 Hz, so that the process proceeds from step 10 to step 11, step 12, and step 15, returns from step 15 to step 10, and repeats this. In the case of the isolated operation, the phase angle θ between the output current and the output voltage of the inverter means 26 and the load phase angle φ determined by the load 24 at the time of system interconnection.
If the difference is small, the frequency changes each time the control unit 29 performs the operation of step 10, and the process proceeds to steps 13 and 14. As described above, according to the present embodiment, the inverter can be reliably stopped during the isolated operation without erroneous detection of the isolated operation at the time of the system interconnection, and furthermore, the configuration is simple, so that the cost can be reduced and the space can be reduced. It is an interconnected inverter.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the present embodiment. The components having the same numbers as those in FIG. 1 have the same functions. Reference numeral 30 denotes a system interconnection inverter according to the present embodiment, which receives the output of the output voltage detection means 27 and outputs an output signal to the zero-voltage phase synchronization signal means 28, and at least the frequency of the output voltage of the inverter means 26 Bandpass filter 31 until exceeding allowable value
And a control means 33 for correcting a phase shift due to the frequency characteristic of the zero voltage phase synchronization signal means 28. The control means 33 receives the output of the zero-voltage phase synchronization signal means 28 and controls the inverter means 26.

The operation of the control means 33 will be described with reference to the flowchart of FIG. In step 20, the control means 33 receives the output of the zero-voltage phase synchronization signal means 28 and detects the zero point of the output voltage of the inverter means 26. The control means 33 outputs a current such that the zero point of the current has a constant phase angle with respect to the detected zero point of the output voltage of the inverter means 26. Here, the output of the zero-voltage phase synchronization signal means 28 has been corrected for a phase shift due to the frequency characteristics of the band-pass filter 31 as in step 26. Next, at step 21, the control means 33 inputs the output of the zero-voltage phase synchronization signal means 28 and measures the output voltage frequency of the inverter means 26. Next, the routine proceeds to step 22.

The control means 33 in step 22 is the frequency measured in step 21 is determined greater than determination frequency f _H. If it is larger, the operation is determined to be the islanding operation, and the process proceeds to step 23. In step 23, the control means 33 stops the operation of the inverter means 26 and proceeds to step 24. Step 2
Although only the operation of the inverter means 26 is stopped at 3, a switch may be inserted in series in a line connected to the load 24, and may be disconnected by the control means 33. In step 24, the control means 33 performs the operation of the inverter means 26 again after a lapse of a predetermined time, and automatically returns to step 20. In step 22 the contrary, when the frequency is determined the frequency f _H is smaller than that measured in step 21, the process proceeds to step 25. In step 25, the control means 33 determines whether the frequency measured in step 21 is smaller than the determination frequency f _L. If it is smaller, it is determined that the vehicle is operating alone, and step 23 is performed.
Proceed to step 24. Conversely, in step 25, step 2
When the frequency measured in step 1 is higher than the determination frequency f _L, it is time for system interconnection, and the process proceeds to step 26.

In step 26, the phase correcting means 32 corrects the phase shift due to the frequency characteristic of the band-pass filter 31 to the zero-voltage phase synchronizing signal means 28 in accordance with the frequency measured in step 21, and returns to step 20. Is repeated. As described above, according to the present invention, the bandpass filter 31 removes frequency components other than the vicinity of the system frequency, such as high-frequency noise and harmonic noise, with respect to the power supply abnormality of the system 23. 31 can correct the phase shift due to the frequency characteristic and improve the zero point detection accuracy and frequency accuracy of the zero-voltage phase synchronization signal means 28. It is a system interconnection inverter for stopping the means.

Embodiment 3 Hereinafter, a third embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the present embodiment. Components having the same numbers as those in FIGS. 1 and 3 have the same functions. Reference numeral 36 denotes a system interconnection inverter according to the present embodiment, to which the output of the output voltage detecting means 27 is input,
The band-pass filter 31 for outputting an output signal to the zero-voltage phase synchronization signal means 28 and the phase shift due to the frequency characteristics of the band-pass filter 31 at least until the frequency of the output voltage of the inverter means 26 exceeds an allowable value. A phase correction means 32 for correcting the signal means 28, a correction amount setting means 34 for arbitrarily setting a correction amount for phase correction by the phase correction means 32, and a control means 35.
The control means 35 receives the output of the zero-voltage phase synchronization signal means 28 and controls the inverter means 26.

The operation of the control means 35 will be described with reference to the flowchart of FIG. In step 30, the control means 35 receives the output of the zero-voltage phase synchronization signal means 28 and detects the zero point of the output voltage of the inverter means 26. The control means 35 outputs a current such that the zero point of the current has a constant phase angle with respect to the detected zero point of the output voltage of the inverter means 26. Here, the output of the zero-voltage phase synchronization signal means 28 corrects the phase shift due to the frequency characteristics of the band-pass filter 31 by the correction amount set by the correction amount setting means 34 as in step 37. Next, at step 31, the control means 35 inputs the output of the zero-voltage phase synchronization signal means 28 and measures the output voltage frequency of the inverter means 26.

Next, the routine proceeds to step 32. Step 32 the control unit 35 is a frequency measured in step 31 is determined greater than determination frequency f _H. If it is larger, the operation is determined to be the islanding operation, and the routine proceeds to step 33. In step 33, the control means 35 stops the operation of the inverter means 26 and proceeds to step 34. Although only the operation of the inverter means 26 is stopped in step 33, a switch may be inserted in series in a line connected to the load 24, and may be disconnected by the control means 35. In step 34, the control means 35 performs the operation of the inverter means 26 again after a predetermined time has elapsed, and automatically returns to step 30. Step 3
2, the determination frequency measured in step 31 the frequency f _H
If it is smaller, the process proceeds to step 35. In step 35, the control means 35 determines whether the frequency measured in step 31 is smaller than the determination frequency f _L. If it is smaller, it is determined that the vehicle is operating alone, and the process proceeds to steps 33 and 34. Conversely, when the frequency measured in step 31 is higher than the judgment frequency f _L in step 35, it is the time of system interconnection, and
Proceed to 6.

In step 36, the correction amount is set by the correction amount setting means 34. For example, if the phase shift due to the frequency characteristic of the band-pass filter 31 is α, the standard correction amount α
In this case, it is possible to set an increase / decrease amount for increasing or decreasing the correction amount. Here, by increasing the correction amount, the time of the frequency change at the time of the isolated operation can be shortened, and the detection time can be shortened. Conversely, by reducing the correction amount, it is possible to delay the time of the frequency change at the time of the isolated operation and to lengthen the detection time. Next, the routine proceeds to step 37. In step 37, the phase correction means 32 adds an increase or decrease in the correction amount set in step 36 according to the frequency measured in step 31 to remove a phase shift due to the frequency characteristic of the band-pass filter 31.
The zero voltage phase synchronization signal means 28 is corrected. Next, returning to step 30, the above operation is repeated. As described above, according to the present invention, the correction amount setting means 34 changes the time during which the frequency of the output voltage of the inverter means changes during the single operation, and makes the detection time variable.

(Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the present embodiment. Components having the same numbers as those in FIGS. 1, 3, and 5 have the same functions. Reference numeral 39 denotes a system interconnection inverter of the present embodiment, which receives the output of the output voltage detection means 27 and outputs an output signal to the zero-voltage phase synchronization signal means 28;
Phase correction means 3 for correcting the phase shift due to the frequency characteristics of the band-pass filter 31 to the zero-voltage phase synchronization signal means 28 until the frequency of the output voltage 6 exceeds the allowable value.
2 and a correction delay time setting means 37 for setting a time for delaying the phase correction by the phase correction means 32 and a control means 3
8. The control means 38 receives the output of the zero-voltage phase synchronization signal means 28 and controls the inverter means 26.

The operation of the control means 38 will be described with reference to the flowchart of FIG. In step 40, the control means 38 inputs the output of the zero-voltage phase synchronization signal means 28 and detects the zero point of the output voltage of the inverter means 26. The control means 38 outputs a current such that the zero point of the current has a constant phase angle with respect to the detected zero point of the output voltage of the inverter means 26. Here, the output of the zero-voltage phase synchronizing signal means 28 is a step 46,
Only when the time set by the correction delay time setting means 37 has passed as in step 47, the bandpass filter 3
The phase shift due to the frequency characteristic 1 is corrected. Next, at step 41, the control means 38 inputs the output of the zero-voltage phase synchronization signal means 28 and measures the output voltage frequency of the inverter means 26. Next, the routine proceeds to step 42.

The control means 38 in step 42 is the frequency measured in step 41 is determined greater than determination frequency f _H. If it is larger, the operation is determined to be the islanding operation, and the process proceeds to step 43. In step 43, the control means 38 stops the operation of the inverter means 26 and proceeds to step 44. Step 4
Although only the operation of the inverter means 26 is stopped at 3, a switch may be inserted in series in a line connected to the load 24, and may be disconnected by the control means 38. In step 44, the control means 38 performs the operation of the inverter means 26 again after a lapse of a predetermined time, and returns automatically to step 40. In step 42 the contrary, when the frequency is determined the frequency f _H is smaller than that measured in step 41, the process proceeds to step 45.

In step 45, the control means 38 determines whether the frequency measured in step 41 is smaller than the determination frequency f _L. If it is smaller, it is determined that the vehicle is operating alone, and step 43 is performed.
Proceed to step 44. Conversely, in step 45, step 4
When the frequency measured in Step 1 is higher than the judgment frequency f _L, it is the time of system interconnection, and the process proceeds to Step 46. In step 46, a time t for delaying the correction is set by the correction delay time setting means 37, and the flow advances to step 47 to determine whether the delay time t has elapsed. If the delay time t has not elapsed in step 47, the process returns to step 40 without correction. Step 4
If the delay time t has elapsed in step 7, the process proceeds to step 48, and the phase correction means 32 causes the phase shift due to the frequency characteristic of the band-pass filter 31 to the zero-voltage phase synchronization signal means 28 according to the frequency measured in step 41. To correct. Next, returning to step 40, the above operation is repeated. Here, in a state where the correction is not performed by the correction delay time, the amount of change in the frequency becomes small, so that the detection time of the isolated operation can be freely delayed. As described above, according to the present invention, a system interconnection inverter is provided in which the time during which the frequency of the output voltage of the inverter means changes during islanding operation is delayed and the detection time has a degree of freedom.

(Embodiment 5) Hereinafter, a fifth embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of this embodiment. Components having the same numbers as those in FIGS. 1, 3, 5, and 7 have the same functions. Reference numeral 44 denotes a system interconnection inverter of the present embodiment, which receives the output of the output voltage detecting means 27 and outputs an output signal to the zero-voltage phase synchronizing signal means 28, and a 50 Hz band-pass filter 43 and a 60 Hz band-pass filter 40; 50/60 Hz switching means 41 for switching the pass filter, and the frequency of the 50 Hz band pass filter 43 or the 60 Hz band pass filter 40 selected by the 50/60 Hz switching means 41 at least until the frequency of the output voltage of the inverter means 26 exceeds an allowable value. The phase shift due to the characteristic is corrected by the phase correction means 32 for correcting the zero voltage phase synchronization signal means 28, the correction amount setting means 34 for arbitrarily setting the correction amount for phase correction by the phase correction means 32, and the phase correction means 32. Correction delay to set the time to delay the phase correction It consists of the control unit 42 and between setting means 37. The control means 42 receives the output of the zero-voltage phase synchronization signal means 28 and controls the inverter means 26.

The operation of the control means 42 will be described with reference to the flowchart of FIG. In step 50, the 50/60 Hz switching means 41 measures the frequency of the system 23. Next, the routine proceeds to step 51. In step 51, it is determined whether the frequency of the system 23 is a 50 Hz system. If it is a 50 Hz system, the process proceeds to step 52. In step 52, 50/60 Hz
The switching means 41 selects the 50-Hz band-pass filter 43. Next, the routine proceeds to step 53. In step 53, the control means 42 receives the output of the zero-voltage phase synchronization signal means 28 and detects the zero point of the output voltage of the inverter means 26.
The control means 42 outputs a current such that the zero point of the current has a constant phase angle with respect to the detected zero point of the output voltage of the inverter means 26. Here, the output of the zero-voltage phase synchronization signal means 28 corrects the phase shift due to the frequency characteristics of the 50 Hz bandpass filter 43 by the correction amount set by the correction amount setting means 34 as in step 59. The output of the zero-voltage phase synchronizing signal means 28 corrects the phase shift due to the frequency characteristics of the 50 Hz bandpass filter 43 only after the time set by the correction delay time setting means 37 as in steps 60 and 61. are doing.

Next, at step 54, the control means 42 inputs the output of the zero-voltage phase synchronization signal means 28 and measures the output voltage frequency of the inverter means 26. Next, the routine proceeds to step 55. In step 55 the control unit 42 is a frequency measured in step 54 is determined greater than determination frequency f50 _H. If it is larger, the operation is determined to be the islanding operation, and the routine proceeds to step 56. In step 56, the control means 42 sets the
The operation of Step 6 is stopped, and the process proceeds to Step 57. Step 56
Although the operation of the inverter means 26 is merely stopped, a switch may be inserted in series in a line connected to the load 24, and the switch may be disconnected by the control means 42. In step 57, the control means 42 performs the operation of the inverter means 26 again after a predetermined time has elapsed, and automatically returns to step 5.
Return to 3. In step 55 the contrary, when the frequency is determined the frequency f50 _H is less than that measured in step 54, the process proceeds to step 58. Step 58 the control unit 42 is a frequency measured in step 54 it is determined whether the determination frequency f50 _L smaller. If it is smaller, it is determined that the vehicle is operating alone, and the process proceeds to steps 56 and 57. In step 58 the contrary, when the frequency is greater than the determination frequency f50 _L measured in step 54 is the time of system interconnection, the process proceeds to step 59.

In step 59, the correction amount is set by the correction amount setting means 34. For example, assuming that the phase shift due to the frequency characteristic of the 50 Hz bandpass filter 43 is α, it is possible to set an increase / decrease amount that makes the correction amount larger or smaller than the standard correction amount α. Here, by increasing the correction amount, the time of the frequency change at the time of the isolated operation can be shortened, and the detection time can be shortened. Conversely, by reducing the correction amount, it is possible to delay the time of the frequency change at the time of the isolated operation and to lengthen the detection time. Next, the routine proceeds to step 60. Step 60
Then, a time t for delaying the correction is set by the correction delay time setting means 37, and the routine proceeds to step 61, where it is determined whether the delay time t has elapsed. If the delay time t has not elapsed in step 61, the process returns to step 53 without correction.

If the delay time t has elapsed in step 61, the process proceeds to step 62, and the phase correction means 32 sets the 50 Hz band-pass filter 4 in accordance with the frequency measured in step 54.
The phase shift due to the frequency characteristic of No. 3 is corrected for the zero-voltage phase synchronization signal means 28. Next, returning to step 53, the above operation is repeated. Here, in a state where the correction is not performed by the correction delay time, the amount of change in the frequency becomes small, so that the detection time of the isolated operation can be freely delayed. Conversely, if the frequency of the system 23 is 60 Hz in step 51, the process proceeds to step 63. In step 63, the 50/60 Hz switching means 41 selects the 60 Hz band pass filter 40. Next, the routine proceeds to step 64. In step 64, the control means 42 receives the output of the zero-voltage phase synchronization signal means 28 and detects the zero point of the output voltage of the inverter means 26. The control means 42 outputs a current such that the zero point of the current has a constant phase angle with respect to the detected zero point of the output voltage of the inverter means 26.

Here, the output of the zero-voltage phase synchronizing signal means 28 corrects the phase shift due to the frequency characteristic of the 60 Hz band-pass filter 40 by the correction amount set by the correction amount setting means 34 as in step 68. . The output of the zero-voltage phase synchronizing signal means 28 is not output from the 60 Hz band-pass filter 4 until the time set by the correction delay time setting means 37 has passed as in steps 69 and 70.
The phase shift due to the zero frequency characteristic is corrected. Next, at step 65, the control means 42 inputs the output of the zero-voltage phase synchronization signal means 28 and measures the output voltage frequency of the inverter means 26. Next, the routine proceeds to step 66. Step 6
Control means 42 in 6 the frequency measured in step 65 is determined greater than determination frequency f60 _H. If it is larger, the operation is determined to be the islanding operation, and the routine proceeds to step 56. Step 56
Then, the control means 42 stops the operation of the inverter means 26 and proceeds to step 57.

In step 57, the control means 42 performs the operation of the inverter means 26 again after a lapse of a predetermined time, and returns automatically to step 64. In step 66 the contrary, when the frequency is determined the frequency f60 _H is less than that measured in step 65, the process proceeds to step 67. Step 67 the control unit 42 is a frequency measured in step 65 it is determined whether the determination frequency f60 _L smaller. If it is smaller, it is determined that the vehicle is operating alone, and the process proceeds to steps 56 and 57. In step 67 the contrary, when the frequency is greater than the determination frequency f60 _L measured in step 65 is the time of system interconnection, the process proceeds to step 68. In step 68, the correction amount is set by the correction amount setting means 34. For example, assuming that the phase shift due to the frequency characteristic of the 60 Hz band-pass filter 40 is α, the amount of increase or decrease of the correction amount than the standard correction amount α can be set. Here, by increasing the correction amount, the time of the frequency change at the time of the isolated operation can be shortened, and the detection time can be shortened. Conversely, by reducing the correction amount, it is possible to delay the time of the frequency change at the time of the isolated operation and to lengthen the detection time.

Next, the routine proceeds to step 69. In step 69, the time t for delaying the correction is set by the correction delay time setting means 37, and the flow advances to step 70 to determine whether the delay time t has elapsed. If the delay time t has not elapsed in step 70, the process returns to step 64 without correction. Step 7
If the delay time t has elapsed at 0, the process proceeds to step 71, and the phase correction means 32 causes the phase shift due to the frequency characteristic of the 60 Hz band-pass filter 40 to the zero voltage phase synchronization signal means 28 according to the frequency measured at step 65. Correct for. Next, returning to step 64, the above operation is repeated.
Here, in a state where the correction is not performed by the correction delay time, the amount of change in the frequency becomes small, so that the detection time of the isolated operation can be freely delayed. F60 _H = 65 Hz, f6
0 _L = 55Hz, when the frequency of the system is 50Hz f50 _H
= 55 Hz, f50 _L = 45 Hz, etc., which are not normally generated in the system.

As described above, according to the present embodiment, the allowable value of the frequency can be set to be far from the frequency range which can be considered in the system. A point that removes frequency components other than the vicinity of the system frequency, such as noise, and corrects the phase shift due to the frequency characteristics of the band-pass filter by the phase correction means, thereby improving the zero point detection accuracy and frequency accuracy of the zero voltage phase synchronization signal means. , The bandpass filter can be switched depending on the system frequency.
From the point that the correction accuracy due to the phase shift of the band-pass filter at 0 Hz can be improved, the correction amount setting unit that can shorten the detection time of the isolated operation, and the correction delay time setting unit that can be lengthened can also set the finer time. A grid-connected inverter capable of reliably stopping the inverter means during the single operation without erroneously detecting the single operation during the grid connection.

[0043]

As described above, according to the first aspect of the present invention, there are provided inverter means for converting an input power supply into an AC power supply and outputting the AC power to the system, output voltage detection means for detecting an output voltage of the inverter means, An output signal of the output voltage detecting means is input, a zero voltage phase synchronizing signal means for outputting a signal synchronized with a zero voltage phase of an output voltage of the inverter means, and an output of the zero voltage phase synchronizing signal means is inputted, Controlling the inverter means to output the zero point of the output current of the means from the zero point of the output voltage at a constant phase angle,
Control the frequency of the output voltage of the inverter means and stop the inverter means when the measured frequency exceeds the permissible value. By setting such a location, the inverter means can be stopped reliably during the isolated operation without erroneous detection of the isolated operation at the time of the system interconnection, so that the system-connected inverter has a simple configuration.

According to a second aspect of the present invention, there is provided a band-pass filter which receives an output of the output voltage detecting means and outputs an output signal to the zero-voltage phase synchronization signal means, and at least a frequency of an output voltage of the inverter means is allowed. The system is equipped with a phase correction unit that corrects the phase shift due to the frequency characteristics of the band-pass filter to the zero-voltage phase synchronization signal unit until the value exceeds the value. In addition to removing frequency components other than the vicinity of the system frequency, the phase correction means corrects the phase shift due to the frequency characteristic of the band-pass filter. A system-linked inverter that reliably stops the inverter means during islanding operation without erroneous detection of islanding operation Than it is.

Further, the invention according to claim 3 is provided with a correction amount setting means for arbitrarily setting a correction amount for phase correction by the phase correction means, and the isolated operation is performed by changing the correction amount from the standard correction amount. A system interconnection inverter capable of changing the time at which the frequency of the output voltage of the inverter means changes at times and varying the detection time.

Further, the invention described in claim 4 is provided with a correction delay time setting means for setting a time for delaying the phase correction by the phase correction means. It is a system interconnection inverter in which the time during which the frequency of the output voltage of the inverter means changes is delayed and the detection time has a degree of freedom.

According to a fifth aspect of the present invention, there are provided two band-pass filters for 50 Hz and 60 Hz.
A system interconnection inverter having a configuration provided with 50/60 Hz switching means for switching to a band-pass filter for 50 Hz or 60 Hz, and having improved correction accuracy due to a phase shift of the band-pass filter when the system frequency is 50 Hz and 60 Hz. Things.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a grid-connected inverter according to a first embodiment of the present invention;

FIG. 2 is a flowchart showing the operation of the same-system interconnection inverter;

FIG. 3 is a block diagram showing a grid-connected inverter according to a second embodiment of the present invention;

FIG. 4 is a flowchart showing the operation of the same system interconnection inverter;

FIG. 5 is a block diagram showing a grid-connected inverter according to a third embodiment of the present invention;

FIG. 6 is a flowchart showing the operation of the same system interconnection inverter;

FIG. 7 is a block diagram showing a grid-connected inverter according to a fourth embodiment of the present invention;

FIG. 8 is a flowchart showing the operation of the same system interconnection inverter;

FIG. 9 is a block diagram showing a grid-connected inverter according to a fifth embodiment of the present invention;

FIG. 10 is a flowchart showing the operation of the grid-connected inverter;

FIG. 11 is a block diagram showing a conventional system interconnection inverter.

FIG. 12 is an explanatory diagram of the operation of the same system interconnection inverter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Grid connection inverter 26 Inverter means 27 Output voltage detection means 28 Zero voltage phase synchronizing signal means 29 Control means 30 System connection inverter 31 Band pass filter 32 Phase correction means 33 Control means 34 Correction amount setting means 35 Control means 36 System connection System inverter 37 Correction delay time setting means 38 Control means 39 System interconnection inverter 40 60 Hz bandpass filter 41 50/60 Hz switching means 42 Control means 43 50 Hz bandpass filter 44 System interconnection inverter

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor ▲ Taka ▼ Masayuki Kuwa 1006 Kadoma, Kazuma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. In-house F term (reference) 5G066 HA11 HB04 5H007 AA01 AA07 AA08 AA17 BB02 CC09 DA03 DB01 DC04 DC05 FA13 GA06 GA08 5J055 AX37 AX51 AX67 BX16 CX07 EZ07 EZ14 FX31 GX02 GX03

Claims (5)

[Claims] An inverter for converting an input power supply into an AC power supply and outputting the AC power to a system, an output voltage detection means for detecting an output voltage of the inverter means, and an output signal from the output voltage detection means, Zero voltage phase synchronization signal means for outputting a signal synchronized with the zero voltage phase of the output voltage of the inverter means, and the output of the zero voltage phase synchronization signal means is inputted, and the zero point of the output current of the inverter means is converted to the zero point of the output voltage. And controlling the inverter means to output at a constant phase angle from, measuring the frequency of the output voltage of the inverter means, and when the measured frequency exceeds an allowable value, control means for stopping the inverter means. A grid-connected inverter equipped with 2. An output of the output voltage detecting means is input,
A band-pass filter for outputting an output signal to the zero-voltage phase-locking signal means; and a zero-voltage phase-locked phase shift at least until the frequency of the output voltage of the inverter means exceeds an allowable value. 2. The system interconnection inverter according to claim 1, further comprising phase correction means for correcting the signal means. 3. A correction amount setting means for arbitrarily setting a correction amount for phase correction by said phase correction means.
Or the grid-connected inverter according to 2. 4. The system interconnection inverter according to claim 1, further comprising a correction delay time setting means for setting a time for delaying the phase correction by said phase correction means. 5. The band-pass filter according to claim 1, wherein said band-pass filter is provided for 50 Hz and 60 Hz, and said band-pass filter is provided with 50/60 Hz switching means for switching to a band-pass filter for 50 Hz or 60 Hz. Grid-connected inverter.