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ITVA20050061A1 - Metodo di gestione di un dispositivo di memoria non volatile e relativa memoria - Google Patents

Metodo di gestione di un dispositivo di memoria non volatile e relativa memoria

Info

Publication number
ITVA20050061A1
ITVA20050061A1 IT000061A ITVA20050061A ITVA20050061A1 IT VA20050061 A1 ITVA20050061 A1 IT VA20050061A1 IT 000061 A IT000061 A IT 000061A IT VA20050061 A ITVA20050061 A IT VA20050061A IT VA20050061 A1 ITVA20050061 A1 IT VA20050061A1
Authority
IT
Italy
Prior art keywords
management
relative
memory device
volatile memory
memory
Prior art date
Application number
IT000061A
Other languages
English (en)
Inventor
Procolo Carannante
Adamo Corsi
Tuoro Concetta Di
Gianfranco Ferrante
Demetrio Pellicone
Marco Roveda
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000061A priority Critical patent/ITVA20050061A1/it
Priority to US11/557,786 priority patent/US7571362B2/en
Publication of ITVA20050061A1 publication Critical patent/ITVA20050061A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
IT000061A 2005-11-08 2005-11-08 Metodo di gestione di un dispositivo di memoria non volatile e relativa memoria ITVA20050061A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000061A ITVA20050061A1 (it) 2005-11-08 2005-11-08 Metodo di gestione di un dispositivo di memoria non volatile e relativa memoria
US11/557,786 US7571362B2 (en) 2005-11-08 2006-11-08 Method of managing fails in a non-volatile memory device and relative memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000061A ITVA20050061A1 (it) 2005-11-08 2005-11-08 Metodo di gestione di un dispositivo di memoria non volatile e relativa memoria

Publications (1)

Publication Number Publication Date
ITVA20050061A1 true ITVA20050061A1 (it) 2007-05-09

Family

ID=38040634

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000061A ITVA20050061A1 (it) 2005-11-08 2005-11-08 Metodo di gestione di un dispositivo di memoria non volatile e relativa memoria

Country Status (2)

Country Link
US (1) US7571362B2 (it)
IT (1) ITVA20050061A1 (it)

Families Citing this family (340)

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