DE602007002041D1 - Nichtflüchtige Speichervorrichtung und Verfahren zum Betreiben derselben - Google Patents
Nichtflüchtige Speichervorrichtung und Verfahren zum Betreiben derselbenInfo
- Publication number
- DE602007002041D1 DE602007002041D1 DE602007002041T DE602007002041T DE602007002041D1 DE 602007002041 D1 DE602007002041 D1 DE 602007002041D1 DE 602007002041 T DE602007002041 T DE 602007002041T DE 602007002041 T DE602007002041 T DE 602007002041T DE 602007002041 D1 DE602007002041 D1 DE 602007002041D1
- Authority
- DE
- Germany
- Prior art keywords
- operating
- same
- memory device
- volatile memory
- volatile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060133093A KR101169396B1 (ko) | 2006-12-22 | 2006-12-22 | 비휘발성 메모리 소자 및 그 동작 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602007002041D1 true DE602007002041D1 (de) | 2009-10-01 |
Family
ID=39110541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602007002041T Active DE602007002041D1 (de) | 2006-12-22 | 2007-12-11 | Nichtflüchtige Speichervorrichtung und Verfahren zum Betreiben derselben |
Country Status (6)
Country | Link |
---|---|
US (1) | US7679960B2 (de) |
EP (1) | EP1936681B1 (de) |
JP (1) | JP2008160113A (de) |
KR (1) | KR101169396B1 (de) |
CN (1) | CN101207136B (de) |
DE (1) | DE602007002041D1 (de) |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20080010900A (ko) * | 2006-07-28 | 2008-01-31 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법 |
KR100763918B1 (ko) * | 2006-07-28 | 2007-10-05 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
KR20080087580A (ko) * | 2007-03-27 | 2008-10-01 | 삼성전자주식회사 | 비휘발성 메모리 소자의 제조 방법 |
JP5331826B2 (ja) | 2008-03-10 | 2013-10-30 | フォルティメディクス・サージカル・ベスローテン・フェンノートシャップ | 内視鏡用途のための器具を作製する方法及びこの方法を用いて得られる内視鏡用途のための器具 |
KR101491714B1 (ko) * | 2008-09-16 | 2015-02-16 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
KR101019893B1 (ko) * | 2008-12-23 | 2011-03-04 | 주식회사 하이닉스반도체 | 플로팅 바디 효과를 이용한 자기저항 메모리셀, 이를 포함하는 메모리 소자 및 그 동작 방법 |
US8203187B2 (en) | 2009-03-03 | 2012-06-19 | Macronix International Co., Ltd. | 3D memory array arranged for FN tunneling program and erase |
TWI433302B (zh) | 2009-03-03 | 2014-04-01 | Macronix Int Co Ltd | 積體電路自對準三度空間記憶陣列及其製作方法 |
US8173987B2 (en) | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US8829646B2 (en) | 2009-04-27 | 2014-09-09 | Macronix International Co., Ltd. | Integrated circuit 3D memory array and manufacturing method |
US8383512B2 (en) | 2011-01-19 | 2013-02-26 | Macronix International Co., Ltd. | Method for making multilayer connection structure |
US8154128B2 (en) | 2009-10-14 | 2012-04-10 | Macronix International Co., Ltd. | 3D integrated circuit layer interconnect |
JP5388814B2 (ja) * | 2009-11-24 | 2014-01-15 | 株式会社東芝 | 半導体記憶装置 |
US8437192B2 (en) | 2010-05-21 | 2013-05-07 | Macronix International Co., Ltd. | 3D two bit-per-cell NAND flash memory |
US8735902B2 (en) * | 2010-05-10 | 2014-05-27 | Micron Technology, Inc. | Memories with memory arrays extending in opposite directions from a semiconductor and their formation |
US8395942B2 (en) * | 2010-05-17 | 2013-03-12 | Sandisk Technologies Inc. | Junctionless TFT NAND flash memory |
US8890233B2 (en) | 2010-07-06 | 2014-11-18 | Macronix International Co., Ltd. | 3D memory array with improved SSL and BL contact layout |
US8659944B2 (en) | 2010-09-01 | 2014-02-25 | Macronix International Co., Ltd. | Memory architecture of 3D array with diode in memory string |
KR101152446B1 (ko) * | 2010-12-08 | 2012-06-01 | 한양대학교 산학협력단 | 프린징 효과 및 정전차폐를 이용하는 플래시 메모리 |
US8630114B2 (en) | 2011-01-19 | 2014-01-14 | Macronix International Co., Ltd. | Memory architecture of 3D NOR array |
US8486791B2 (en) | 2011-01-19 | 2013-07-16 | Macronix International Co., Ltd. | Mufti-layer single crystal 3D stackable memory |
US8503213B2 (en) | 2011-01-19 | 2013-08-06 | Macronix International Co., Ltd. | Memory architecture of 3D array with alternating memory string orientation and string select structures |
US8598032B2 (en) | 2011-01-19 | 2013-12-03 | Macronix International Co., Ltd | Reduced number of masks for IC device with stacked contact levels |
US8836137B2 (en) | 2012-04-19 | 2014-09-16 | Macronix International Co., Ltd. | Method for creating a 3D stacked multichip module |
JP2012244180A (ja) | 2011-05-24 | 2012-12-10 | Macronix Internatl Co Ltd | 多層接続構造及びその製造方法 |
US8574992B2 (en) | 2011-09-22 | 2013-11-05 | Macronix International Co., Ltd. | Contact architecture for 3D memory array |
US8541882B2 (en) | 2011-09-22 | 2013-09-24 | Macronix International Co. Ltd. | Stacked IC device with recessed conductive layers adjacent to interlevel conductors |
US9082656B2 (en) | 2011-11-11 | 2015-07-14 | Macronix International Co., Ltd. | NAND flash with non-trapping switch transistors |
US8570806B2 (en) | 2011-12-13 | 2013-10-29 | Macronix International Co., Ltd. | Z-direction decoding for three dimensional memory array |
US9035275B2 (en) | 2011-12-19 | 2015-05-19 | Macronix International Co., Ltd. | Three dimensional memory array adjacent to trench sidewalls |
US8587998B2 (en) | 2012-01-06 | 2013-11-19 | Macronix International Co., Ltd. | 3D memory array with read bit line shielding |
US8987098B2 (en) | 2012-06-19 | 2015-03-24 | Macronix International Co., Ltd. | Damascene word line |
US8633099B1 (en) | 2012-07-19 | 2014-01-21 | Macronix International Co., Ltd. | Method for forming interlayer connectors in a three-dimensional stacked IC device |
US8927957B2 (en) | 2012-08-09 | 2015-01-06 | Macronix International Co., Ltd. | Sidewall diode driving device and memory using same |
US8736069B2 (en) | 2012-08-23 | 2014-05-27 | Macronix International Co., Ltd. | Multi-level vertical plug formation with stop layers of increasing thicknesses |
US9196315B2 (en) | 2012-11-19 | 2015-11-24 | Macronix International Co., Ltd. | Three dimensional gate structures with horizontal extensions |
US9224474B2 (en) | 2013-01-09 | 2015-12-29 | Macronix International Co., Ltd. | P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals |
US8759899B1 (en) | 2013-01-11 | 2014-06-24 | Macronix International Co., Ltd. | Integration of 3D stacked IC device with peripheral circuits |
US9171636B2 (en) | 2013-01-29 | 2015-10-27 | Macronix International Co. Ltd. | Hot carrier generation and programming in NAND flash |
US8987914B2 (en) | 2013-02-07 | 2015-03-24 | Macronix International Co., Ltd. | Conductor structure and method |
US9214351B2 (en) | 2013-03-12 | 2015-12-15 | Macronix International Co., Ltd. | Memory architecture of thin film 3D array |
US8993429B2 (en) | 2013-03-12 | 2015-03-31 | Macronix International Co., Ltd. | Interlayer conductor structure and method |
US9379126B2 (en) | 2013-03-14 | 2016-06-28 | Macronix International Co., Ltd. | Damascene conductor for a 3D device |
US9076535B2 (en) | 2013-07-08 | 2015-07-07 | Macronix International Co., Ltd. | Array arrangement including carrier source |
US9117526B2 (en) | 2013-07-08 | 2015-08-25 | Macronix International Co., Ltd. | Substrate connection of three dimensional NAND for improving erase performance |
US9214234B2 (en) | 2013-09-05 | 2015-12-15 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
US9099538B2 (en) | 2013-09-17 | 2015-08-04 | Macronix International Co., Ltd. | Conductor with a plurality of vertical extensions for a 3D device |
US9070447B2 (en) | 2013-09-26 | 2015-06-30 | Macronix International Co., Ltd. | Contact structure and forming method |
US8970040B1 (en) | 2013-09-26 | 2015-03-03 | Macronix International Co., Ltd. | Contact structure and forming method |
US9343322B2 (en) | 2014-01-17 | 2016-05-17 | Macronix International Co., Ltd. | Three dimensional stacking memory film structure |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9196628B1 (en) | 2014-05-08 | 2015-11-24 | Macronix International Co., Ltd. | 3D stacked IC device with stepped substack interlayer connectors |
US9721964B2 (en) | 2014-06-05 | 2017-08-01 | Macronix International Co., Ltd. | Low dielectric constant insulating material in 3D memory |
US9373409B2 (en) | 2014-07-08 | 2016-06-21 | Macronix International Co., Ltd. | Systems and methods for reduced program disturb for 3D NAND flash |
US9312019B1 (en) | 2014-09-29 | 2016-04-12 | Kabushiki Kaisha Toshiba | Memory device and method for operating the same |
US9379129B1 (en) | 2015-04-13 | 2016-06-28 | Macronix International Co., Ltd. | Assist gate structures for three-dimensional (3D) vertical gate array memory structure |
US9478259B1 (en) | 2015-05-05 | 2016-10-25 | Macronix International Co., Ltd. | 3D voltage switching transistors for 3D vertical gate memory array |
KR102118440B1 (ko) | 2018-09-05 | 2020-06-03 | 고려대학교 산학협력단 | 휘발성 및 비휘발성 동작변환 가능한 피드백 전계효과 배열소자 및 이를 이용한 배열 회로 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06208796A (ja) | 1993-11-01 | 1994-07-26 | Hitachi Ltd | 半導体メモリ |
KR100333275B1 (ko) * | 1999-05-20 | 2002-04-24 | 구본준, 론 위라하디락사 | 액정표시장치의 tft 및 그 제조방법 |
JP2003007869A (ja) * | 2001-06-26 | 2003-01-10 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2003298021A (ja) * | 2002-03-29 | 2003-10-17 | Seiko Epson Corp | 強誘電体薄膜の形成方法、強誘電体メモリならびに強誘電体メモリの製造方法、および半導体装置ならびに半導体装置の製造方法 |
KR100432889B1 (ko) * | 2002-04-12 | 2004-05-22 | 삼성전자주식회사 | 2비트 기입가능한 비휘발성 메모리 소자, 그 구동방법 및그 제조방법 |
JP2004039965A (ja) * | 2002-07-05 | 2004-02-05 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
JP4405412B2 (ja) * | 2005-03-02 | 2010-01-27 | 株式会社東芝 | 半導体集積回路 |
US20060278913A1 (en) * | 2005-06-08 | 2006-12-14 | Micron Technology, Inc. | Non-volatile memory cells without diffusion junctions |
-
2006
- 2006-12-22 KR KR1020060133093A patent/KR101169396B1/ko not_active IP Right Cessation
-
2007
- 2007-10-31 US US11/980,358 patent/US7679960B2/en not_active Expired - Fee Related
- 2007-12-11 EP EP07122917A patent/EP1936681B1/de not_active Expired - Fee Related
- 2007-12-11 DE DE602007002041T patent/DE602007002041D1/de active Active
- 2007-12-17 JP JP2007325241A patent/JP2008160113A/ja active Pending
- 2007-12-20 CN CN2007101991976A patent/CN101207136B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7679960B2 (en) | 2010-03-16 |
EP1936681A1 (de) | 2008-06-25 |
CN101207136A (zh) | 2008-06-25 |
EP1936681B1 (de) | 2009-08-19 |
CN101207136B (zh) | 2010-12-22 |
KR20080058896A (ko) | 2008-06-26 |
KR101169396B1 (ko) | 2012-07-30 |
US20080151631A1 (en) | 2008-06-26 |
JP2008160113A (ja) | 2008-07-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |