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IT1252575B - Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura - Google Patents

Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura

Info

Publication number
IT1252575B
IT1252575B ITMI913440A ITMI913440A IT1252575B IT 1252575 B IT1252575 B IT 1252575B IT MI913440 A ITMI913440 A IT MI913440A IT MI913440 A ITMI913440 A IT MI913440A IT 1252575 B IT1252575 B IT 1252575B
Authority
IT
Italy
Prior art keywords
mold
plate
dissipator
manufacture
cavity
Prior art date
Application number
ITMI913440A
Other languages
English (en)
Inventor
Paolo Casati
Pierangelo Magni
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to ITMI913440A priority Critical patent/IT1252575B/it
Publication of ITMI913440A0 publication Critical patent/ITMI913440A0/it
Priority to DE69216377T priority patent/DE69216377T2/de
Priority to EP92118078A priority patent/EP0548496B1/en
Priority to JP29671592A priority patent/JP3217876B2/ja
Priority to US07/994,421 priority patent/US5445995A/en
Publication of ITMI913440A1 publication Critical patent/ITMI913440A1/it
Application granted granted Critical
Publication of IT1252575B publication Critical patent/IT1252575B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10931—Exposed leads, i.e. encapsulation of component partly removed for exposing a part of lead, e.g. for soldering purposes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)

Abstract

E' descritto uno stampo (10) per dispositivi a semiconduttore per montaggio in superficie, del tipo comprendente una lastrina metallica (12) e un corpo in plastica (20). Esso è formato da due piastre (10a, l0b) che delimitano almeno una cavità (11) atta ad alloggiare la lastrina (12) e a contenere materia plastica per la formazione del corpo (20) del dispositivo. Due elementi (16) dello stampo (io) spingono la lastrina (12) su lati opposti contro il fondo della cavità (11). La cavità (11) presenta due estensioni laterali (18) che sono delimitate dalle superfici laterali del bordi della lastrina, cosicché in esse si formano delle protrusioni (22) di plastica che si staccano facilmente dopo lo stampaggio. Si ottiene così una struttura in cui la lastrina (12) ha la superficie di fondo e due parti laterali di bordo completamente scoperte che consentono una saldatura ottima e controllabile su una piastra a circuito stampato.
ITMI913440A 1991-12-20 1991-12-20 Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura IT1252575B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
ITMI913440A IT1252575B (it) 1991-12-20 1991-12-20 Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura
DE69216377T DE69216377T2 (de) 1991-12-20 1992-10-22 Form und Verfahren zur Herstellung von Kunststoffpackungen für integrierte Schaltungen die eine freie metallische Wärmesenke enthalten zur Inspektion der Lötverbindung
EP92118078A EP0548496B1 (en) 1991-12-20 1992-10-22 A mold and a method for manufacturing semiconductor devices of plastics incorporating an exposed heat sink of metal for inspecting the soldered joint
JP29671592A JP3217876B2 (ja) 1991-12-20 1992-11-06 半導体電子素子構造を製造するためのモールドおよびそれを用いて半導体電子素子構造を製造する方法
US07/994,421 US5445995A (en) 1991-12-20 1992-12-21 Method for manufacturing plastic-encapsulated semiconductor devices with exposed metal heat sink

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI913440A IT1252575B (it) 1991-12-20 1991-12-20 Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura

Publications (3)

Publication Number Publication Date
ITMI913440A0 ITMI913440A0 (it) 1991-12-20
ITMI913440A1 ITMI913440A1 (it) 1993-06-20
IT1252575B true IT1252575B (it) 1995-06-19

Family

ID=11361402

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI913440A IT1252575B (it) 1991-12-20 1991-12-20 Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura

Country Status (5)

Country Link
US (1) US5445995A (it)
EP (1) EP0548496B1 (it)
JP (1) JP3217876B2 (it)
DE (1) DE69216377T2 (it)
IT (1) IT1252575B (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1252575B (it) * 1991-12-20 1995-06-19 Sgs Thomson Microelectronics Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura
DE69620564T2 (de) * 1996-01-25 2003-01-30 Stmicroelectronics S.R.L., Agrate Brianza Kunststoffkörper eines Leitungshalbleiters zur Oberflächenmontage mit optimierten charakteristischen Abmessungen zur Benutzung von Standard-Transport- und Testhaltern
DE19624478A1 (de) * 1996-02-08 1998-01-02 Bayerische Motoren Werke Ag Verfahren zum Herstellen eines elektronischen Steuergeräts
DE19621766A1 (de) * 1996-05-30 1997-12-04 Siemens Ag Halbleiteranordnung mit Kunststoffgehäuse und Wärmeverteiler
US6046501A (en) * 1996-10-02 2000-04-04 Matsushita Electric Industrial Co., Ltd. RF-driven semiconductor device
US5939775A (en) * 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
DE69636853T2 (de) * 1996-11-27 2007-11-08 Stmicroelectronics S.R.L., Agrate Brianza Herstellunsgverfahren einer Kunststoffpackung für elektronische Anordnungen mit einer Wärmesenke
JP3027954B2 (ja) * 1997-04-17 2000-04-04 日本電気株式会社 集積回路装置、その製造方法
AU2000275687A1 (en) * 2000-09-08 2002-03-22 Asm Technology Singapore Pte Ltd. A mold
US20040113240A1 (en) 2002-10-11 2004-06-17 Wolfgang Hauser An electronic component with a leadframe
DE102005016830A1 (de) * 2004-04-14 2005-11-03 Denso Corp., Kariya Halbleitervorrichtung und Verfahren zu ihrer Herstellung

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Publication number Priority date Publication date Assignee Title
US4216577A (en) * 1975-12-31 1980-08-12 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Portable standardized card adapted to provide access to a system for processing electrical signals and a method of manufacturing such a card
JPS5480079A (en) * 1978-08-07 1979-06-26 Dai Ichi Seiko Co Ltd Method of forming semiconductor seal
JPS6188535A (ja) * 1984-10-08 1986-05-06 Nec Corp 半導体装置の製造方法
JPS62128721A (ja) * 1985-11-29 1987-06-11 Rohm Co Ltd 樹脂成形方法
JPS62244139A (ja) * 1986-04-17 1987-10-24 Citizen Watch Co Ltd 樹脂封止型ピングリツドアレイ及びその製造方法
IT1201836B (it) * 1986-07-17 1989-02-02 Sgs Microelettronica Spa Dispositivo a semiconduttore montato in un contenitore segmentato altamente flessibile e fornite di dissipatore termico
US4688152A (en) * 1986-08-11 1987-08-18 National Semiconductor Corporation Molded pin grid array package GPT
JPS63107159A (ja) * 1986-10-24 1988-05-12 Toshiba Corp 半導体装置
JPH0828443B2 (ja) * 1987-09-26 1996-03-21 株式会社東芝 半導体装置
JP2752677B2 (ja) * 1989-01-11 1998-05-18 日本電気株式会社 半導体装置の製造方法
US5157478A (en) * 1989-04-19 1992-10-20 Mitsubishi Denki Kabushiki Kaisha Tape automated bonding packaged semiconductor device incorporating a heat sink
JPH02306639A (ja) * 1989-05-22 1990-12-20 Toshiba Corp 半導体装置の樹脂封入方法
ATE154990T1 (de) * 1991-04-10 1997-07-15 Caddock Electronics Inc Schichtwiderstand
IT1252575B (it) * 1991-12-20 1995-06-19 Sgs Thomson Microelectronics Stampo e procedimento per la fabbricazione di dispositivi a semiconduttore in plastica, con dissipatore metallico visibile per il controllo della saldatura

Also Published As

Publication number Publication date
EP0548496B1 (en) 1997-01-02
JP3217876B2 (ja) 2001-10-15
DE69216377D1 (de) 1997-02-13
EP0548496A1 (en) 1993-06-30
ITMI913440A1 (it) 1993-06-20
DE69216377T2 (de) 1997-04-24
ITMI913440A0 (it) 1991-12-20
JPH05326589A (ja) 1993-12-10
US5445995A (en) 1995-08-29

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