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IT1044592B - Dispositivo semiconduttor - Google Patents

Dispositivo semiconduttor

Info

Publication number
IT1044592B
IT1044592B IT28663/75A IT2866375A IT1044592B IT 1044592 B IT1044592 B IT 1044592B IT 28663/75 A IT28663/75 A IT 28663/75A IT 2866375 A IT2866375 A IT 2866375A IT 1044592 B IT1044592 B IT 1044592B
Authority
IT
Italy
Prior art keywords
semiconductor device
semiconductor
Prior art date
Application number
IT28663/75A
Other languages
English (en)
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of IT1044592B publication Critical patent/IT1044592B/it

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
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    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905Plural dram cells share common contact or common trench

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)
  • Photovoltaic Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
IT28663/75A 1974-10-26 1975-10-24 Dispositivo semiconduttor IT1044592B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49123765A JPS6022497B2 (ja) 1974-10-26 1974-10-26 半導体装置

Publications (1)

Publication Number Publication Date
IT1044592B true IT1044592B (it) 1980-03-31

Family

ID=14868714

Family Applications (1)

Application Number Title Priority Date Filing Date
IT28663/75A IT1044592B (it) 1974-10-26 1975-10-24 Dispositivo semiconduttor

Country Status (15)

Country Link
US (1) US4063275A (it)
JP (1) JPS6022497B2 (it)
AT (1) AT370561B (it)
AU (1) AU504667B2 (it)
BR (1) BR7506996A (it)
CA (1) CA1046650A (it)
CH (1) CH608653A5 (it)
DE (1) DE2547304A1 (it)
DK (1) DK142758B (it)
ES (1) ES442102A1 (it)
FR (1) FR2290040A1 (it)
GB (1) GB1515179A (it)
IT (1) IT1044592B (it)
NL (1) NL183260C (it)
SE (1) SE411606B (it)

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DE2632647A1 (de) * 1976-07-20 1978-01-26 Siemens Ag Halbleiterbauelement mit passivierender schutzschicht
IN147578B (it) * 1977-02-24 1980-04-19 Rca Corp
DE2730367A1 (de) * 1977-07-05 1979-01-18 Siemens Ag Verfahren zum passivieren von halbleiterelementen
US4174252A (en) * 1978-07-26 1979-11-13 Rca Corporation Method of defining contact openings in insulating layers on semiconductor devices without the formation of undesirable pinholes
CA1136773A (en) * 1978-08-14 1982-11-30 Norikazu Ohuchi Semiconductor device
FR2459551A1 (fr) * 1979-06-19 1981-01-09 Thomson Csf Procede et structure de passivation a autoalignement sur l'emplacement d'un masque
GB2071411B (en) * 1980-03-07 1983-12-21 Philips Electronic Associated Passivating p-n junction devices
US4344985A (en) * 1981-03-27 1982-08-17 Rca Corporation Method of passivating a semiconductor device with a multi-layer passivant system by thermally growing a layer of oxide on an oxygen doped polycrystalline silicon layer
US4420765A (en) * 1981-05-29 1983-12-13 Rca Corporation Multi-layer passivant system
AT384121B (de) * 1983-03-28 1987-10-12 Shell Austria Verfahren zum gettern von halbleiterbauelementen
JPS6042859A (ja) * 1983-08-19 1985-03-07 Toshiba Corp 高耐圧半導体装置の製造方法
JPS61222172A (ja) * 1985-03-15 1986-10-02 Sharp Corp Mosfetのゲ−ト絶縁膜形成方法
JPS6276673A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 高耐圧半導体装置
DE3542166A1 (de) * 1985-11-29 1987-06-04 Telefunken Electronic Gmbh Halbleiterbauelement
EP0388612B1 (en) * 1989-03-24 1994-11-30 International Business Machines Corporation Semiconductor device with self-aligned contact to buried subcollector
JPH04343479A (ja) * 1991-05-21 1992-11-30 Nec Yamagata Ltd 可変容量ダイオード
EP0620586B1 (en) * 1993-04-05 2001-06-20 Denso Corporation Semiconductor device having thin film resistor
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
CN1293374C (zh) * 2002-04-17 2007-01-03 北京师范大学 能直接测量波长的新结构光电探测器及其探测方法
CN111816574B (zh) * 2020-05-29 2022-03-04 济宁东方芯电子科技有限公司 一种uv膜模板及利用uv膜模板实现洁净玻璃钝化的方法

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GB1515179A (en) 1978-06-21
DK480275A (it) 1976-04-27
AT370561B (de) 1983-04-11
SE7511927L (sv) 1976-04-27
DE2547304C2 (it) 1988-08-11
ATA818475A (de) 1982-08-15
JPS5149686A (it) 1976-04-30
NL183260C (nl) 1988-09-01
DK142758C (it) 1981-08-10
AU504667B2 (en) 1979-10-25
FR2290040A1 (fr) 1976-05-28
NL183260B (nl) 1988-04-05
NL7512559A (nl) 1976-04-28
SE411606B (sv) 1980-01-14
AU8599175A (en) 1977-04-28
ES442102A1 (es) 1977-03-16
FR2290040B1 (it) 1979-08-17
US4063275A (en) 1977-12-13
BR7506996A (pt) 1976-08-17
CA1046650A (en) 1979-01-16
JPS6022497B2 (ja) 1985-06-03
DK142758B (da) 1981-01-12
DE2547304A1 (de) 1976-04-29
CH608653A5 (it) 1979-01-15

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