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GB2614069B - Cache systems - Google Patents

Cache systems Download PDF

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Publication number
GB2614069B
GB2614069B GB2118624.2A GB202118624A GB2614069B GB 2614069 B GB2614069 B GB 2614069B GB 202118624 A GB202118624 A GB 202118624A GB 2614069 B GB2614069 B GB 2614069B
Authority
GB
United Kingdom
Prior art keywords
cache systems
cache
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2118624.2A
Other versions
GB2614069A (en
Inventor
Henrik Uhrenholt Olof
Henrik Jahren Ole
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to GB2118624.2A priority Critical patent/GB2614069B/en
Priority to CN202211457453.8A priority patent/CN116303134A/en
Priority to US18/064,044 priority patent/US12135651B2/en
Priority to US18/064,020 priority patent/US20230195631A1/en
Priority to KR1020220176018A priority patent/KR20230094998A/en
Priority to US18/067,180 priority patent/US20230195638A1/en
Publication of GB2614069A publication Critical patent/GB2614069A/en
Application granted granted Critical
Publication of GB2614069B publication Critical patent/GB2614069B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0817Cache consistency protocols using directory methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0817Cache consistency protocols using directory methods
    • G06F12/0826Limited pointers directories; State-only directories without pointers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877Cache access modes
    • G06F12/0886Variable-length word access
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/60Memory management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30Providing cache or TLB in specific location of a processing system
    • G06F2212/302In image processor or graphics adapter
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40Specific encoding of data in memory or cache
    • G06F2212/401Compressed data
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45Caching of specific data in cache memory
    • G06F2212/455Image or video data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB2118624.2A 2021-12-21 2021-12-21 Cache systems Active GB2614069B (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
GB2118624.2A GB2614069B (en) 2021-12-21 2021-12-21 Cache systems
CN202211457453.8A CN116303134A (en) 2021-12-21 2022-11-21 Cache system
US18/064,044 US12135651B2 (en) 2021-12-21 2022-12-09 Cache systems with different address domains
US18/064,020 US20230195631A1 (en) 2021-12-21 2022-12-09 Cache systems
KR1020220176018A KR20230094998A (en) 2021-12-21 2022-12-15 Cache systems
US18/067,180 US20230195638A1 (en) 2021-12-21 2022-12-16 Cache systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2118624.2A GB2614069B (en) 2021-12-21 2021-12-21 Cache systems

Publications (2)

Publication Number Publication Date
GB2614069A GB2614069A (en) 2023-06-28
GB2614069B true GB2614069B (en) 2024-10-09

Family

ID=79602006

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2118624.2A Active GB2614069B (en) 2021-12-21 2021-12-21 Cache systems

Country Status (1)

Country Link
GB (1) GB2614069B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150221063A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Method for caching gpu data and data processing system therefor
US20160154739A1 (en) * 2014-12-01 2016-06-02 Samsung Electronics Co., Ltd. Display driving apparatus and cache managing method thereof
US20170256025A1 (en) * 2016-03-04 2017-09-07 Samsung Electronics Co., Ltd. Efficient low-power texture cache architecture
EP3385848A1 (en) * 2017-04-07 2018-10-10 INTEL Corporation Apparatus and method for managing data bias in a graphics processing architecture
EP3486784A1 (en) * 2017-11-20 2019-05-22 Samsung Electronics Co., Ltd. Systems and methods for efficient compressed cache line storage and handling
US10802967B1 (en) * 2019-06-28 2020-10-13 Intel Corporation Partial write management in a multi-tiled compute engine
US20210216464A1 (en) * 2020-01-14 2021-07-15 Arm Limited Cache operations in data processing systems

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8990518B2 (en) 2011-08-04 2015-03-24 Arm Limited Methods of and apparatus for storing data in memory in data processing systems
US9116790B2 (en) 2011-08-04 2015-08-25 Arm Limited Methods of and apparatus for storing data in memory in data processing systems
GB2579568B (en) 2018-12-03 2022-04-27 Advanced Risc Mach Ltd Encoding data arrays

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150221063A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Method for caching gpu data and data processing system therefor
US20160154739A1 (en) * 2014-12-01 2016-06-02 Samsung Electronics Co., Ltd. Display driving apparatus and cache managing method thereof
US20170256025A1 (en) * 2016-03-04 2017-09-07 Samsung Electronics Co., Ltd. Efficient low-power texture cache architecture
EP3385848A1 (en) * 2017-04-07 2018-10-10 INTEL Corporation Apparatus and method for managing data bias in a graphics processing architecture
EP3486784A1 (en) * 2017-11-20 2019-05-22 Samsung Electronics Co., Ltd. Systems and methods for efficient compressed cache line storage and handling
US10802967B1 (en) * 2019-06-28 2020-10-13 Intel Corporation Partial write management in a multi-tiled compute engine
US20210216464A1 (en) * 2020-01-14 2021-07-15 Arm Limited Cache operations in data processing systems

Also Published As

Publication number Publication date
GB2614069A (en) 2023-06-28

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