[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

GB2598226B - Cache arrangement for graphics processing systems - Google Patents

Cache arrangement for graphics processing systems Download PDF

Info

Publication number
GB2598226B
GB2598226B GB2114513.1A GB202114513A GB2598226B GB 2598226 B GB2598226 B GB 2598226B GB 202114513 A GB202114513 A GB 202114513A GB 2598226 B GB2598226 B GB 2598226B
Authority
GB
United Kingdom
Prior art keywords
graphics processing
processing systems
cache arrangement
cache
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2114513.1A
Other versions
GB202114513D0 (en
GB2598226A (en
Inventor
Henrik Uhrenholt Olof
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to GB2114513.1A priority Critical patent/GB2598226B/en
Priority claimed from GB1907828.6A external-priority patent/GB2584440B/en
Publication of GB202114513D0 publication Critical patent/GB202114513D0/en
Publication of GB2598226A publication Critical patent/GB2598226A/en
Application granted granted Critical
Publication of GB2598226B publication Critical patent/GB2598226B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB2114513.1A 2019-06-03 2019-06-03 Cache arrangement for graphics processing systems Active GB2598226B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2114513.1A GB2598226B (en) 2019-06-03 2019-06-03 Cache arrangement for graphics processing systems

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB2114513.1A GB2598226B (en) 2019-06-03 2019-06-03 Cache arrangement for graphics processing systems
GB1907828.6A GB2584440B (en) 2019-06-03 2019-06-03 Cache arrangement for graphics processing systems

Publications (3)

Publication Number Publication Date
GB202114513D0 GB202114513D0 (en) 2021-11-24
GB2598226A GB2598226A (en) 2022-02-23
GB2598226B true GB2598226B (en) 2022-09-14

Family

ID=80001954

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2114513.1A Active GB2598226B (en) 2019-06-03 2019-06-03 Cache arrangement for graphics processing systems

Country Status (1)

Country Link
GB (1) GB2598226B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120254507A1 (en) * 2011-03-31 2012-10-04 Jichuan Chang Write-absorbing buffer for non-volatile memory
US20180349291A1 (en) * 2017-05-31 2018-12-06 Apple Inc. Cache drop feature to increase memory bandwidth and save power

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120254507A1 (en) * 2011-03-31 2012-10-04 Jichuan Chang Write-absorbing buffer for non-volatile memory
US20180349291A1 (en) * 2017-05-31 2018-12-06 Apple Inc. Cache drop feature to increase memory bandwidth and save power

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Chao Chen et al DRAM write-only-cache for improving lifetime of phase change memory , 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 Oct. 2016, 4 pp. ISBN 978-1-5090-0916-9 *

Also Published As

Publication number Publication date
GB202114513D0 (en) 2021-11-24
GB2598226A (en) 2022-02-23

Similar Documents

Publication Publication Date Title
GB2584440B (en) Cache arrangement for graphics processing systems
GB2563688B (en) Graphics processing systems
GB2594764B (en) Graphics processing systems
GB2573543B (en) Graphics Processing
GB201711269D0 (en) Graphics processing systems
GB2578320B (en) Graphics processing
GB2571271B (en) Graphics processing
GB2580740B (en) Graphics processing systems
GB2567207B (en) Graphics processing systems
GB2595326B (en) Graphics Processing Systems
GB2578507B (en) Graphics processing
PL3389240T3 (en) Method and system for processing cache cluster service
GB2580170B (en) Transformed geometry data cache for graphics processing systems
GB2609425B (en) Graphics processing systems
GB2571979B8 (en) Graphics processing
GB2597370B (en) Transformed geometry data cache for graphics processing systems
GB2598226B (en) Cache arrangement for graphics processing systems
GB2610659B (en) Graphics processing systems
GB2614073B (en) Cache systems
GB2614069B (en) Cache systems
GB2614071B (en) Cache systems
GB2600108B (en) Graphics processing systems
GB2610919B (en) Tag buffer for graphics processing systems
EP3995220C0 (en) Processing system
GB202217232D0 (en) Graphics processing systems