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GB2403173A - Soldering refractory metal surfaces - Google Patents

Soldering refractory metal surfaces Download PDF

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Publication number
GB2403173A
GB2403173A GB0314768A GB0314768A GB2403173A GB 2403173 A GB2403173 A GB 2403173A GB 0314768 A GB0314768 A GB 0314768A GB 0314768 A GB0314768 A GB 0314768A GB 2403173 A GB2403173 A GB 2403173A
Authority
GB
United Kingdom
Prior art keywords
solder
refractory metal
layer
soldering
niobium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0314768A
Other versions
GB0314768D0 (en
Inventor
Samjid Hassan Mannan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kings College London
Original Assignee
Kings College London
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kings College London filed Critical Kings College London
Priority to GB0314768A priority Critical patent/GB2403173A/en
Publication of GB0314768D0 publication Critical patent/GB0314768D0/en
Publication of GB2403173A publication Critical patent/GB2403173A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/19—Soldering, e.g. brazing, or unsoldering taking account of the properties of the materials to be soldered
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

A barrier layer 4 for use in soldering components 1 on to a substrate 2 is a refractory metal, preferably niobium, tungsten or an alloy thereof. The refractory metal layer 4 is deposited on at least one metallic component 3, and a solder 5 is deposited onto this refractory metal layer 4 before contacting the solder with the other metallic component 6, 7. Preferably, both components include a barrier layer 4. The barrier layer 4 may be coated with a sacrificial protective coating (6, figure 2), which may be made from gold, tin, copper, platinum or palladium. The solder 5 is preferably an In/Sn solder. The method may be used to bond an electronic or micro-electronic component such as a chip, a flip-chip, a CSP or a BGA onto a substrate.

Description

536 improved method of Soldering As Fllod 24-J:n-'3 - 13 54 24031 73 - 1 -
Improved Method of Soldering This invention relates to a barrier layer for liquid solder interconnections particularly for connecting semiconductor devices to circuit boards and the invention also relates to a method of liquid soldering using such a barrier layer.
Electronic assemblies are designed to function reliably within temperature ranges from -40 C to +125 C, depending on local weather conditions and other factors such as the heat generated by the electronics. Some applications however, require the assemblies to function at higher temperatures, for example electronics situated inside a car engine, in an aeroplane, or down an oil well. Passive components, and even active semiconductor components, can in many cases function at temperatures up to 350 C. However conventional packaging materials, and in particular, the solder joints used to connect the electronic devices to the circuit board, tend to fail during operation at high temperatures.
The conventional approach to high temperature solder joints for electrical connection is to use solder materials with higher melting points than the standard Sn63/Pb37 solder which melts at 183 C (e.g. 90Pb/lOSn or 99Sn/lCu). However these joints will still be prone to strain hardening and eventual crack formation resulting in loss of electrical continuity. To address this problem in conventional electronic devices, IBM and others have patented the idea of using low melting point solders, which are molten during operation of the electronic assembly and methods are disclosed in US Patents 5170930, 5553769, 5808874, 5920125, 6202298 and 6437240. Because the joints melt during each high temperature excursion, strain hardening cannot occur, and the solder joints do not crack. However, this idea cannot be applied immediately to high temperature electronic devices because the high temperatures will encourage intermetallic growth formation between the solder and the barrier layer metals on the contact pads on the circuit board and on the component. Alternatively, if a material is chosen that does not react with the solder, then adhesion between the two materials will be minimal.
Sal improved method of Solderlng A-. Filed 24-Jl:-G'] - 1 1 54
- 2 -
We have now devised an improved method for liquid soldering using refractory metals as a barrier layer.
To be effective as a barrier layer the barrier layer must be an electrical conductor; limiting the likely possibilities to metals; the barrier layer must form a strong adhesive bond with the solder under process conditions of limited temperature and time (ruling out processes which could harm the electronics or circuit board due to excessively high temperatures, or which are too to long to be considered feasible for manufacturing economics); the barrier layer must act as a diffusion barrier between the solder and the underlying metal on the circuit board or the component; the reaction between the barrier metal and the solder must be either self limiting, or the reaction rate must be small enough not to affect long term reliability; the intermetallic layer formed between barrier metal and solder must not be brittle, must not dissolve into the solder, and must remain as a continuous layer between the barrier layer and the solder this implies that the solubility of the barrier metal in the liquid solder must be limited; deposition of the barrier layers must be possible in a manner which is consistent with electronics assembly practices, so as not to raise the cost of the assembly excessively; the barrier layers must be stable over a reasonable period of time before solder is applied e.g. formation of a non- solderable oxide layer in the presence of air must be inhibited.
The method we have devised uses a barrier layer which fulfils these criteria.
According to the invention there is provided a method for liquid soldering two metal surfaces together which method comprises placing a refractory metal layer on the surface of one metal depositing the solder onto the refractory metal layer and contacting the solder with the other metal surface.
When the refractory metal surface can form an oxide surface the refractory metal surface is protected from the atmosphere when it is formed and prior to soldering.
SD6 Imprrved method of 501derng As Flled >4-Jn-rJ - 1 1 S4 - 3 - This can be achieved by coating the refractory metal with a solderable protective surface before it gets a chance to oxidise.
The invention also provides a metal surface with a liquid solderable refractory metal layer formed on it.
The liquid solderable refractory metal surface can have a non-oxidisable protective metal layer on its surface.
The invention can be used to solder an electronic or micro-electronic component onto a substrate. The component can be a chip such as a i:1ipchip or any other micro electronic component e.g CSPs, BGAs etc. and the substrate can be any substrate used in micro-electronic circuits.
A component to be soldered to the substrate can then be soldered in any conventional way.
The preferred refractory metal is niobium. Niobium alloys can also be used e.g. alloys with titanium, tin or vanadium and these metals may be consumed at the interface.
There can also optionally be a sacrificial layer e.. of platinum which is consumed slowly. By the time the sacrificial layer or alloy component has been consumed the refractory metal layer would have had time to bond with the solder e.g. with tin in the solder. Tungsten and tantalum have been tested but require severe processing temperatures or very long processing times (months).
The preferred solder is an In/Sn solder, e.g. 52In/48Sn, 51 In/32.5Bi/1 6. 5Sn, 62.5Ga/21.5In/16Sn in general eutectic compositions are preferred.
Some refractory metals (most commonly tungsten) are routinely used as diffusion barriers in electronic assemblies. However, these metals are "non solderable" under normal circumstances and are usually covered by a further, solderable layer, and never come into contact with the solder. The use of tungsten as a barrier layer for b86 Improved method of Soldering As Filed 24-J-13 13: r'4 - 4 - liquid solder connections has been proposed, but there would be minimal adhesion between the tungsten and the solder.
Sn/Au solders have been used to solder to niobium under conditions of high temperature (320 C), however, we have now discovered that niobium remains stable in the presence of liquid solder for extended periods of time (years) and that niobium can form a strong adhesive bond with tin containing solders at relatively low temperatures and times but the use of this type of barrier layer has never been proposed for liquid phase solder joints at elevated temperatures.
The protective layer is preferably gold, but any suitably oxidation resistant metal can be used which does not adversely affect the soldering process can be used. Examples include platinum, palladium, copper, tin.
The thickness of the layers is preferably, for the refractory metal layer from 0.2 micron to 20 micron thick, and for the protective metal layer from 0.02 micron to l 0 micron thick e.g. about 2 microns.
To form the soldered joint the refractory metal must be kept at elevated temperatures in contact with the liquid solder for periods far greater than typically used during soldering. For example, conventional reflow soldering using Sn/Pb eutectic solders require soldering temperatures of 220 C, for 60seconds. In the present invention in order to form barrier layers with the required properties, soldering temperatures of 200 C must be maintained for times of 24 hours or longer, depending on the exact metal chosen, and the limits set by the other materials in the assembly.
In an embodiment of the invention the soldering process lasts at least twenty four hours in order to form a bond with the solder, unless a sacrifical element is used which forms an immediate bond with the solder and is slowly consumed while the solder is molten, allowing a bond between the refractory metal and the solder to form.
SB6 improved method of Solderlnq}9 Filed 24-Jur:-03' - 3 54 - 5 In using the method of the present invention to solder a chip to substrate the metal substrate to be coated is first cleaned e.g. in a standard way to promote adhesion to niobium. When the substrate is subject to substrate metallisation, typical metals used are copper and nickel (used as a diffusion barrier). In the case of metallisation of the chip, the metal will typically be aluminium or copper. However, many semiconductor chips will be available with a barrier metallisation already in placed.
Typically this will be nickel followed by a thin gold layer. These metal surfaces should be cleaned, first by washing in ethanol, then IPA, then rinsed with distilled water, followed by sputtering or electroplating of niobium. If sputtering is used, then a reactive ion etch is routinely used to further clean the surface of contaminants.
In the case of the component, it would be expected that a mask would be used to define the pattern of contact electrodes on the chip. This mask would be aligned with the wafer rather than individual chips for economies of scale. In the case of the substrate, a mask would be used to define the bondpads and niobium would be sputtered onto the substrate.
Once the niobium coating has been applied, the solderable protective layer must be applied. If this layer is to be sputtered onto the niobium, it is important that the niobium has not come into contact with air and allowed to oxidise, as it is difficult to clean off the oxide. If the protective layer is to be plated, then the etching step must clean olf the oxide on the niobium so that protective layer is plated onto a clean niobium surface.
The solder may now be deposited onto the surface using any standard method, as the surface is robust enough to withstand normal handling, and no special precautions need be taken. One popular method is stencil printing of solder paste, but the availability of solder pastes with In/Sn solder is limited, another method would be to sputter or evaporate the In/Sn solder onto the barrier metallisation, using the same mask pattern as used during barrier metal deposition. Electroplating is another 586 Improved method ot 51dernq As Flled 24- Jn-03. - 13 S4 6 - popular option. It might even be possible to use dip soldering, depending on the minimum volume of solder which is required.
Finally the chip must be sawn from the wafer, soldered to the substrate, and underfilled. These are all standard procedures, used in conventional flip chip assembly. However, in order to form the adhesive bond between barrier layer and solder, it will be necessary to "burn in" the assembly, e.g. leaving the assembly at 200 C for 24 hours. Given that the system is designed for operation at 200 C, this should not cause any problems, although the length of time required is significantly longer than the conventional longest step (underfilling) which lasts only 1-2 hours.
An alternative is to solder the assembly using high soldering temperatures (e.g. 300 C for 30 minutes), depending on the constraints imposed by the polymeric components of the assembly. The more severe the burn in step, the higher the initial joint adhesion.
A particular application is in flip-chip assemblies containing liquid solder joints in which the barrier layers would only be present to prevent solid state diffusion between the solder and underlying metallisation. T he main features are the electrical component (semiconductor chip), bond pads (usually aluminium or copper), circuit board (substrate), solder joints, passivation layer (e.g. glass passivation or polyimide passivation), substrate metallisation (usually Cu tracks), barrier layer on the substrate and on the device and the polymer underfill.
The function of the underfill layer, which is also used in conventional flip-chip assemblies, is to mechanically lock the electrical component to the board. The main difference between the role of the undersell in a conventional assembly and in a liquid solder assembly is that, in the former case, the underfill must stiffen the assembly throughout the temperature cycle, whereas in the latter case, stiffening is not required once the joint has become molten, though it must still mechanically join the assembly together.
sac Improved method of Soldernq As El1ed 24-J (i3 - 13 54 - 7 - It is a feature of the invention that it provides a method for soldering where adhesion is retained at low temperatures and the surface is stable against intermetallic growth at high temperatures even when one of the metals is molten or may be molten for long periods of time. In the method the initial bond can be formed at moderate temperatures and time scales compatible with electronic assembly manufacturing.
The invention is illustrated in the accompanying drawings in which Fig. l shows a cross section through a typical flip chip assembly.
Fig. 2 shows details of the barrier layer before bonding Fig. 3 shows a detail of the metal barrier after bonding to solder Fig. 4 shows a BGA connection using liquid phase solder Fig. 5 shows encapsulated electronics utilising liquid solder.
Referring to fig. 1, a semiconductor device (l) is soldered to a substrate (2). There is metallisation layer (3) on the substrate where the connection is to be made. There is niobium barrier layer (4) shown in detail in (fig. 2). The liquid solder joints (5) are formed on the niobium layer and another niobium barrier layer formed on the solder layer to which the semiconductor device (l) is soldered via passivation layer or solder mask (6) and bond pad (7).
Referring to fig. 2 this shows the sputtered or plated sacrificial protective gold coating (8) on the niobium layer.
Referring to fig. 3 this shows the thermally grown intermetallic adhesion layer (7).
Referring to fig. 4 this shows the soldering of a BGA component (lo) onto substrate (16).
Referring to fig. 5 a device (l 8) is soldered to substrate (2) and then encapsulated by encapsulating polymer ( ] 7).

Claims (25)

  1. 586 Improved method of 501derng As Flled 24-Jur,- C'1 - 13 54 - 8 - Claims
    l. A method for liquid soldering two metal surfaces together which method comprises depositing a refractory metal layer on the surface of one metal, depositing a solder which is molten during high temperature excursions of the assembly, onto the refractory metal layer and contacting the solder with the other metal surface.
  2. 2. A method as claimed in claim l in which the refractory metal has a thickness of 0.2 micron to 20 microns.
  3. 3. A method as claimed in claim l or 2 in which the refractory metal surface is protected by a layer of a solderable protective surface.
  4. 4. A method as claimed in claim 3 in which the protective layer is formed of gold, tin, copper, platinum, palladium.
  5. 5. A method as claimed in claim 3 or 4 in which the protective layer is from 0.02 micron to lO micron thick.
  6. 6. A method as claimed in any one of the preceding claims in which the refractory metals is niobium, tungsten or a niobium or tungsten alloy.
  7. 7. A method as claimed in any one of the preceding claims in which there is a sacrificial layer on the refractory metal surface which sacrificial layer is consumed.
  8. 8. A method as claimed in any one of the preceding claims in which the solder is an In/Sn solder.
  9. 9. A method as claimed in claim 8 in which the solder is selected from 521n/48Sn, 51 In/32.5Bi/l 6.5 Sn and 62.5Ga/2 1.51n/l 6Sn solders.
    506 improved method of Soldering A-. Filed 24-JI:n-Ot - l 1 54 _ 9 _
  10. l O. A method as claimed in any one of the preceding claims in which the metal surface on the substrate is a metallised surface.
  11. 11. A method as claimed in any one of the preceding claims in which refractory metal layer is deposited by sputtering or electroplating.
  12. 12. A method as claimed in any one of the preceding claims in which refractory metal surface is protected by a layer of a solderable protective surface which is deposited on the refractory metal surface before the refractory metal surface has come into contact with air and allowed to oxidise.
  13. l 3. A method as claimed in any one of the preceding claims in which an electronic or micro-electronic component is soldered to a substrate.
  14. 14. A method as claimed in claim 13 in which the component is a chip, a flip-chip or a CSP or BOA.
  15. 15. A method as claimed in any one of the preceding claims in which the solder is deposited onto the surface by stencil printing of solder paste, by sputtering or 2 0 evaporating the solder onto the refractory metal surface, electroplating or dip soldering.
  16. 16. A method as claimed in any one of the preceding claims in which the soldering process is carried out for at least twenty four hours in order to form a bond with the solder.
  17. 17. method as claimed in any one of the preceding claims in which there is a sacrifical element which forms an immediate bond with the solder and is slowly consumed while the solder is molten, allowing a bond between the refractory metal and the solder to form.
    586 Improved method of Soldering As Flled 24 JO - 1 3.54 - 10 -
  18. 18. A structure comprising a metal with a liquid solderablc refractory metal layer formed on its surface which layer is formed from a low melting point alloy which melts during high temperature excursions.
  19. 19. A structure comprising two refractory metal surfaces with a solder bond between them in which the solder is a low melting point alloy which melts during high temperature excusions.
  20. 20. A structure as claimed in claim 18 or 19 in which the refractory metal has a thickness of 0.2 micron to 20 microns.
  21. 21. A structure as claimed in any one of claims 18 to 20 in which the liquid solderable refractory metal layer has a non-oxidisable protective metal layer on its surface.
  22. 22. A structure as claimed in claim 21 in which the protective layer is formed of gold, tin, copper, platinum, palladium.
  23. 23. A structure as claimed in claim 21 or 22 in which the protective layer is from 0.02 micron to 10 micron thick.
  24. 24. A structure as claimed in any one of claims 18 to 23 in which the refractory metals is niobium, tungsten or a niobium or tungsten alloy.
  25. 25. A structure comprising a substrate on which a component is soldered by the method of any one of claims I to 17.
GB0314768A 2003-06-25 2003-06-25 Soldering refractory metal surfaces Withdrawn GB2403173A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2473285A (en) * 2009-09-08 2011-03-09 Astron Advanced Materials Ltd Low temperature joining process
US11654504B1 (en) 2021-07-14 2023-05-23 Peregrine Falcon Corporation Solid state diffusion bonding of refractory metals and their alloys

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US4321617A (en) * 1978-07-25 1982-03-23 Thomson-Csf System for soldering a semiconductor laser to a metal base
JPS59107586A (en) * 1982-12-13 1984-06-21 Nippon Telegr & Teleph Corp <Ntt> Superconductive flip chip bonding method
JPH01209747A (en) * 1988-02-17 1989-08-23 Ricoh Co Ltd Flip-chip bonding method of semiconductor chip
EP0457344A2 (en) * 1990-05-18 1991-11-21 Kabushiki Kaisha Toshiba Semiconductor light-emitting device
JPH08204244A (en) * 1995-01-26 1996-08-09 Tanaka Denshi Kogyo Kk Superconductive unit
US5622305A (en) * 1995-05-10 1997-04-22 Lucent Technologies Inc. Bonding scheme using group VB metallic layer
US6083770A (en) * 1996-12-24 2000-07-04 Matsushita Electric Works, Ltd. Thermoelectric piece and process of making the same
JP2001217275A (en) * 2000-02-03 2001-08-10 Matsushita Electric Works Ltd Flip-chip mounting structure for semiconductor device
US20020185524A1 (en) * 2001-05-30 2002-12-12 Gerneral Electric Company With Cover Sheet Bonded niobium silicide and molybdenum silicide composite articles using brazes
US20030060041A1 (en) * 2001-09-21 2003-03-27 Intel Corporation Dual-stack, ball-limiting metallurgy and method of making same

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Publication number Priority date Publication date Assignee Title
US4098452A (en) * 1975-03-31 1978-07-04 General Electric Company Lead bonding method
US4321617A (en) * 1978-07-25 1982-03-23 Thomson-Csf System for soldering a semiconductor laser to a metal base
JPS59107586A (en) * 1982-12-13 1984-06-21 Nippon Telegr & Teleph Corp <Ntt> Superconductive flip chip bonding method
JPH01209747A (en) * 1988-02-17 1989-08-23 Ricoh Co Ltd Flip-chip bonding method of semiconductor chip
EP0457344A2 (en) * 1990-05-18 1991-11-21 Kabushiki Kaisha Toshiba Semiconductor light-emitting device
JPH08204244A (en) * 1995-01-26 1996-08-09 Tanaka Denshi Kogyo Kk Superconductive unit
US5622305A (en) * 1995-05-10 1997-04-22 Lucent Technologies Inc. Bonding scheme using group VB metallic layer
US6083770A (en) * 1996-12-24 2000-07-04 Matsushita Electric Works, Ltd. Thermoelectric piece and process of making the same
JP2001217275A (en) * 2000-02-03 2001-08-10 Matsushita Electric Works Ltd Flip-chip mounting structure for semiconductor device
US20020185524A1 (en) * 2001-05-30 2002-12-12 Gerneral Electric Company With Cover Sheet Bonded niobium silicide and molybdenum silicide composite articles using brazes
US20030060041A1 (en) * 2001-09-21 2003-03-27 Intel Corporation Dual-stack, ball-limiting metallurgy and method of making same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2473285A (en) * 2009-09-08 2011-03-09 Astron Advanced Materials Ltd Low temperature joining process
US11654504B1 (en) 2021-07-14 2023-05-23 Peregrine Falcon Corporation Solid state diffusion bonding of refractory metals and their alloys

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