GB2126030A - Digital delay circuit with compensation for parameters effecting operational speed thereof - Google Patents

Abstract

An MOS integrated circuit includes compensation circuitry (10) for maintaining propagation delays through a number of MOS transistors (22) within desired limits. The compensation circuit includes circuit apparatus for monitoring the current- conduction capability of the MOS material of the integrated circuit to develop therefrom a compensation signal (Vc) that is used to vary the operating voltage of the number of MOS transistors. <IMAGE>

Description

SPECIFICATION Digital delay circuit with compensation for parameters effecting operational speed thereof Background of the invention This invention relates to a digital delay circuit comprising a number of transistors on a common substrate and compensated for parameters affecting speed of operation of the transistors, and has particular but not exclusive application to a Metal/Oxide/Semiconductor (MOS) integrated circuit color delay line.

Among the variety of methods used to generate a color signal for use in raster-scan display system, one finds particular advantage: a series connection of a number of delay elements that form a color delay line circuit. The color delay line circuit receives a color clock (reference) signal that is applied to and passed through the delaying elements. Each delaying element delays propagation of the signal applied thereto to produce a number of time-delayed replicas of the applied signal; and each delayed replica has a predetermined amount of delay relative to the color clock signal. One advantage of this method is its particular suitability for implementation with digital electronic techniques, in which the color delay line circuit is constructed from a series string of logic elements.Each of the logic elements is designed to have a predetermined amount of propagation delay from input to output, and additional logic selects one of the delayed versions of the applied color clock for use as the ultimate color signal.

The use of digital electronics for color signal generation allows one to take advantage of the benefits that accompany this technology, including low cost, low power consumption, reliability, and the capability of forming the delay line circuit, in combination with other circuit elements, on a single integrated circuit chip.

However, there exists problems-particularly where, as here, the delay times are on the order of tens of nanoseconds. For example, it is generally known that as the operating temperature of the semiconductor material changes, the propagation delays of the circuit components formed from the semiconductor material will also change.

Integrated circuit semiconductor-generating characteristics can also vary from chip to chip due to fabrication process techniques. Together, temperature and process variations can create propagation delay errors that can make an MOS integrated circuit color delay line inoperative~ unless these variations are compensated in some way. Delay line circuits comprising seriesconnected delay elements have been fabricated in Metal/Oxide/Semiconductor (MOS) integrated circuit form to operate in response to a color clock signal of 3.58 MHz for producing fourteen potential color signals, each time-related (or, more accurately, phase-related) to the color clock.

Each delay element is designed to produce a desired propagation delay of 20 nanoseconds (T/1 4=1/f/i 4 or 280 ns/14). However, temperature variations will cause propagation delays of the circuit elements that make up the delay elements to also vary, affecting the propagation delay of each delay element an unacceptable amount. Further, the particular process used to fabricate MOS integrated circuits can affect the threshold voltages of the MOS transistors from which the delay elements are constructed. This threshold voltage variation (from integrated circuit chip to integrated circuit chip) can also affect the propagation delay through any particular delay element. Further still, fluctuations in the supply voltage applied to the integrated circuit chip can also affect propagation delays of the MOS transistors on the chip.

Process variations can be controlled, to an extent, using costly fabrication techniques.

Alternatively, or in addition, propagation delay compensation caused by temperature and process variations has been attempted adding an external variable resistor to the MOS integrated circuit. The variable resistor functions to set the operating voltage applied to the individual MOS transistors that perform the actual signal delaying function. Final inspection of the unit incorporating the color delay line would include adjustment of the variable resistor to set the operating voltage of the MOS transistors at a value that allows the color delay line to perform adequately, and hopefully without too much problem, for moderate operating temperature variations and supply voltage fluctuations.Adding selfcompensating capability for temperature, process, and supply voltage variations to the chip itself, however, would delete a (somewhat) costly part (i.e., the variable resistor), together with the necessary wiring, and obviate the labor costs attendant with wiring the variable resistor into the circuit and the adjustment procedure.

Yet another technique is directed to developing a substrate bias voltage that is applied to the substrate of the integrated circuit to compensate for transistor threshold voltage variations caused by fabrication nonuniformities. Examples of this type of technique may be found in U.S. Patent Nos. 3,609,414,3,806,741 and 4,049,980. This technique does not provide compensation for temperature variations-except insofar as variations in temperature will result in threshold voltage changes.

But there still remains a problem of propagation delay accumulation-even under the best of conditions. If it is desired, for example, to provide fourteen available signals from which the color signal is obtained, current color delay lines of the type under consideration here would use thirteen delay elements. If each delay element introduces an additional one (1) nanosecond delay because of an operating temperature change, for example, from that encountered during adjustment, the signal provided by the last or thirtheenth delay will be in error by 13 nanoseconds.

Summary of the invention Accordingly, the present invention provides circuitry that can be implemented on the same MOS integrated circuit chip that incorporates the color delay line to compensate for temperature, fabrication process, and supply voltage variations in order to maintain the propagation delays of the individual stages of the color delay line within acceptable limits. Generally, the invention operates to monitor the current-producing capability of the MOS integrated circuit material to develop a compensation signal that is indicative thereof. The compensation signal is applied to, and controls, a voltage coupling circuit that provides the operating voltage to the individual MOS transistors of the color delay line stages.As the operating temperature varies, for example, the compensation signal will also vary, in turn modifying the operating voltage to maintain the propagation delay of each transistor forming the color delay line within a desire limit.

Similar variations of the compensation signal occur in response to process-caused transistor threshold voltage variations and/or supply voltage variations.

In the preferred embodiment of the invention, the mobility of the majority charge carrier of the MOS integrated circuit is continuously.monitored by charging a capacitor for a known period of time through an MOS transistor. The voltage to which the capacitor is charged provides an indication of the MOS material mobility. From this voltage is derived a compensation signal that is applied to the control input gates of MOS transistor circuits that operate to deliver an operating voltage to the individual delay transistors.As the operating temperature, threshold voltage, supply voltage, or any combination thereof varies, the compensation signal will also vary in turn varying the operating voltage of the delay transistors in a manner that compensates for such operating parameter variations to maintain the propagation delays of the delay transistors within acceptable limits.

In an alternate embodiment of the present invention, the possibility of accumulating propagation delay errors is cut in half by using a controllable inverter circuit that passes either the true or an inverted version of the signal ultimately provided by the color delay line. For example, a color signal having a relative phase shift (to the color clock) of N can be represented as NO for 1800 TN 10 or N for 1800 < N < 3600. Thus, if the capability of providing fourteen different color signals is desired, only six delay stages and the controllable inverter need be used. The delay accumulation factor will be six (6), as opposed to thirteen (13) in a delay line circuit having thirteen individual delay stages.

A number of advantages are obtained by providing such self-compensating techniques.

Fabrication costs are reduced by deleting external parts (i.e., the variable resistor), their cost, wiring costs and labor costs that were heretofore added to set the operating voltage of the delay transistors at a level that would compensate for process variations.

Further, temperature, process, and supply voltage variation compensation is provided. The ultimate result is a color delay line having propagation delays that are kept within predetermined and acceptable limits.

Propagation delay accumulation errors that do exist are cut in half by the inverting technique.

These and further advantages of the present invention will become apparent upon reading of the following detailed description of the invention, which is to be taken in conjunction with the accompanying drawings.

Brief description of the drawings Fig. 1 is a block diagram of the present invention used to compensate a six-stage color delay line; Fig. 2 illustrates, in greater detail, the mobility detection circuit and linear amplifier used to provide the compensation signal that is applied to the color delay line; Fig. 3A is a logic block diagram of a timing circuit used to operate the mobility detection circuit illustrated in Fig. 2; Fig. 3B is the timing diagram of the circuit of Fig. 3A; Fig. 4 is a logic diagram of the color delay line, illustrating the individual, series-connected elements that make up the color delay line; Fig. 5 is a circuit diagram of one of the delay elements of the color delay line; and Fig. 6 is a circuit diagram of the controllable inverter used to ultimately generate the color signal.

Detailed description of the invention The time it takes for a signal applied to the input (gate lead) of an MOS transistor to appear at an output point of that transistor is a function of a number of factors, including the transistor's operating voltage, operating temperature and threshold voltage (which also varies with temperature). For example, if the operating temperature of the transistor varies from OOC. to 1000C., the signal propagation time of the transistor will correspondingly vary from a lower to a higher value, i.e., the transistor slows down as its operating temperature increases. This is so because the mobility of the majority charge carrier of the MOS transistor material is inversely proportional to operating temperature.

But, other factors effect the signal propagation delay of the transistor. When part of an integrated circuit chip, the MOS transistors' threshold voltage of one chip can be higher or lower than that of another chip, a difference that is caused by the process variations encountered in fabricating the integrated circuit chip. An MOS transistor exhibiting a high threshold voltage will exhibit higher signal propagation delay than a transistor having a lower threshold voltage. Too, threshold voltage is affected somewhat by operating temperature variations-which, in turn, affects signal propagation delay.

These variations, however, also exhibit themselves in the current produced by an MOS transistor. Thus, the present invention monitors the current of an MOS transistor of an integrated circuit by charging a capacitor to obtain a voltage that is indicative of operating temperature, supply voltage, and threshold voltage of the particular MOS integrated circuit chip at the particular time.

If operating parameters are such that the MOS transistors of the delay elements that comprise a color delay line formed on the chip are operating too fast, the voltage across the charged capacitor is used to form a compensation signal that slows down transistor speed-by lowering the operating voltages of the delay element transistors. Conversely, if the current-conducting capability of the chip's MOS material is too low (causing transistor propagation to also be low), because of particular values of operating parameters, the delay element transistor operating voltage will be caused by the compensation signal to be increased to speed up delay element transistor operation.

Referring now to Fig.1, there is illustrated a self-compensated color delay line circuit designated generally with the reference numeral 8, and shown as including a compensation circuit 10. The compensation circuit 10 includes a current monitor 12 and a linear amplifier 14. A color clock (CC) signal is received at an input terminal 1 8 of the compensation circuit 10 and applied to the current monitor 12 for timing functions which will be described below.

The output of the compensation circuit 10 is a compensation signal (Vc) that is conducted by signal line 20 to a six-stage color delay line 22.

The six-stage color delay line 22 receives at its clock (CLK) input, via the signal line 24, the CC signal. In response to the received CC signal, the six-stage color delay line 22 operates to produce six delay signals, all of which are related to the received CC signal by a predetermined time (phase) relationship. The six-stage color delay line 22 provides, on a corresponding one of the output signal lines 26a-26g, a selected one of seven available output signals: the CC signal itself or one of its six delayed replicas. Selection is made by internal logic of the six-stage color delay line 22. The selected signal is then conducted to a controllable inverter 28 which passes, to amplifier 40, the true version of the applied signal or its complemented (inverted or 1800 phase-shifted) version.

A four-bit color register 30 receives from a data bus 31 four bits of binary information which, when decoded, will cause to be selected the one of seven available signals provided by the sixstage color delay line 22. The four bit content in the color register 30 is applied to a color code decoder 32 for decoding. The color code decoder 32 has eight individual outputs. Seven of the outputs are coupled and applied to the six-stage color delay line 22 by signal lines 36 and used for selecting one of the output signals produced by the delay line 22. The eighth output of the color code decoder is conducted by a single signal line 38 to a selection (SEL) input of the controllable inverter 28 and used to select the true or inverted version of the applied delay line signal.

Shown in Fig. 2 is the circuit diagram of the current monitor circuit 12, and the linear amplifier 14. As illustrated, the current monitor circuit 12 comprises MOS transistors Q1 and Q2 connected in series fashion between the supply voltage Vcc and ground G, with the drain lead D1 of transistor Q1 connected to Vcc and the source lead S2 of the transistor Q2 connected to ground G. The respective gate leads G1 and G2 of the transistors Q1 and Q2 are connected to a timing circuit (50~Fig.3) for receiving timing signals TC1 and TC2. The connection between transistors Q1, Q2 is connected to one lead of a capacitor C1, and to a drain lead D3 of a transistor Q3. The remaining lead of capacitor C1 is connected to ground.The gate G3 of transistor Q3 receives a timing signal TC3 from the timing circuit 50. The source lead S3 of the transistor Q3 is connected to one lead of a capacitor C2, the other lead of which is connected to ground.

The current monitor circuit 12 functions to charge capacitors C1 and C2 to a voltage that is indicative of majority charge-carrier mobility, transistor threshold voltage and the supply voltage (Vcc) of the integrated circuit chip carrying the color delay line circuit 8 in the following manner: Timing signals TC 1, TC2 and TC3 are applied to allow the capacitor C1 to charge for a predetermined time. During charging, the transistor Q1 is in a conducting state (i.e., "turned on") while the transistors Q2 and Q3 are in nonconducting states ("turned off"). The transistor Q1 is then turned off and transistor Q3 turned on to cause the capacitor C2 to be charged to the same voltage as the capacitor C1.The transistor Q3 is then turned off, transistor Q2 turned on and capacitor C1 allowed to discharge.

The voltage across capacitor C2 is coupled to the linear amplifier 14 and applied to a gate lead G4 of a transistor 04. The drain lead D4 of transistor Q4 is connected to Vcc by a resistor R1, and the source lead S4 of the transistor is connected to ground through resistor R2. The output stage of the linear amplifier 14 is formed by an MOS transistor stack comprising four enhancement transistors Q5-Q8 and a depletion transistor Q9-which functions as a load transistor for the stack. As can be seen, the transistors Q5-Q9 are connected between Vcc and ground in series fashion, and the source lead of each immediate upper transistor (as viewed in Fig. 2) is connected to the lower transistor. The drain of transistor Q9 is connected to Vcc and the source of transistor Q8 is connected to ground. In addition, the gate lead of each of the transistors Q5-Q8 are connected to the drain of that transistor, and the gate lead of the transistor Q9 is connected to its source. The connection between transistors Q5 and Q9 connects to the drain of transistor Q4, to signal line 20, and develops the compensation signal Vc.

As indicated, the voltage across capacitor C2 will provide a close indication of the parameters that affect propagation delay of an MOS transistor. For example, under possible extreme conditions of high temperature, high transistor threshold voltage, and decreased Vcc, MOS transistor speed will be slow, as will be its current-conducting capability. Thus, a low current will result in a low voltage to which capacitor C1 (and capacitor C2) will be charged during the time allotted by timing signal TC 1. The MOS transistors of the color delay line 22 that effect actual signal delay will require, under these conditions, an increased operating voltage to speed them up, so to speak, to compensate.

When conditions change to some other extreme, causing the MOS transistors forming the color delay line 22 to operate faster, the applied operating voltage must be decreased to slow down transistor operation. The compensation signal must obtain the necessary voltage levels for causing proper compensation of the color delay line 22 at these (and other) extremes, and operate in a linear fashion in between.

For purposes that will be described below, the compensation signal must be at a high level when the voltage across C2 is low (indicating increased propagation delay), and be at a low level when voltage across C2 is high (indicating decreased propagation delay).

It has been found that an MOS integrated circuit chip constructed and operated within certain parameter ranges will cause the voltage across C2 to vary between 1.08 volts (indicating the lower current-conducting extreme) and 2.32 volts (the high current-conducting extreme).

Those parameter ranges are: 4.75V < =Vcc < 5.25 489 < =# < #805 O.6SV < =Vth < i.15V 00C. < T < 1 000C.

where Vcc is the supply voltage applied to the chip; ,u is the majority charge carrier mobility at OOC, and 1000C.; Vth is the MOS transistor threshold voltage of the chip at 250C.; and T is temperature.

It has also been found that a color delay line can be constructed having individual delay elements that each provide a 20 nanosecond that will vary no more than 2 nanoseconds over the parameter range specified above provided the compensation voltage varies linearly from supply voltage to 2.3 volts when voltage across C2 varies from 1.08 volts to 2.32 volts. This is the function of the linear amplifier 14.

For the most part, the circuit comprising resistors R1 and R2 and transistor Q4 operates quite nicely to linearly convert voltages in the range of 1.08 volts to 2.32 volts to voltages in the range of supply voltage to 2.3 volts, respectively, when all parameters are as set forth above-with one exception: When the operating temperature is in the vicinity of 1000C and the threshold voltage, Vth, around the low end of specification (i.e., 0.65 volts at 250C) a problem occurs. This high operating temperature produces a low majority charge carrier mobility, causing the delay line transistors to operate slower. Vc, as derived from charging capacitor C1, will be high.

However, the low threshold voltage (0.65 volts, which will drop even lower with increased temperature) operates to increase or speed up operation of the transistors of the delay line circuit 22-at the same time that the compensating voltage, Vc is attempting to also effect an increase in operation of the transistors of the delay line circuit 22. Thus, the compensation voltage must be pulled down by an amount proportional to the low threshold voltage. This is the function of the transistor stack. It is only under these extreme conditions-high temperatures (causing Vc to be high) and low threshold voltage, that the transistors Q5-Q8 will conduct. Their conduction, in turn, loads the output of the linear amplifier 14, pulling the compensation voltage down to a value more appropriate (approximately 2.6 volts).

One further design aspect of linear amplifier 14 must be noted. The ratio of resistor R1 to resistor R2 should be on the order of 2.1 7-2.5, and the resistor R1 should be a relatively low value (i.e., 5K~1OK ohms) to allow some voltage division interplay between resistor R1 and the transistor stack Q5-Q9 to occur when transistors Q5-Q8 of the stack conduct-as described above.

In the preferred construction, the following fabrication component and design values were used: 1. The nominal width to length (w/l) ratios for the transistors 01--Q13 are: 01=20/40 Q2=50/3.5 03=3.5/3.5 Q4=500/10 Q5=Q6=Q7=Q8=300/4 09=4/310 010=5/22 at 1=5/18 Q12=50/4 013=50/4 2. Nominal capacitance values are: C1=11.8 pf C2=4.5 pf 3. Nominal resistance values are: R1=8.220K ohms R2=3.285K ohms The timing signals TC1, TC2 and TC3 are developed by the timing circuit 50, illustrated in Fig. 3A. As shown, timing circuit 50 comprises a four-state counter 52, a state decoder 54, and two delay elements 56 and 58.In operation, the four-state counter 52 receives the CC signal that is applied to the current monitor circuit 12 (Fig. 1) to sequence through four binary states. State decoder 54 receives the two output lines 55, 57 of the four-state counter 52 and generates the timing signal TIC 1 when a predetermined one of the four states is assumed. The timing signal TC1 is applied to delay network 56 which delays the timing signal TC1 by an amount T1 to produce the timing signal TC3. Timing signal TC3 is, in turn, applied to delay element 58 and delayed for T2 to produce timing signal TC2.

The timing signals TC1, TC2 and TC3 are illustrated in Fig. 38. In particular, it should be noted that there exists a spacing (of a few nanoseconds) between the fall time (ft1) of timing signal TC1 and the rise time (rt2) of timing signal TC2. Similar spacing between fall and rise times of timing signals TC2, TC3 and TC3, TC 1 exist.

This spacing is necessary in order to prevent overlap between conduction of any of the transistors Q1, Q2 and Q3 during their sequence of operation.

The six-stage color delay line 22 is illustrated in greater detail in Fig. 4 as being formed from six series-connected delay elements 60-70 and seven two-input AND gates 72-84. The delay element 60 receives at its input the CC signal via signal line 24. The output of delay element 60 is coupled to input of the following delay element 62, the output of which is, in turn, coupled to the next following delay element 64, and so on down the line to delay element 70. The CC signal and the output of each of the delay elements 60-70 are each applied to one input of a corresponding one of the two-input AND gates 72-84. Applied to the remaining input of each of the AND gates 72-84 is one of the seven signal lines 36.The outputs of the AND gates 72-84 are connected to signal lines 26a-26g.

Fig.5 illustrates the circuit configuration of the delay element 60. The remaining delay elements 62-70 are identically constructed and, therefore, any discussion of the delay element 60 will apply equally to the remaining delay elements 62-70.

The delay element 60 is shown as including inverter stages 60a and 60b, each stage having a "pull-up" transistor and a "pull-down" transistor.

The pull-down transistors function as the signal delaying device while the pull-up transistors function as a controllable source of the operating voltage applied to the pull-down transistors. Thus, the inverter stages 60a and 60b respectively.

comprise pull-up transistors Q10 and Q11 which provide the operating voltage to the "pull-down" transistors Q12 and 013. Transistors 012 and Q13 together provide the overall single propagation delay of the delay elements 60. The transistors Q10 and Q11 have their drain leads connected to Vcc; their source leads connected to the respective drain leads of transistors Q12 and 013. The signal to be delayed, here the CC signal, is applied to the gate of the first pull-down transistor Q12 of the delay 60, and ultimately appears at the output 60c in its delayed form.The amount of the delay provided by transistors Q12, 013 is a function of a variety of factors, as discussed, and can be further modified by proper control of the operating voltages applied.

Accordingly, these operating voltages of transistors Q12,Q13, are controlled by the compensation signal Vc through the pull-up transistors 010 and Q11 in the following manner: If conditions (i.e., operating temperature, threshold voltage, etc.) are such that transistors Q12 and 013 operate at an increased speed, resulting in lower than the desired propagation delay (20 nanoseconds), the voltage across C2 will so indicate by being higher than normal. In turn, the compensation signal Vc will be reduced which, when applied to the gate leads of the transistors Q10 and 011, will cause current conduction of these transistors, and therefore the operating voltage they supply to transistors Q12 and Q13, to decrease.This decreased operating voltage will, in turn, reduce the operating speed of transistors Q12 and Q13 by an amount approximately equal to the operating speed increase caused by the charge carrier mobility increase.

Conversely, if operating conditions cause the majority charge-causing to decrease, in turn reducing the speed of operation of transistors Q12 and Q13, resulting in higher propagation delay, and the rate at which capacitor C1 is charged will also decrease, and the voltage attained across the capacitor (during the conduction time of the transistor Cl-Fig. 2) will be lower.The voltage attained by the capacitor C1 is sampled and the sample transferred to the capacitor C2, applied to the linear amplifier 14 to become the compensation signal Vc (and a higher value) that, when applied to the gate leads of the transistors Q10, Q1 1, increases their conduction and the operating voltage applied to the transistors 012, 013. This increase in operating voltage will increase the operating speed of transistors 012 and 013 to compensate for the decrease in operating speed caused by the thenexisting operating conditions (such as, for example, a temperature-affected charge carrier mobility decline).

Often, it is a requirement that there be available the capability of generating a number of delayed replicas of a color clock, each representing a predetermined color, from which one or another can be selected as the color signal.

For example, the apparatus of Fig. 1 is capable of providing fourteen (14) different color signals (the color clock CC, its mirror image, and twelve timedelayed versions thereof, each delayed signal being coded by its phase shift relative to the color clock (CC) signal. This phase shift will be between 0 and 3600. Recognizing that one-half of the delayed signals have relative phase shifts in the range of 0 to 1 800, that the other one-half of the signals with relative phase shifts in the range of 180 ~360 , and that each of the first one-half of delayed signals will have a mirror image (i.e., a 1 800 phase-shifted) signal in the second one half of signals, the number of the delay elements used to construct a color delay line can be cut in half.Implementation of this concept is found in the use of the controllable inverter 28 (Fig. 1), which is illustrated in greater detail in Fig. 6.

Referring now to Fig. 6, the controllable inverter 28 is shown as including inverters 90 and 92 and transistor switches 94, 96. The output of the six-stage color delay line 22 is conducted to the controllable inverter 28 via the signal line 29 and applied to the input of inverter 90 and to the transistor switch 94. The output of the inverter 90 is coupled to the output line 42 via the transistor switch 96. Transistor switches 94 and 96 of the controllable inverter 28 are operated by the signal communicated to the SEL input from the color code decoder 32 (Fig.1) via the signal line 38. A logic ONE at the SEL input will "close" the transistor switch 94, "open" the transistor switch 96, causing the signal then present on signal line 29 to appear in its true form at the output signal line 42.Conversely, a logic ZERO applied to the SEL input of the controllable inverter 28 will open the transistor switch 94, close the transistor switch 96 and provide the complement (or 1 800 phase-shifted version) of the signal present on the signal line 92 at the signal line 42.

Thus, the controllable inverter 28 functions not only to reduce the number of delay line elements, but to cut the amount of temperature-change induced propagation error that may be exhibited by delay signals provided by delay elements located at the end of the series. For example, if each delay element introduces an additional 2 nanosecond propagation delay, a colour delay line circuit using a series of twelve delay elements will provide a final delay signal having a 24 nanosecond error. With the controllable inverter of the present invention, this error is cut in half.

In summary, the disclosed invention provides apparatus that compensates for propagation delays caused by process variations, operating temperature variations, and supply voltage fluctuations experienced by color delay line circuitry formed on an MOS integrated circuit chip. Although the invention has been described above in considerable detail with reference to several possible embodiments, including the preferred specifications for fabricating the MOS integrated circuit chip carrying both the color delay line circuit and the compensating apparatus, it should be appreciated that the scope of the invention is to be determined solely with reference to the following appended claims.

Claims (23)

Claims

1. A digital delay circuit comprising a number of transistors integrated on a common substrate, the delay circuit being compensated for parameters affecting the speed of the transistors and comprising: a plurality of cascaded inverter circuits, each inverter circuit comprising first and second transistors serially coupled across a source of supply voltage, the gate of the first transistor couped to a first conductor to receive a bias voltage, one inverter circuit having a gate of the second transistor coupled to a source of clock signals, and the other inverter circuits each having the gate of the second transistor coupled to the connection between the first and second transistor of another inverter circuit;; bias means including a first reference transistor on the common substrate for providing the bias voltage, the amplitude of the bias voltage varying inversely with respect to the mobility of the reference transistor.

2. A digital delay circuit as in claim 1 wherein the bias means further comprises compensation means comprising a second reference transistor for varying the amplitude of the bias voltage inversely with respect to the threshold voltage of the second reference transistor.

3. A digital delay circuit as in claim 2 wherein the compensation means varies the bias voltage only in response to the bias voltage having an amplitude greater than a compensation threshold wherein the compensation threshold has an amplitude which varies directly with respect to the threshold voltage.

4. A digital delay circuit as in claim 2 wherein the compensation means varies the bias voltage only in response to a low threshold voltage compensation with low mobility.

5. A digital delay circuit as in claim 3 wherein the bias means comprises means for detecting the charge transferred by the first reference transistor during each of a number of periodic clock periods.

6. A digital delay circuit as in claim 5 wherein the compensation means comprises a plurality of compensation transistors serially coupled between the first conductor and ground, the gates of each compensation transistor coupled to its drain.

7. A digital delay circuit as in claim 6 wherein the bias means further comprises a first capacitor coupled to the first reference transistor for storing the charge transferred by the first reference transistor and a second capacitor coupled to periodically sample the charge on the first capacitor, means for periodically discharging the first capacitor; and an inverter circuit-comprising a resistive device coupled in series between the first conductor and the source of a supply voltage and an inversion transistor serially coupled between the first conductor and ground, the gate of the inversion transistor coupled to the second capacitor.

8. A digital delay circuit as in claim 7 further comprising means coupled to each of the cascaded inverter circuits for inverting the delayed clock signals provided by a number of the cascaded inverters.

9. in an MOS semiconductor integrated circuit having a color delay line including a plurality of MOS transistors, a number of which form a circuit of the type including a plurality of seriesconnected signal delaying elements for receiving a clock signal and for producing therefrom a number of time-delayed versions of the clock signal, each of the delaying elements including a controllable voltage coupling device for receiving a supply voltage and for producing therefrom an operating voltage and at least one of the number of MOS transistors of such delay element having operable to receive and delay an applied signal by an amount determined in part by the operating voltage, apparatus for compensating for propagation delay changes of the signal propagation delay device caused by variations in operating temperature of the integrated circuit, the apparatus comprising:: means for developing a compensation signal indicative of the current-conducting capability of the MOS integrated circuit; and means coupling the compensation signal to the controllable voltage coupling device, the controllable voltage coupling device being responsive to the compensation signal for varying the operating voltage.

10. The apparatus of claim 9, the compensation signal developing means including voltage inverting means for producing the compensation signal.

11. The apparatus of claim 9, wherein the developing means includes a first capacitor and a first circuit means for charging the first capacitor through a first MOS transistor for predetermined period of time to a first voltage, and second circuit means coupled to the first capacitor for receiving the first voltage and for converting the first voltage to the compensation signal.

12. The apparatus of claim 11, wherein the second circuit means includes voltage inverting means for receiving the first voltage and for providing therefrom the compensation signal.

13. The apparatus of claim ii, wherein the second circuit means includes a second capacitor, and third circuit means for transferring the first voltage from the first capacitor to the second capacitor, fourth circuit means for periodically discharging the first capacitor; and wherein the developing means further includes control means for sequentially operating the first, third and fourth circuit means to periodically (1) charge the first capacitor to the first voltage, (2) transfer the first voltage to the second capacitor, and (3) discharge the first capacitor.

14. In an integrated MOS semiconductor chip having at least one input terminal for receiving a supply voltage and, a plurality of MOS transistors interconnected to form a functional electronic circuit operable in response to an operating voltage, apparatus formed on the semi-conductor chip for compensating for operational condition variation effects on the current-conducting capability of the plurality of MOS transistors, the apparatus comprising: a first MOS transistor for producing a current; first circuit means coupled to the first MOS transistor for monitoring the current and for producing therefrom a voltage indicative of the current-conducting capability; second circuit means coupled to the first circuit means and respnsive to said voltage to form therefrom a compensation signal; and voltage coupling means interconnecting the input terminal and the plurality of MOS transistors for supplying the operating voltage thereto, the voltage coupling means including a control input for receiving the control signal and means responsive to the control signal for varying the operating voltage.

15. The apparatus of claim 14, the first circuit means including capacitor means for receiving the current and producing the first voltage.

16. In an MOS integrated semiconductor circuit chip fabricated to have a predetermined range of operating characteristics, including majority charge carrier mobility, temperature, and MOS transistor threshold voltage, and having formed thereon at least one electronic circuit and input means for receiving a supply voltage, the one electronic circuit including at least a first MOS transistor operable from an operating voltage to have a predetermined speed of operation, apparatus for compensating for the effect of operating characteristic variations on the speed of operation, the apparatus comprising:: monitoring means for providing a compensation signal indicative of the currentproducing capability of a second MOS transistor, the monitoring means including a capacitor and current providing means, including the second MOS transistor, for charging the capacitor to a first voltage for a predetermined time period and means coupled to the capacitor for producing the compensation signal from the first voltage; and controllable voltage providing means coupling the input means to the MOS transistor for supplying the operating voltage thereto and having a control input for receiving the compensation signal, the voltage providing means being responsive to the compensation signal to vary the operating voltage in inverse response to variations in the compensation signal.

17. A self-compensating color delay line circuit formed on an MOS semiconductor chip operable in response to a supply voltage applied to a first input terminal and a color clock signal applied to a second input terminal of the semiconductor chip for providing a color signal, the circuit comprising: : delay line means coupled to the second input terminal and responsive to the color clock signal for producing a plurality of delay signals having a predetermined phase relation to the color clock signal, the delay line means including a plurality of MOS transistors operable from an operating voltage for providing the delay signals; detection means for providing a compensation signal indicative of the charge carrier mobility of the MOS semiconductor chip;; voltage varying means coupled to the first input and to the plurality of the MOS transistors for receiving the supply voltage and deriving therefrom the operating voltage applied to the plurality of MOS transistors, the voltage varying means including a control input for receiving the compensation signal and means connected to the control input to vary the supply voltage in response to the control signal to provide said operating voltage.

18. The apparatus of claim 17, including voltage compensation means intercoupling the detection means and the voltage varying means.

19. The apparatus of claim 17, the delay time means including means for selecting a one of the predetermined delay signals.

20. The apparatus of claim 19, including means for receiving the selected one of the predetermined delay signals and for selectively conducting the selected delay signal on a complemented form of the selected delay signal to an output terminal as the color signal.

21. A digital delay circuit compensated for variations in an operating parameter, comprising a plurality of series connected signal delay elements each element including semiconductor switching means defining a switchable current flow path which is connected across a source of operating voltage, the switching means having an input for controlling the switched state of the path, the delay time of the element being determined by the time taken for the switching means to operate in response to a signal to the input thereof, and the delay time being a function of the operating parameter and the operating voltage, the switching means of the elements being formed on a common semiconductor substrate, and compensating means including a semiconductor device formed on said substrate, means for producing a bias signal indicative of the current conducting capability of the semiconductor device, and means for controlling the operating voltage as a function of said bias signal and in such a manner as to compensate the delay times of the elements for changes in the operating parameter.

22. A digital delay circuit according to claim 21 wherein said parameter is temperative.

23. A digital delay circuit substantially as herein described with reference to the accompanying drawings.