GB1444067A - Control arrangement - Google Patents

Abstract

1444067 Data processing; timing system INTERNATIONAL STANDARD ELECTRIC CORP 11 July 1974 [13 July 1973] 30698/74 Heading G4A [Also in Division H3] In an arrangement in which a pair of first devices each supply a train of first pulses for use in the control of a respective second device each first device further supplies a train of second pulses to the other first device and each first device further includes control logic circuitry which permits a received second pulse to be used to control its associated second device in place of a locally generated first pulse, if a said second pulse is received within a predetermined time interval before a said first pulse is due to be generated. In the embodiment the first devices are pulse generator circuits SD1, SD2 each supplying synchronization pulses SYNC2, STOC<SP>1</SP>2 to a respective one of a pair of computers CO 1 , CO 2 controlling a telephone exchange. No details of the computers or telephone network are given. Each pulse generator (Fig. 2, not shown) comprises a source of clock pulses and a counter which for every 1000 clock pulses produces an output pulse CRO1 (CRO<SP>1</SP>1) (Fig. 5). Alternate ones of the CRO1 (CRO<SP>1</SP>1) pulses are used to produce the second train of pulses SYNC1, (SYNC<SP>1</SP>1) which are supplied to the other generator, the two generators differing only in that in generator SD1 the SYNC2 pulses follow the SYNC1 pulses by 10 Ás., whereas in generator SD2 the SYNC<SP>1</SP>2 pulses follow the SYNC<SP>1</SP>1 pulses by 10Ás. + 5ms. This ensures that there is no conflict between the two computers if they are running in perfect synchronism i.e. the SYNC1 and SYNC<SP>1</SP>1 pulses coincide. If, when the two computers are running, a SYNC<SP>1</SP>1 pulse is received in generator SD1 within 10 clock pulses of pulse CRO1 being produced, the logic circuitry causes the counter to be reset and uses the received SYNC<SP>1</SP>1 pulses to produce a SYNC2 pulse, the SYNC1 pulse being inhibited. Hence if one generator is only slightly faster than the other it controls both computers but if it is too fast, the computers are allowed to run out of synchronism. When one generator is switched on with the other generator already running, the counting of clock pulses is inhibited for a predetermined period during which time the receipt of a SYNC1 (SYNC<SP>1</SP>1) pulse sets the counter going and causes the production of the first SYNC2 (SYNC<SP>1</SP>2) pulse. If, however, a pulse is not received within the predetermined time, the counter is then started and the computers run out of synchronism.