[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

ES428221A1 - Control arrangement - Google Patents

Control arrangement

Info

Publication number
ES428221A1
ES428221A1 ES428221A ES428221A ES428221A1 ES 428221 A1 ES428221 A1 ES 428221A1 ES 428221 A ES428221 A ES 428221A ES 428221 A ES428221 A ES 428221A ES 428221 A1 ES428221 A1 ES 428221A1
Authority
ES
Spain
Prior art keywords
control
signal
control device
cro1
sync
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES428221A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES428221A1 publication Critical patent/ES428221A1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Feedback Control In General (AREA)
  • Hardware Redundancy (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Lubrication Of Internal Combustion Engines (AREA)
  • Pens And Brushes (AREA)

Abstract

A control set for synchronizing computers that control switching meshes for at least two systems, including at least two control devices, each associated with one of the systems, and each of them including a local generator to generate first signals that control the associated system and second signals that are transmitted to the other control device (s). Each control device includes logical elements that, when receiving a second signal, intervenes in the control of the associated system. Characterized in that the logical elements of each control device make it possible for a second signal (SYNC'1) to be received to intervene in the control of the system associated with said control system, instead of a first locally generated signal (CRO1), when said second signal (SYNC'1) is received within a predetermined time interval before a first signal (CRO1) is generated locally. (Machine-translation by Google Translate, not legally binding)
ES428221A 1973-07-13 1974-07-12 Control arrangement Expired ES428221A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7309770A NL7309770A (en) 1973-07-13 1973-07-13 CONTROL DEVICE.

Publications (1)

Publication Number Publication Date
ES428221A1 true ES428221A1 (en) 1976-11-16

Family

ID=19819258

Family Applications (1)

Application Number Title Priority Date Filing Date
ES428221A Expired ES428221A1 (en) 1973-07-13 1974-07-12 Control arrangement

Country Status (5)

Country Link
BE (1) BE817584R (en)
ES (1) ES428221A1 (en)
GB (1) GB1444067A (en)
NL (1) NL7309770A (en)
NO (1) NO143410C (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2737713C2 (en) * 1977-08-22 1983-09-29 Siemens AG, 1000 Berlin und 8000 München Time division multiplex digital switching system, in particular PCM telephone switching system, with double switching network devices
DE2907608A1 (en) * 1979-02-27 1980-08-28 Siemens Ag CIRCUIT FOR CLOCK GENERATION IN TELECOMMUNICATION SYSTEMS, IN PARTICULAR TIME MULTIPLEX-DIGITAL SWITCHING SYSTEMS
US4569017A (en) * 1983-12-22 1986-02-04 Gte Automatic Electric Incorporated Duplex central processing unit synchronization circuit
JPS6227813A (en) * 1985-07-29 1987-02-05 Hitachi Ltd Phase synchronization system

Also Published As

Publication number Publication date
NO742447L (en) 1975-02-10
BE817584R (en) 1975-01-13
NO143410B (en) 1980-10-27
GB1444067A (en) 1976-07-28
AU7029374A (en) 1976-01-08
NL7309770A (en) 1975-01-15
NO143410C (en) 1981-02-04

Similar Documents

Publication Publication Date Title
JPS5255337A (en) Refresh control system
ES428221A1 (en) Control arrangement
GB1533577A (en) Synchronising means
JPS5391543A (en) Installation system for hdlc circuit
GB1262156A (en) Apparatus for producing synchronisation in address-coded communication systems
ES430267A1 (en) Electrical control systems
ES460450A1 (en) Local device in a control information transfer system
JPS52145206A (en) Standard signal formation for phase synchronization in rotary control system
ES451439A1 (en) Clock signal and auxiliary signal transmission system
JPS537165A (en) Synchronism detecting circuit of phase control circuit
JPS5396605A (en) Data transmission system
JPS5274237A (en) Refresh control system
JPS52106602A (en) Signal receiving unit
JPS51112240A (en) Input output unit control system
JPS52132703A (en) Time sharing multiplex data transmission system
JPS5361931A (en) Communication control device
JPS51130134A (en) Asynchronous data reception control system
JPS5289344A (en) Data collecting and transmitting system
JPS53107252A (en) Interruption answer system
ES425738A1 (en) Time division multiplex subscriber circuit
JPS5285454A (en) Key input circuit
JPS5326538A (en) Refresh control system for memory
JPS51145349A (en) Associated synchronous controlling system of irregular signal wave
JPS5245233A (en) System for interruption control of process input signal
JPS5353931A (en) Timing control system for memory unit