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GB1300710A - Complementary transistor structure and method - Google Patents

Complementary transistor structure and method

Info

Publication number
GB1300710A
GB1300710A GB55246/71A GB5524671A GB1300710A GB 1300710 A GB1300710 A GB 1300710A GB 55246/71 A GB55246/71 A GB 55246/71A GB 5524671 A GB5524671 A GB 5524671A GB 1300710 A GB1300710 A GB 1300710A
Authority
GB
United Kingdom
Prior art keywords
collector
groove
diffusion
transistor
npn transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB55246/71A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of GB1300710A publication Critical patent/GB1300710A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

1300710 Integrated circuits SIGNETICS CORP 29 Nov 1971 [10 Dec 1970] 55246/71 Heading H1K The complementary vertical PNP and NPN transistors shown are formed from a single N- type silicon starting wafer 11 the (100) lower surface of which etched through apertured silica passivation using an anisotropic etch to form a groove. The groove and its surrounding area are exposed through silica film 18, and the entire collector region of the PNP transistor is formed by diffusion. The process is repeated at a further location to form the enhanced conductivity portion 24 of the collector region of the NPN transistor. Deeper grooves are then etched in the lower surface, the entire lower surface passivated, and a polycrystalline support 29 grown thereon. The upper surface of the structure is lapped to leave the isolated transistor islands, the diffused collector regions remaining just below the surface. Further diffusion operations provide emitter and base regions and enhanced conductivity contact regions. Care is taken to ensure that the collector contact regions meet the diffused collector portions which follow the contours of the grooves. Aluminium electrodes are provided. In the variant of Fig. 10 (not shown) the NPN transistor is not formed with a groove in its lower surface and diffusion into the lower face of the starting wafer at the location of the NPN transistor merely provides a normal collector sub-region.
GB55246/71A 1970-12-10 1971-11-29 Complementary transistor structure and method Expired GB1300710A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US9671370A 1970-12-10 1970-12-10

Publications (1)

Publication Number Publication Date
GB1300710A true GB1300710A (en) 1972-12-20

Family

ID=22258729

Family Applications (1)

Application Number Title Priority Date Filing Date
GB55246/71A Expired GB1300710A (en) 1970-12-10 1971-11-29 Complementary transistor structure and method

Country Status (1)

Country Link
GB (1) GB1300710A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2465316A1 (en) * 1979-09-17 1981-03-20 Nippon Telegraph & Telephone SEMICONDUCTOR DEVICES HAVING COMPLEMENTARY SEMICONDUCTOR ELEMENTS AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE
EP0142737A3 (en) * 1983-11-04 1987-11-25 Harris Corporation Electrochemical dielectric isolation technique

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2465316A1 (en) * 1979-09-17 1981-03-20 Nippon Telegraph & Telephone SEMICONDUCTOR DEVICES HAVING COMPLEMENTARY SEMICONDUCTOR ELEMENTS AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE
EP0142737A3 (en) * 1983-11-04 1987-11-25 Harris Corporation Electrochemical dielectric isolation technique

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee