[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

FR3030882B1 - INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES - Google Patents

INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES Download PDF

Info

Publication number
FR3030882B1
FR3030882B1 FR1463174A FR1463174A FR3030882B1 FR 3030882 B1 FR3030882 B1 FR 3030882B1 FR 1463174 A FR1463174 A FR 1463174A FR 1463174 A FR1463174 A FR 1463174A FR 3030882 B1 FR3030882 B1 FR 3030882B1
Authority
FR
France
Prior art keywords
integrated circuit
pmos transistors
threshold voltages
separate threshold
separate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1463174A
Other languages
French (fr)
Other versions
FR3030882A1 (en
Inventor
Francois Andrieu
Nicolas Degors
Pierre Perreau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
International Business Machines Corp
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA, International Business Machines Corp filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1463174A priority Critical patent/FR3030882B1/en
Priority to US14/978,428 priority patent/US9520330B2/en
Publication of FR3030882A1 publication Critical patent/FR3030882A1/en
Application granted granted Critical
Publication of FR3030882B1 publication Critical patent/FR3030882B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR1463174A 2014-12-22 2014-12-22 INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES Active FR3030882B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1463174A FR3030882B1 (en) 2014-12-22 2014-12-22 INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES
US14/978,428 US9520330B2 (en) 2014-12-22 2015-12-22 Integrated circuit comprising PMOS transistors with different voltage thresholds

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1463174 2014-12-22
FR1463174A FR3030882B1 (en) 2014-12-22 2014-12-22 INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES

Publications (2)

Publication Number Publication Date
FR3030882A1 FR3030882A1 (en) 2016-06-24
FR3030882B1 true FR3030882B1 (en) 2018-03-09

Family

ID=52627460

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1463174A Active FR3030882B1 (en) 2014-12-22 2014-12-22 INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES

Country Status (2)

Country Link
US (1) US9520330B2 (en)
FR (1) FR3030882B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10297672B2 (en) * 2017-07-13 2019-05-21 Globalfoundries Inc. Triple gate technology for 14 nanometer and onwards
US10559593B1 (en) * 2018-08-13 2020-02-11 Globalfoundries Inc. Field-effect transistors with a grown silicon-germanium channel
US10679901B2 (en) 2018-08-14 2020-06-09 International Business Machines Corporation Differing device characteristics on a single wafer by selective etch
US12107168B2 (en) 2021-08-25 2024-10-01 International Business Machines Corporation Independent gate length tunability for stacked transistors
CN118073352A (en) * 2022-11-11 2024-05-24 长鑫存储技术有限公司 Semiconductor structure, preparation method thereof and memory

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424016B1 (en) * 1996-05-24 2002-07-23 Texas Instruments Incorporated SOI DRAM having P-doped polysilicon gate for a memory pass transistor
US7071122B2 (en) * 2003-12-10 2006-07-04 International Business Machines Corporation Field effect transistor with etched-back gate dielectric
US7382023B2 (en) * 2004-04-28 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fully depleted SOI multiple threshold voltage application
FR2870043B1 (en) * 2004-05-07 2006-11-24 Commissariat Energie Atomique MANUFACTURING OF ACTIVE ZONES OF DIFFERENT NATURE DIRECTLY ON INSULATION AND APPLICATION TO MOS TRANSISTOR WITH SINGLE OR DOUBLE GRID
US8178902B2 (en) * 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US7265004B2 (en) * 2005-11-14 2007-09-04 Freescale Semiconductor, Inc. Electronic devices including a semiconductor layer and a process for forming the same
JP2007317975A (en) 2006-05-29 2007-12-06 Nec Electronics Corp Optical semiconductor device
FR2902234B1 (en) * 2006-06-12 2008-10-10 Commissariat Energie Atomique METHOD FOR MAKING Si1-yGey ZONES OF DIFFERENT Ge CONTENTS ON THE SAME SUBSTRATE BY GERMANIUM CONDENSATION
US7449735B2 (en) * 2006-10-10 2008-11-11 International Business Machines Corporation Dual work-function single gate stack
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
US20090072312A1 (en) * 2007-09-14 2009-03-19 Leland Chang Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS
FR2925979A1 (en) 2007-12-27 2009-07-03 Commissariat Energie Atomique METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE ON INSULATION INCLUDING AN ENRICHMENT STEP IN LOCALIZED GE
FR2935194B1 (en) 2008-08-22 2010-10-08 Commissariat Energie Atomique METHOD FOR PRODUCING LOCALIZED GEOI STRUCTURES OBTAINED BY ENRICHMENT IN GERMANIUM
FR2936095B1 (en) 2008-09-18 2011-04-01 Commissariat Energie Atomique METHOD FOR MANUFACTURING A MICROELECTRONIC DEVICE HAVING SEMICONDUCTOR ZONES ON HORIZONTAL GRADIENT INSULATION OF GE CONCENTRATION
US8017469B2 (en) * 2009-01-21 2011-09-13 Freescale Semiconductor, Inc. Dual high-k oxides with sige channel
US8058137B1 (en) * 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8362482B2 (en) * 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US8492886B2 (en) * 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8273610B2 (en) * 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US8492210B2 (en) * 2010-12-17 2013-07-23 Institute of Microelectronics, Chinese Academy of Sciences Transistor, semiconductor device comprising the transistor and method for manufacturing the same
CN102881694A (en) * 2011-07-14 2013-01-16 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
US9214400B2 (en) * 2011-08-31 2015-12-15 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device with back gate isolation regions and method for manufacturing the same
JP5837387B2 (en) * 2011-10-11 2015-12-24 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
US9000557B2 (en) * 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US9275911B2 (en) * 2012-10-12 2016-03-01 Globalfoundries Inc. Hybrid orientation fin field effect transistor and planar field effect transistor
US9691882B2 (en) * 2013-03-14 2017-06-27 International Business Machines Corporation Carbon-doped cap for a raised active semiconductor region
US9219078B2 (en) * 2013-04-18 2015-12-22 International Business Machines Corporation Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
US9018057B1 (en) * 2013-10-08 2015-04-28 Stmicroelectronics, Inc. Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
US9093302B2 (en) * 2013-11-13 2015-07-28 Globalfoundries Inc. Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
FR3015769B1 (en) * 2013-12-23 2017-08-11 Commissariat Energie Atomique IMPROVED METHOD FOR PRODUCING CONCEALED SEMICONDUCTOR BLOCKS ON THE INSULATING LAYER OF A SEMICONDUCTOR SUBSTRATE ON INSULATION
US9985030B2 (en) * 2014-04-07 2018-05-29 International Business Machines Corporation FinFET semiconductor device having integrated SiGe fin

Also Published As

Publication number Publication date
US20160197018A1 (en) 2016-07-07
US9520330B2 (en) 2016-12-13
FR3030882A1 (en) 2016-06-24

Similar Documents

Publication Publication Date Title
GB2527196B (en) Indicia-reading module with an integrated flexible circuit
GB2545127B (en) GOA circuit based on ltps semiconductor tft
GB201706061D0 (en) GOA circuit based on oxide semiconductor thin-film transistor
GB201700516D0 (en) Gate drive circuit having self-compensation function
GB201700515D0 (en) Gate drive circuit having self-compensation function
GB201700518D0 (en) Gate drive circuit having self-compensation function
GB201700525D0 (en) Gate drive circuit having self-compensation function
GB201700519D0 (en) Gate drive circuit having self-compensation function
DK3258994T3 (en) INJECTION DEVICE WITH AUXILIARY DEVICE
EP3183751A4 (en) Mos antifuse with void-accelerated breakdown
GB2546685B (en) Gate drive circuit and shift register
GB2548018B (en) GOA circuit based on LTPS semiconductor TFT
GB2543700B (en) Gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors
EP3123516A4 (en) Iii-n transistors with enhanced breakdown voltage
SG10201503305PA (en) Lateral high voltage transistor
GB2550306B (en) PMOS Gate Driving Circuit
FR3030114B1 (en) TRANSISTOR HEMT
GB2548019B (en) GOA circuit based on LTPS semiconductor TFT
GB2544929B (en) GOA circuit based on LTPS semiconductor TFT
FR3018952B1 (en) INTEGRATED STRUCTURE COMPRISING MOS NEIGHBOR TRANSISTORS
EP3127164A4 (en) P-tunneling field effect transistor device with pocket
GB201411621D0 (en) Organic transistor
GB2536585B (en) Transistors with higher switching than nominal voltages
FR3030882B1 (en) INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES
GB2546647B (en) GOA circuit based on LTPS semiconductor TFT

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20160624

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 9

PLFP Fee payment

Year of fee payment: 10