CN118073352A

CN118073352A - Semiconductor structure, preparation method thereof and memory

Info

Publication number: CN118073352A
Application number: CN202211411212.XA
Authority: CN
Inventors: 沈宇桐; 王蒙蒙
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2024-05-24
Also published as: WO2024098707A1

Abstract

The embodiment of the disclosure provides a semiconductor structure, a preparation method thereof and a memory, wherein the semiconductor structure comprises a first device structure and a second device structure; the first device structure comprises a first active region and a first gate structure located above the first active region; the first active region comprises a first energy band adjusting layer, and the first grid structure is positioned above the first energy band adjusting layer; the second device structure includes a second active region and a second gate structure over the second active region; wherein the second active region comprises a second energy band adjustment layer, and the second gate structure is located above the second energy band adjustment layer; the thickness of the first energy band adjustment layer is less than the thickness of the second energy band adjustment layer. The semiconductor structure provided by the embodiment of the disclosure can improve the adjusting effect of the threshold voltage.

Description

Semiconductor structure, preparation method thereof and memory

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure, a method for manufacturing the same, and a memory.

Background

Transistors are an important semiconductor device. Currently, transistors can be divided into thick-oxide devices (THICK DEVICE) and thin-oxide devices (THIN DEVICE) according to the thickness of the gate oxide layer, each of which samples a work function adjusting layer to adjust the threshold voltage (Threshold voltage, VT) of the transistor. However, since the adjusting effect of the work function adjusting layer is limited by the thickness of the gate oxide layer and the high dielectric constant material layer, the adjusting effect of the work function adjusting layer on the thick oxygen device and the thin oxygen device is different, so that the thick oxygen device is easy to introduce a higher threshold voltage, and the performance of the transistor is reduced.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a memory.

In a first aspect, embodiments of the present disclosure provide a semiconductor structure including a first device structure and a second device structure;

The first device structure comprises a first active region and a first gate structure positioned above the first active region; wherein the first active region comprises a first energy band adjustment layer, the first gate structure being located above the first energy band adjustment layer;

The second device structure comprises a second active region and a second gate structure positioned above the second active region; wherein the second active region comprises a second energy band adjustment layer, the second gate structure being located above the second energy band adjustment layer;

The thickness of the first energy band adjusting layer is smaller than that of the second energy band adjusting layer.

In some embodiments, the area of the first gate structure is greater than or equal to the first energy band adjustment layer area, and the area of the second gate structure is greater than or equal to the second energy band adjustment layer area.

In some embodiments, the first band adjustment layer is silicon germanium (SiGe) and the second band adjustment layer is SiGe;

the first device structure and the second device structure are both P-type transistors.

In some embodiments, the semiconductor structure further includes a third device structure and a fourth device structure, each of the third device structure and the fourth device structure being an N-type transistor;

The third device structure comprises a third active region and a third gate structure positioned above the third active region;

The fourth device structure includes a fourth active region and a fourth gate structure over the fourth active region.

In some embodiments, the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure comprises:

a gate dielectric layer;

the conductive layer is positioned above the gate dielectric layer;

An insulating layer over the conductive layer.

a gate dielectric layer;

the work function adjusting layer is positioned above the gate dielectric layer;

a conductive layer over the work function adjustment layer; an insulating layer over the conductive layer.

In some embodiments, in the first gate structure or the third gate structure, the gate dielectric layer includes a gate oxide layer;

in the second gate structure or the fourth gate structure, the gate dielectric layer comprises a gate oxide layer and a high dielectric constant material layer;

Wherein the thickness of the gate oxide layer in the first gate structure is greater than the thickness of the gate oxide layer in the second gate structure, and the thickness of the gate oxide layer in the third gate structure is greater than the thickness of the gate oxide layer in the fourth gate structure.

In some embodiments, the conductive layer comprises:

A polysilicon layer;

And a metal layer positioned above the polysilicon layer.

In some embodiments, the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure further comprises:

The side wall insulation structure covers the side surfaces of the gate dielectric layer, the conductive layer and the insulation layer;

The side wall insulation structure of the first grid structure also covers the side face of the first energy band adjusting layer, and the side wall insulation structure of the second grid structure also covers the side face of the second energy band adjusting layer.

The side wall insulation structure covers the side surfaces of the gate dielectric layer, the work function adjusting layer, the conducting layer and the insulating layer;

In a second aspect, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, the method including:

providing a semiconductor substrate, and forming a first active region and a second active region in the semiconductor substrate;

forming a first energy band adjusting layer in the first active region, and forming a second energy band adjusting layer in the second active region; wherein the thickness of the first energy band adjusting layer is smaller than that of the second energy band adjusting layer;

Forming a first gate structure over the first energy band adjustment layer and forming a second gate structure over the second energy band adjustment layer;

Wherein the first active region, the first energy band adjustment layer, and the first gate structure are used to form a first device structure; the second active region, the second energy band adjustment layer, and the second gate structure are used to form a second device structure.

In some embodiments, the method further comprises:

Forming a third active region and a fourth active region in the semiconductor substrate;

forming a third gate structure over the third active region and forming a fourth gate structure over the fourth active region;

wherein the third active region and the third gate structure are used to form a third device structure; the fourth active region and the fourth gate structure are used to form a fourth device structure.

In some embodiments, the first device structure and the second device structure are both P-type transistors; the third device structure and the fourth device structure are both N-type transistors;

The first gate structure, the second gate structure, the third gate structure or the fourth gate structure comprises a gate dielectric layer, a conductive layer and an insulating layer which are sequentially stacked;

In the first gate structure or the third gate structure, the gate dielectric layer includes a gate oxide layer; in the second gate structure or the fourth gate structure, the gate dielectric layer comprises a gate oxide layer and a high dielectric constant material layer; wherein the thickness of the gate oxide layer in the first gate structure is greater than the thickness of the gate oxide layer in the second gate structure, and the thickness of the gate oxide layer in the third gate structure is greater than the thickness of the gate oxide layer in the fourth gate structure.

In some embodiments, the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure further comprise a work function adjustment layer between the gate dielectric layer and the conductive layer.

In some embodiments, the forming a first energy band adjustment layer in the first active region and a second energy band adjustment layer in the second active region includes:

Depositing a first energy band adjusting material layer on the surfaces of the first active region and the second active region, and depositing a first gate oxide material layer on the surfaces of the third active region and the fourth active region;

depositing a second gate oxide material layer over the first, third and fourth active regions;

depositing a second energy band-adjusting material layer over the second active region;

wherein the first energy band adjustment layer is formed by the first energy band material layer on the first active region surface and the second energy band adjustment layer is formed by the first energy band material layer and the second energy band material layer on the second active region surface together.

In some embodiments, after depositing the second energy band material layer over the second active region, the method further comprises:

removing the first gate oxide material layer and the second gate oxide material layer over the fourth active region;

depositing a third gate oxide material layer over the first, second, third, and fourth active regions;

the gate oxide layer of the first device structure is formed by the second gate oxide material layer and the third gate oxide material layer, the gate oxide layer of the second device structure is formed by the third gate oxide material layer, the gate oxide layer of the third device structure is formed by the first gate oxide material layer, the second gate oxide material layer and the third gate oxide material layer, and the gate oxide layer of the fourth device structure is formed by the third gate oxide material layer.

In some embodiments, the method further comprises:

Forming a side wall insulation structure on the side surfaces of the gate oxide layer, the high dielectric constant material layer, the work function adjusting layer, the conducting layer and the insulating layer;

In a third aspect, embodiments of the present disclosure provide a memory comprising the semiconductor structure of the first aspect.

In the embodiment of the disclosure, the threshold voltage of the transistor is regulated by introducing the energy band regulating layer into the device structure, and the energy band regulating layers with different thicknesses are arranged for different devices, so that the threshold voltages of various devices can be regulated to respective target ranges, and the performance of the semiconductor is improved.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of yet another semiconductor structure provided by embodiments of the present disclosure;

FIG. 4 is a schematic diagram of yet another semiconductor structure provided in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of yet another semiconductor structure provided in an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a semiconductor structure according to the related art;

fig. 7 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 8 is a schematic diagram illustrating a first process for fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 9 is a schematic diagram of a second process for manufacturing a semiconductor structure according to an embodiment of the disclosure;

Fig. 10 is a schematic diagram III of a manufacturing process of a semiconductor structure according to an embodiment of the disclosure;

Fig. 11 is a schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the disclosure;

fig. 12 is a schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the disclosure;

fig. 13 is a schematic diagram sixth illustrating a manufacturing process of a semiconductor structure according to an embodiment of the disclosure;

Fig. 14 is a schematic diagram seventh illustrating a manufacturing process of a semiconductor structure according to an embodiment of the disclosure;

fig. 15 is a schematic view eight of a manufacturing process of a semiconductor structure according to an embodiment of the disclosure;

Fig. 16 is a schematic diagram nine of a process for fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 17 is a schematic view of a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure;

fig. 18 is a schematic diagram eleven of a manufacturing process of a semiconductor structure according to an embodiment of the disclosure;

fig. 19 is a schematic structural diagram of a memory according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

DRAM (Dynamic Random Access Memory): a dynamic random access memory;

GATE FIRST process: a process for forming grid electrode;

PMOS (P-TYPE METAL Oxide Semiconductor FIELD EFFECT transducer): a P-type transistor;

NMOS (N-TYPE METAL Oxide Semiconductor FIELD EFFECT transducer): an N-type transistor;

CMOS (Complementary Metal Oxide Semiconductor): a complementary metal oxide semiconductor;

PG: and a gate.

Taking DRAM as an example, there may be thick-oxide PMOS, thin-oxide PMOS, thick-oxide NMOS, thin-oxide NMOS in the circuit. Generally, the remaining structures of the thick-oxygen PMOS and the thin-oxygen PMOS are substantially the same except for the thickness of the gate oxide layer, i.e., the thick-oxygen PMOS and the thin-oxygen PMOS employ the same work function adjustment layer, and the thick-oxygen NMOS and the thin-oxygen NMOS employ the same work function adjustment layer. In the preparation process, the thick oxygen PMOS, the thin oxygen PMOS, the thick oxygen NMOS and the thin oxygen NMOS are prepared together, and the difference of certain structures is realized by means of masking/etching and other steps.

Taking GATE FIRST process as an example, the adjusting effect of the work function adjusting layer in the thick oxygen device is limited by the thickness of the gate oxide layer, so that the work function adjusting effect of the thick oxygen device and the thin oxygen device is not consistent; in addition, the introduction of the high dielectric constant material layer also brings fermi pinning effect, so that the adjusting effect of the work function adjusting layer on the threshold voltage is limited, and the adjusting effect of the work function adjusting layer on the threshold voltage is not ideal. In particular, the problem is more serious for PMOS, because the means of adjusting the threshold voltage of NMOS is more and the effect is more remarkable.

Based on this, the embodiment of the disclosure provides a semiconductor structure, which uses energy band engineering (for example, introducing an energy band adjusting layer) to adjust the threshold voltage of a transistor, and meanwhile, the energy band adjusting layer in a thick oxygen device is thinner, and the energy band adjusting layer in a thin oxygen device is thicker, so that the threshold voltages of the thin oxygen device and the thick oxygen device are adjusted to be within respective target ranges, the problem that the threshold voltage of the thick oxygen device is too high can be solved, and the performance of the semiconductor is improved.

In one embodiment of the present disclosure, referring to fig. 1, a schematic diagram of a semiconductor structure 10 provided by an embodiment of the present disclosure is shown. As shown in fig. 1, the semiconductor structure 10 includes a first device structure 11 and a second device structure 12; the first device structure 11 includes a first active region 111 and a first gate structure 112 located over the first active region 111; wherein the first active region 111 includes a first energy band adjustment layer 111a, and the first gate structure 112 is located above the first energy band adjustment layer 111 a; the second device structure 12 includes a second active region 121 and a second gate structure 122 located over the second active region 121; the second active region 121 includes a second energy band adjustment layer 121a, and the second gate structure 122 is located above the second energy band adjustment layer 121 a.

Here, the thickness of the first energy band adjustment layer 111a is smaller than that of the second energy band adjustment layer 121 a.

It should be noted that, the first active region 111 and the second active region 121 are both located in a semiconductor substrate, which may be a silicon substrate, and may also include other semiconductor elements, for example: germanium (Ge), or include semiconductor compounds such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.

It should be noted that, the first device structure 11 and the second device structure 12 are both transistors. In the embodiment of the present disclosure, the thickness of the gate oxide layer in the first device structure 11 is greater than the thickness of the gate oxide layer in the second device structure 12, i.e., the first device structure 11 is a thick-oxide device and the second device structure 12 is a thin-oxide device. That is, in the semiconductor structure 10, the first band adjustment layer 111 a/the second band adjustment layer 121a is additionally introduced into the transistor to adjust the threshold voltage of the transistor using the band engineering (Energy Band Engineering); meanwhile, as the adjustment requirements of the thick oxygen device and the thin oxygen device are different, the energy band adjusting layers with at least two thicknesses are arranged, and the threshold voltages of the thick oxygen device and the thin oxygen device can be better adjusted respectively, so that the threshold voltages of the thin oxygen device and the thick oxygen device are better adjusted to be within respective target value ranges respectively, the problem that the threshold voltages of the thin oxygen device and the thick oxygen device (especially the thick oxygen device) are too high is solved, and the performance of the semiconductor structure 10 is further improved.

Here, since the thicknesses of the first energy band adjustment layer 111a and the second energy band adjustment layer 121a are different, the adjustment effects thereof are also different. Illustratively, the threshold voltages of the first device structure 11 and the second device structure 12 are reduced simultaneously, but by different amounts; for example, the threshold voltage adjustment amount of the thin oxygen device is larger, and the threshold voltage adjustment amount of the thick oxygen device is smaller, so that the threshold voltages of the first device structure 11 and the second device structure 12 are adjusted to respective target ranges.

Here, energy band engineering (Energy Band Engineering) refers to the regulation of the energy band structure of materials, so that the materials have different physical and chemical properties. The energy band engineering material regulates and controls the energy band of the semiconductor material by utilizing the energy band engineering, so that the transportation of electrons/holes in the semiconductor is changed greatly, and the performance of the device is changed.

In some embodiments, the first energy band adjustment layer 111a and the second energy band adjustment layer 121a are the same composition. Illustratively, the first band adjustment layer 111a is silicon germanium (SiGe) and the second band adjustment layer 121a is SiGe.

It should be noted that, the first band adjustment layer 111a and the second band adjustment layer 121a may be implemented by SiGe stripes (or referred to as SIGE CHANNEL), and the manufacturing process is not limited. Illustratively, SIGE CHANNEL may be formed by an epitaxial growth process, which refers to growing a single crystal layer of a certain desired crystal orientation of the substrate in a single crystal semiconductor substrate (i.e., first active region 111 and second active region 121). For example, there are various methods for growing epitaxial layers, but most of them are vapor phase epitaxy processes, i.e., high temperature reactions in a reaction chamber, and the resulting Ge, si are epitaxially grown on the silicon surface of a substrate.

In some embodiments, the first device structure 11 and the second device structure 12 are both P-type transistors PMOS.

In the transistor, the adjustment of the threshold voltage generally depends on the work function adjustment layer in the gate structure. For thin-oxide PMOS and thick-oxide PMOS, the work function adjustment layer is not uniform (affected by the gate oxide/high-k material layer), resulting in a threshold voltage of the thick-oxide PMOS that is too high, affecting the performance of the semiconductor structure. Based on this, in the semiconductor structure 10 provided in the embodiment of the present disclosure, the first energy band adjustment layer 111a is introduced into the thick-oxygen PMOS, the second energy band adjustment layer 121a is introduced into the thin-oxygen PMOS, and the thickness of the first energy band adjustment layer 111a is smaller than that of the second energy band adjustment layer 121a, so that the threshold voltage of the PMOS has a better adjustment effect, so that the threshold voltages of all the transistors are adjusted to be within the target range.

The conduction principle of the hole transistor PMOS is the transport of holes. Due to the band characteristics of SiGe, the mobility of holes in SiGe is higher. For thick oxygen devices, the threshold voltage of the transistor is lowered by the alignment of the SiGe narrow bandgap and the energy band of the active region.

In addition, the N-type transistor NMOS has various means of controlling the threshold voltage and has an obvious effect, so that the above problem is not serious, and the NMOS may not be provided with an energy band adjusting layer. Thus, in some embodiments, as shown in fig. 2, semiconductor structure 10 further includes a third device structure 13 and a fourth device structure 14, the third device structure 13 and the fourth device structure 14 each being an N-type transistor NMOS;

The third device structure 13 includes a third active region 131 and a third gate structure 132 over the third active region 131; the fourth device structure 14 includes a fourth active region 141 and a fourth gate structure 142 located over the fourth active region 141.

Note that the thickness of the gate oxide layer in the third device structure 13 is greater than the thickness of the gate oxide layer in the fourth device structure 14, i.e., the third device structure 13 is a thick-oxygen NMOS and the fourth device structure 14 is a thin-oxygen NMOS.

In other embodiments, the energy band adjustment layer may also be disposed in each of the third device structure 13 and the fourth device structure 14. On this basis, the thickness of the energy band adjusting layer in the third device structure 13 is smaller than the thickness of the energy band adjusting layer in the fourth device structure 14.

In some embodiments, the first gate structure 112, the second gate structure 122, the third gate structure 132, or the fourth gate structure 142 includes:

a gate dielectric layer;

the conductive layer is positioned above the gate dielectric layer;

an insulating layer over the conductive layer.

In this way, the threshold voltage of the first device structure 11 (or the second device structure 12) may be regulated by means of the first energy band adjustment layer 111a (or the second energy band adjustment layer 121 a) alone. Meanwhile, corresponding energy band adjusting layers can be arranged in the third device structure 13 and the fourth device structure 14 to realize the regulation and control of the threshold voltage.

In other embodiments, as shown in fig. 3, the first gate structure 112, the second gate structure 122, the third gate structure 132, or the fourth gate structure 142 includes:

a gate dielectric layer 21;

a work function adjusting layer 22 located above the gate dielectric layer 21;

a conductive layer 23 located above the work function adjusting layer 22;

An insulating layer 24 located over the conductive layer 23.

In this way, the work function adjusting layer 22 can also function to adjust the threshold voltage of the transistor. For the first device structure 11 (or the second device structure 12), the adjustment of the threshold voltage depends on both the work function adjustment layer 22 and the first energy band adjustment layer 111a (or the second energy band adjustment layer 121 a), and the adjustment effect of the first energy band adjustment layer 111a (or the second energy band adjustment layer 121 a) on the threshold voltage may be stronger than the adjustment effect of the work function adjustment layer 22 on the threshold voltage; for the third device structure 13 and the fourth device structure 14, the adjustment of the threshold voltage mainly depends on the work function adjustment layer 22.

It should be noted that, for the first gate structure 112, the second gate structure 122, the third gate structure 132, or the fourth gate structure 142, the gate dielectric layer 21 in the different gate structures may be formed of different compositions, the work function adjusting layer 22 in the different gate structures may be formed of different compositions, the conductive layer 23 in the different gate structures may be formed of different compositions, and the insulating layer 24 in the different gate structures may be formed of different compositions, which is only exemplary and not limiting in particular.

In a specific embodiment, as shown in fig. 3, in the first gate structure 112 or the third gate structure 132, the gate dielectric layer includes a gate oxide layer 211 (of course, may further include a dielectric constant material layer 212); in the second gate structure 122 or the fourth gate structure 142, the gate dielectric layer 21 includes a gate oxide layer 211 and a high dielectric constant material layer 212; wherein the thickness of the gate oxide in the first gate structure 112 is greater than the thickness of the gate oxide in the second gate structure 122, and the thickness of the gate oxide in the third gate structure 132 is greater than the thickness of the gate oxide in the fourth gate structure 142.

For the thick-oxygen PMOS, the larger thickness of the gate oxide layer limits the threshold voltage adjusting effect of the work function adjusting layer. Thus, the embodiments of the present disclosure introduce the first energy band adjustment layer 111a into the thick oxygen PMOS, and the first energy band adjustment layer 111a alone or in cooperation with the work function adjustment layer may better adjust the threshold voltage of the thick oxygen PMOS.

Thus, for a thick oxide PMOS or a thick oxide NMOS, the gate dielectric layer 21 includes a thicker gate oxide layer 211 (of course, the high dielectric constant material layer 212 may be further included); for thin-oxide PMOS or thin-oxide NMOS, the gate dielectric layer 21 includes a thinner gate oxide 211 and a high-k material layer 212. The gate oxide layer 211 may be silicon dioxide SiO ₂, the high-K material layer 212 may be referred to as a high-K material layer, and may be formed by depositing a material with a relatively high dielectric constant, such as hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or the like.

It should also be noted that the work function adjusting layer 22 may include one or more of a titanium nitride TiN layer, an aluminum oxide AlO layer, and a lanthanum oxide LaO.

In a specific embodiment, as shown in fig. 3, for the first gate structure 112 and the second gate structure 122 (PMOS), the work function adjustment layer 22 includes, in order from bottom to top: titanium nitride TiN layer 221, aluminum oxide AlO layer 222, tiN layer 223, lanthanum oxide LaO layer 224, and TiN layer 225.

As shown in fig. 3, for the third gate structure 132 and the fourth gate structure 142 (NMOS), the work function adjusting layer 22 includes: laO layer 226 and TiN layer 227.

In the embodiment of the present disclosure, the size and the proportion of the other material layers are not limited except for the thickness relationship between the first energy band adjustment layer 111a and the second energy band adjustment layer 121a, and the thickness relationship between the gate oxide layer in the thick oxygen device and the gate oxide layer in the thin oxygen device.

It should be noted that the above TiN layer, alO layer, laO layer formation process has various possibilities, such as an atomic layer deposition process (Atomic Layer Deposition, ALD), which is a method that can plate substances layer by layer on the substrate surface in the form of a monoatomic film.

Note that, although the AlO layer plays a main role in adjusting work function in PMOS, the role of adjusting threshold voltage by Al is not obvious due to factors such as strong diffusion of Al, and is easily affected by the thickness of the gate oxide layer 211. In this embodiment, for PMOS, the threshold voltage of the thin oxygen device/thick oxygen device is adjusted by introducing SIGE CHANNEL through energy band engineering, and the effect of adjusting the threshold voltage is improved, so that the threshold voltages of the thin oxygen device/thick oxygen device are adjusted to be within respective target ranges.

The work function adjusting layer 22 may be formed of one or more of the following components: titanium aluminum compounds TiAl, tantalum Ta, tantalum nitride TaN, nickel Ni, platinum Pt, and the like, embodiments of the present disclosure are not limited.

In a specific embodiment, as shown in fig. 3, the conductive layer 23 includes:

A polysilicon layer 231;

A metal layer 232 over the polysilicon layer 231.

It should be noted that, the metal layer 232 may be formed of one or more of the following materials: copper, ruthenium, palladium, platinum, cobalt, nickel, tungsten, aluminum, titanium, tantalum, zirconium.

In some embodiments, the insulating layer 24 may be formed using an insulating material such as silicon nitride, silicon dioxide, or the like.

In some embodiments, for the case that the gate structure includes a gate dielectric layer, a conductive layer, and an insulating layer in this order, the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure further includes:

The side wall insulation structure covers the side surfaces of the gate dielectric layer, the conducting layer and the insulating layer; the side wall insulation structure of the first grid structure also covers the side face of the first energy band adjusting layer, and the side wall insulation structure of the second grid structure also covers the side face of the second energy band adjusting layer.

In other embodiments, where the gate structure includes a gate dielectric layer, a work function adjusting layer, a conductive layer, and an insulating layer in this order, as shown in fig. 4, the first gate structure 112, the second gate structure 122, the third gate structure 132, or the fourth gate structure 142 further includes:

The side wall insulation structure 25, and the side wall insulation structure 25 covers the sides of the gate dielectric layer 21, the work function adjusting layer 22, the conductive layer 23 and the insulation layer 24.

Note that the sidewall insulating structure 25 is used to isolate the gate structure. In this way, the insulating layer 24 may realize top surface insulation of the gate structure, and the sidewall insulating structure 25 is used to realize side surface insulation of the gate structure, so that the gate is isolated from other structures.

Illustratively, as shown in fig. 4, the sidewall insulating structure 25 includes a first sidewall insulating structure 251 and a second sidewall insulating structure 252. Illustratively, the first sidewall insulating structure 251 is silicon oxide and the second sidewall insulating structure 252 is silicon nitride. Thus, the sidewall insulating structure 25 is composed of different insulating structures to achieve a better isolation effect.

It should be noted that, the insulating layer 24, the first sidewall insulating structure 251 and the second sidewall insulating structure 252 may be formed of other insulating materials and combinations thereof, which are not limited in the embodiments of the present disclosure.

In the first embodiment, as shown in fig. 4, the area of the first gate structure 112 is greater than or equal to the area of the first energy band adjustment layer 111a, and the area of the second gate structure 122 is greater than or equal to the area of the second energy band adjustment layer 121 a.

For example, the sidewall insulating structure 25 of the first gate structure 112 also covers the side surface of the first energy band adjustment layer 111a, and the sidewall insulating structure 25 of the second gate structure 122 also covers the side surface of the second energy band adjustment layer 121 a.

In the second embodiment, as shown in fig. 5, the area of the first gate structure 112 is smaller than the area of the first band adjustment layer 111a, and the area of the second gate structure 122 is smaller than the area of the second band adjustment layer 121 a.

It should be noted that, for the transistor, after the energy band adjustment layer is introduced, junction leakage (Junction leakage) of the transistor is increased due to the adaptation of the energy band, and this change has little influence on the thin oxygen device, but has a larger influence on the thick oxygen device. Compared with the second possible manner, the first possible manner only retains the energy band adjusting layer right below the gate dielectric layer, so that not only can the threshold voltage be adjusted by using the energy band adjusting layer, but also excessive increase of Junction leakage (Junction leakage) can be avoided.

In summary, embodiments of the present disclosure are in the field of integrated circuit design (VLSI DESIGN), and generally relate to CMOS structures and processes. Referring to fig. 6, a schematic diagram of a semiconductor structure provided by the related art is shown. As shown in fig. 6, SIGE CHANNEL is not present in the transistor, but the threshold voltage is adjusted by the work function adjusting layer. However, the adjusting effect of the work function adjusting layer is limited by the thickness of the gate oxide layer and is also affected by the fermi pinning effect caused by the high dielectric constant material layer, so that in the case that the thick oxygen device and the thin oxygen device share the same work function adjusting layer, the thin oxygen device and the thick oxygen device have difficulty in achieving the ideal work function adjusting effect at the same time, for example, the thick oxygen device may introduce a higher threshold voltage while ensuring that the threshold voltage of the thin oxygen device meets the requirement, thereby reducing the performance of the semiconductor memory.

Based on this, the embodiment of the present disclosure introduces the first energy band adjustment layer 111a and the second energy band adjustment layer 121a to optimize the structure of the gate (PG), which can reduce the problem of high threshold of the device caused by GATE FIRST process. Specifically, in order to solve the problem that the threshold Voltage (VT) of the existing PMOS is too high, on one hand, the present embodiment proposes to utilize a SiGe mask to adjust the threshold voltage by growing a SiGe layer (SIGE CHANNEL) on the thick-oxide PMOS/thin-oxide PMOS; on the other hand, considering the problem of Junction Leakage (Junction Leakage), only the SiGe layer right under the gate is reserved in the subsequent process, so as to better achieve the effect of reducing the threshold voltage of the thick-oxide PMOS; on the other hand, if the SiGe layers with the same thickness and the same concentration are grown for the thick-oxygen PMOS and the thin-oxygen PMOS, the threshold voltage modulation of the thick-oxygen device is too low to control the threshold voltage of the thick-gate-oxide device well, so that the thickness of the SiGe layer in the thick-oxygen PMOS is controlled to be smaller than that of the SiGe layer in the thin-oxygen PMOS, so that the SiGe layer can simultaneously meet the modulation for the PMOS thin-oxygen PMOS and the thick-oxygen PMOS, and the threshold voltages of the thin-oxygen PMOS and the thick-oxygen PMOS are both in respective target ranges.

In an embodiment of the present disclosure, referring to fig. 7, a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown. As shown in fig. 7, the method includes:

S31: a semiconductor substrate is provided, and a first active region and a second active region are formed in the semiconductor substrate.

S32: forming a first energy band adjusting layer in the first active region and forming a second energy band adjusting layer in the second active region; wherein the thickness of the first energy band adjusting layer is smaller than that of the second energy band adjusting layer.

S33: a first gate structure is formed over the first energy band adjustment layer and a second gate structure is formed over the second energy band adjustment layer.

It should be noted that the preparation method provided in the embodiments of the present disclosure is used to prepare the semiconductor structure 10 described above. Here, the first active region, the first energy band adjustment layer, and the first gate structure are used to form a first device structure; the second active region, the second energy band adjustment layer, and the second gate structure are used to form a second device structure.

Specifically, in the DRAM GATE FIRST process context, after the first active region and the second active region are formed, a first energy band adjustment layer is formed in the first active region and a second energy band adjustment layer is formed in the second active region to facilitate adjusting the threshold voltage of the transistor by energy band engineering, and then forming the first gate structure and the second gate structure.

It should be further noted that, the first device structure is a thick oxygen device, the second device structure is a thin oxygen device, and since the adjustment requirements of the thick oxygen device and the thin oxygen device are different, the energy band adjusting layers with at least two thicknesses are set, and the adjustment is better performed on the thick oxygen device and the thin oxygen device, so that the threshold voltages of the thick oxygen device and the thin oxygen device are both within the target range.

In some embodiments, the method further comprises:

Forming a third gate structure over the third active region and forming a fourth gate structure over the fourth active region; wherein the third active region and the third gate structure are used to form a third device structure; the fourth active region and the fourth gate structure are used to form a fourth device structure.

It should be noted that, the first device structure and the second device structure are P-type transistors PMOS; the third device structure and the fourth device structure are both N-type transistors NMOS. That is, the first device structure is a thick oxygen PMOS, the second device structure is a thin oxygen PMOS, the third device structure is a thick oxygen NMOS, and the fourth device structure is a thin oxygen NMOS.

Here, the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure includes a gate dielectric layer, a conductive layer, and an insulating layer that are sequentially stacked. In the first gate structure or the third gate structure, the gate dielectric layer comprises a gate oxide layer; in the second gate structure or the fourth gate structure, the gate dielectric layer comprises a gate oxide layer and a high dielectric constant material layer; wherein the thickness of the gate oxide layer in the first gate structure is greater than the thickness of the gate oxide layer in the second gate structure, and the thickness of the gate oxide layer in the third gate structure is greater than the thickness of the gate oxide layer in the fourth gate structure.

Thus, in the embodiment of the disclosure, the first energy band adjusting layer is introduced into the thick-oxygen PMOS (i.e., the first device structure), the second energy band adjusting layer is introduced into the thin-oxygen PMOS (i.e., the second device structure), and the thicknesses of the first energy band adjusting layer and the second energy band adjusting layer are different, so that the threshold voltage of the PMOS has a better adjusting effect, and the threshold voltages of all transistors are in respective target ranges. In addition, the threshold voltage of the NMOS has various regulation means and obvious effect, so the problems are not serious, and an energy band regulating layer is not required to be introduced.

In other embodiments, the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure further comprise a work function adjustment layer between the gate dielectric layer and the conductive layer.

A specific preparation method is provided below by taking the example of synchronously preparing the first device structure 11, the second device structure 12, the third device structure 13 and the fourth device structure 14 in conjunction with fig. 8 to 16.

Referring to fig. 8, a first energy band material layer is deposited on the surfaces of the first active region 111 and the second active region 121, and a first gate oxide material layer is deposited on the surfaces of the third active region 131 and the fourth active region 141; as shown in fig. 9, a second gate oxide material layer is deposited over the first, third and fourth active regions 111, 131 and 141; as shown in fig. 9 and 10, a second energy band material layer is deposited over the second active region 121. Wherein the first energy band adjustment layer is formed by a first energy band material layer on the surface of the first active region 111 and the second energy band adjustment layer is formed by a combination of the first energy band material layer and a second energy band material layer on the surface of the second active region 121.

It should be noted that the selective deposition of the energy band material layer and the gate oxide material layer described above needs to be achieved by relying on a mask. Here, the material of the energy band material layer (abbreviated as energy band material) may be SiGe, and the material of the gate oxide material layer (abbreviated as gate oxide material) may be SiO ₂.

Illustratively, first, depositing a first gate oxide material layer directly over the semiconductor substrate (including the first active region 111, the second active region 121, the third active region 131, and the fourth active region 141), forming a first mask directly over the third active region 131 and the fourth active region 141, etching to remove the first gate oxide material layer over the first active region 111 and the second active region 121, and removing the first mask; a first energy band material layer is uniformly deposited directly over the semiconductor substrate, a second mask is formed directly over the first active region 111 and the second active region 121, the first energy band material layer over the third active region 131 and the fourth active region 141 is etched away, and the second mask is removed. Thus, as shown in fig. 8, a first energy band material layer remains over the first active region 111 and the second active region 121, and a first gate oxide material layer remains over the third active region 131 and the fourth active region 141.

Next, uniformly depositing a second gate oxide material layer right above the semiconductor substrate, forming a third mask above the first active region 111, the third active region 131 and the fourth active region 141, etching to remove the second gate oxide material layer above the second active region 121, and removing the third mask; thus, as shown in fig. 9, 2 times of deposited gate oxide material remains over the third active region 131 and the fourth active region 141, only 2 times of deposited gate oxide material is over the first active region 111, and no gate oxide material is over the second active region 121.

Then, as shown in fig. 10, a fourth mask is formed over the first active region 111, the third active region 131 and the fourth active region 141, a second energy band material layer is uniformly deposited over the semiconductor substrate, and the fourth mask is laterally etched, and at this time, the second energy band material layer over the fourth mask is also removed; thus, as shown in fig. 11, the band material deposited 2 times remains over the second active region 121, thereby forming a second band-adjusting layer 121a; the 1 st deposited energy band material remains over the first active region 111, thereby forming a first energy band adjustment layer 111a, i.e., the thickness of the first energy band adjustment layer 111a is less than the thickness of the second energy band adjustment layer 121 a.

Referring to fig. 12 and 13, the first gate oxide material layer and the second gate oxide material layer over the fourth active region 141 are removed;

As shown in fig. 14, a third gate oxide material layer is deposited over the first, second, third and fourth active regions 111, 121, 131 and 141; wherein the gate oxide layer 211 of the first device structure 11 is formed by the second gate oxide material layer and the third gate oxide material layer, the gate oxide layer 211 of the second device structure 12 is formed by the second gate oxide material layer and the third gate oxide material layer, the gate oxide layer 211 of the third device structure 13 is formed by the first gate oxide material layer, the second gate oxide material layer 14 and the third gate oxide material layer, and the gate oxide layer 211 of the fourth device structure is formed by the third gate oxide material layer.

As shown in fig. 12, a fifth mask is formed over the first active region 111, the second active region 121, and the third active region 131, the gate oxide material (from the first gate oxide material layer and the second gate oxide material layer) over the fourth active region 141 is etched away, and the fifth mask is removed; as shown in fig. 13, deposited band-gap material is removed over the fourth active region 141.

Then, as shown in fig. 14, a third gate oxide material layer is uniformly deposited directly over the semiconductor substrate, so that the gate oxide layer 211 in the first device structure 11 retains the gate oxide materials deposited 2 nd and 3 rd times, the gate oxide layer 211 in the second device structure 12 retains the gate oxide materials deposited 3 rd times, the gate oxide layer 211 in the third device structure 13 retains the gate oxide materials deposited 1 st, 2 nd and 3 rd times, and the gate oxide layer 211 in the fourth device structure 14 retains only the gate oxide materials deposited 3 rd times, i.e., the thickness of the gate oxide layer 211 in the first device structure 11 is greater than the thickness of the gate oxide layer 211 in the second device structure 12, and the thickness of the gate oxide layer 211 in the third device structure 13 is greater than the thickness of the gate oxide layer 211 in the fourth device structure 14.

After the gate oxide layer 211 is formed, as shown in fig. 15, a high dielectric constant material is uniformly deposited directly over the semiconductor substrate, and a sixth mask is formed over the second and fourth active regions 121 and 141, and then the high dielectric constant material over the first and third active regions 111 and 131 is removed, and the sixth mask is removed. Thus, as shown in fig. 16, the second and third active regions 121 and 131 are formed with a high dielectric constant material layer 212. In other words, for the first device structure 11 and the third device structure 13, the gate oxide layer 211 forms the aforementioned gate dielectric layer; the gate oxide 211 and the high-k material layer 212 form the aforementioned gate dielectric layer for the second device structure 12 and the fourth device structure 14. Here, the high dielectric constant material layer 212 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate.

As shown in fig. 16, after the gate dielectric layer is formed, deposition is continued to form the work function adjusting layer 22. For the first device structure 11 and the second device structure 12, the work function adjusting layer 22 includes, in order from bottom to top: tiN layers, alO layers, tiN layers, laO layers, and TiN layers; for the third device structure 13 and the fourth device structure 14, the work function adjusting layer 22 sequentially includes: laO layers and TiN layers, which are only examples and not limiting in particular, work function tuning layer 22 has many more possible embodiments.

As shown in fig. 17, the conductive layer 23 and the insulating layer 24 are continuously formed over the work function adjusting layer 22. The conductive layer 23 includes a polysilicon layer and a metal layer in this order from bottom to top. The metal layer 232 may be formed from one or more of the following materials: copper, ruthenium, palladium, platinum, cobalt, nickel, tungsten, aluminum, titanium, tantalum, zirconium. The insulating layer 24 may be formed of an insulating material such as silicon dioxide or silicon nitride.

Finally, as shown in fig. 18, the first energy band adjustment layer 111a, the second energy band adjustment layer 121a, the gate dielectric layer 21, the work function adjustment layer 22, the conductive layer 23, and the insulating layer 24 are formed by cutting according to the required gate area.

In addition, the first gate structure 112 to the fourth gate structure 142 further include a sidewall insulating structure. Thus, in some embodiments, the method further comprises:

As shown in fig. 4, a sidewall insulating structure 25 is formed on the sides of the gate oxide layer, the high dielectric constant material layer, the work function adjusting layer, the conductive layer and the insulating layer;

The side wall insulating structure 25 of the first gate structure also covers the side surface of the first energy band adjusting layer, and the side wall insulating structure 25 of the second gate structure also covers the side surface of the second energy band adjusting layer.

Note that, as shown in fig. 4, the sidewall insulating structure 25 includes a first sidewall insulating structure 251 and a second sidewall insulating structure 252. Illustratively, the first sidewall insulating structure 251 is silicon oxide and the second sidewall insulating structure 252 is silicon nitride.

In the foregoing description, all specific material compositions may be replaced by material compositions of similar nature, the above being merely exemplary and not limiting in particular.

The embodiment of the disclosure provides a method for preparing a semiconductor structure, which introduces SIGE CHANNEL (SiGe channel, i.e. capable of carrying an adjusting layer) through energy band engineering so as to adjust the threshold Voltage (VT) of a thin-oxide device (THIN DEVICE), and sets energy band adjusting layers with different thicknesses for different types of devices, so that the threshold voltages of the thin-oxide device and the thick-oxide device can be better adjusted to be within respective target value ranges, thereby improving the problem that the threshold voltages of the thin-oxide device and the thick-oxide device (especially the thick-oxide device) are too high, and further improving the performance of the semiconductor structure; in addition, for thin oxygen devices, the fermi pinning effect caused by the introduction of the high dielectric constant material layer limits the threshold voltage adjusting effect of the work function adjusting layer, and the energy band adjusting layer and the work function adjusting layer cooperate to better adjust the threshold voltage. In addition, after SIGE CHANNEL is introduced, junction Leakage (Junction Leakage) is obviously increased due to the adaptation of energy bands, and the Junction Leakage is more cared for by a thick oxygen device (THICK DEVICE) in the circuit, so that only SIGE CHANNEL below the gate structure is reserved, and the Junction Leakage is avoided.

In yet another embodiment of the present disclosure, reference is made to fig. 19, which illustrates a schematic structural diagram of a memory 50 provided by an embodiment of the present disclosure. As shown in fig. 19, the memory 50 includes the aforementioned semiconductor structure 10. For example, the memory 50 includes, but is not limited to, dynamic Random Access Memory (DRAM).

In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

While the invention has been described with respect to certain embodiments, it will be apparent to those skilled in the art that various changes and substitutions can be made without departing from the scope of the invention. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, the semiconductor structure comprising a first device structure and a second device structure;

2. The semiconductor structure of claim 1, wherein,

The area of the first grid structure is larger than or equal to the area of the first energy band adjusting layer, and the area of the second grid structure is larger than or equal to the area of the second energy band adjusting layer.

3. The semiconductor structure of claim 1, wherein the first band adjustment layer is silicon germanium (SiGe) and the second band adjustment layer is SiGe;

4. The semiconductor structure of claim 3, further comprising a third device structure and a fourth device structure, wherein the third device structure and the fourth device structure are each N-type transistors;

5. The semiconductor structure of claim 4, wherein the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure comprises:

a gate dielectric layer;

the conductive layer is positioned above the gate dielectric layer;

An insulating layer over the conductive layer.

6. The semiconductor structure of claim 4, wherein the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure comprises:

a gate dielectric layer;

a conductive layer over the work function adjustment layer;

An insulating layer over the conductive layer.

7. The semiconductor structure of claim 5 or 6, wherein,

In the first gate structure or the third gate structure, the gate dielectric layer includes a gate oxide layer;

8. The semiconductor structure of claim 5 or 6, wherein the conductive layer comprises:

A polysilicon layer;

And a metal layer positioned above the polysilicon layer.

9. The semiconductor structure of claim 5, wherein the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure further comprises:

10. The semiconductor structure of claim 6, wherein the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure further comprises:

11. A method of fabricating a semiconductor structure, the method comprising:

12. The method of manufacturing according to claim 11, wherein the method further comprises:

13. The method of manufacturing of claim 12, wherein the first device structure and the second device structure are both P-type transistors; the third device structure and the fourth device structure are both N-type transistors;

14. The method of manufacturing of claim 13, wherein the first gate structure, the second gate structure, the third gate structure, or the fourth gate structure further comprises a work function adjustment layer between the gate dielectric layer and the conductive layer.

15. The method of claim 13 or 14, wherein forming a first energy band adjustment layer in the first active region and a second energy band adjustment layer in the second active region comprises:

16. The method of manufacturing of claim 15, wherein after depositing a second energy band material layer over the second active region, the method further comprises:

17. The method of manufacturing according to claim 14, further comprising:

18. A memory comprising the semiconductor structure of any of claims 1-10.