FR3013505A1 - METHOD FOR CONVERTING AN ANALOGUE SIGNAL TO A DIGITAL SIGNAL AND THE ANALOGUE / DIGITAL CONVERTER CORRESPONDING - Google Patents

Abstract

A method of converting an analog signal into a digital signal, comprising providing a chain of "silicon on insulator" inverters, for example totally deserted to an ultrathin substrate and buried oxide, whose inverter inputs are mutually connected, applying at least one bias voltage difference to at least one semiconductor well (WA, WB) located beneath a buried insulating layer under said inverter chain such that the first inverter (INVi) of the chain has the lowest inversion threshold voltage and the last inverter (INVn) of the string has the highest inverting threshold voltage, each inverter having an inversion threshold voltage greater than the threshold voltage inverting the preceding inverter in the chain, supplying said analog signal to all inverter inputs, and obtaining said digital signal from the output signals of the inverter pourers.

Description

The invention relates to microelectronics and more particularly to any circuit requiring an array of reference scale voltages such as, for example, analog / digital data converters. Among the analog / digital converters (ADCs), a "flash" ADC is advantageously used in all applications where fast data conversion is imperative. A conventional flash ADC includes a network of comparators and a resistive scale with many resistors. But such a conventional flash CAN offers a complex comparator circuit and the passive scale suffers from a feedback noise introduced by the comparators. In addition, the use of a low ohmic scale would lead to high power consumption. According to one embodiment, a new flash ADC is proposed, which offers lower power consumption, lower complexity and a smaller area. Advantageously, according to one embodiment, the ADC uses a "silicon-on-insulator" (SOI) comparator chain, in particular ultra-thin substrate and buried oxide silicon-on-insulator comparators (SOI UTBB), such as inverting cells, by example of the CMOS inverters, and the polarization of a rear gate (ground plane) through the resistive path of the underlying semiconductor case (s) to provide the inverters with different inversion threshold voltages. According to one aspect, there is provided a method of converting an analog signal into a digital signal which comprises: - the supply of a chain of silicon-on-insulator inverting cells, in particular of totally deserted silicon-on-insulator inverting cells (FDSOI) with ultrathin substrate and buried oxide, for example CMOS inverters, having their mutually connected inverting cell inputs, - applying at least one bias voltage difference on at least one semiconductor well located under a buried insulating layer (BOX ) beneath said chain of inverting cells such that the first inverting cell in the chain has the lowest inverting threshold voltage and the last inverting cell in the chain has the highest inverting threshold voltage , each inverting cell having an inversion threshold voltage greater than the reversal threshold voltage of the inverting cell one preceding in the chain, - providing said analog signal on all the inverting cell inputs, and - obtaining said digital signal from the output signals of the inverting cells. The transistors of the inverting cell transistors are not connected to the ground or the power supply, but coupled to said at least one semiconductor casing through the buried insulating layer (BOX), the application of said at least one voltage difference of polarization on said at least one semiconductor wafer leads to applying a voltage just below the part of the buried insulating layer located under the transistors of each inverting cell, this voltage being different from one inverting cell to another because of the resistive path intrinsic of said at least one semiconductor well.

This thus changes the electrostatic control of the transistors of the inverting cells and shifts their threshold voltage and therefore the inversion cell inversion threshold voltage. In other words, the transistors of the inverting cells have a distinct substrate bias accessible through the intrinsic resistive path of said at least one semiconductor well. According to one embodiment, the application of said at least one polarization voltage difference comprises the application of a first bias voltage on a first semiconductor contact surface coupled to a first zone of said at least one semiconductor box located under said first inverting cell and a second biasing voltage on a second semiconductive contacting surface coupled to a second area of said at least one semiconductor well under said last inverting cell, said first and second areas being mutually coupled by a resistive area ( path) of said at least one semiconductor well extending between said first and second regions. And the resistive path is coupled to the transistors of the inverting cell transistors through the buried insulating layer (BOX). Each inverting cell may comprise a CMOS inverter or a common source mount transistor (NMOS or PMOS) associated with an active or passive load. In addition, the architecture of an inverting cell can be an asymmetric architecture ("single ended" in English) or a differential architecture. When using a differential architecture, each inverting cell comprises at least one differential pair of MOS transistors of the same type depending on the type of the cell (that is to say two NMOS transistors and / or two PMOS transistors). When each inverting cell comprises a CMOS inverter, each inverter comprises a group of at least one (depending on the type of architecture (asymmetric or differential)) NMOS transistor and a group of at least one (depending on the type of architecture (asymmetric or differential)) PMOS transistor. Although it is possible to arrange the groups of NMOS transistors of the inverters and the groups of PMOS transistors of the inverters over the same semiconductor well, it is easier to arrange the groups of NMOS transistors of the inverter chain. above a first semiconductor well and arranging the groups of PMOS transistors of the inverter chain above a second semiconductor well, which is different from the first semiconductor well. This allows in particular to choose the family of transistors, that is to say to put a same family of transistors above the corresponding box, for example NMOS transistors LVT (Low Threshold Voltage, low threshold voltage) and PMOS LVT transistors, or NMOS and PMOS transistors RVT (Regular Threshold Voltage) or NMOS LVT transistors and PMOS RVT transistors for example. This also allows easier distribution of the different threshold voltages. Furthermore, in combination with the arrangement of the NMOS transistors over a first semiconductor well and PMOS transistors over a second semiconductor well, the application of the at least one polarization voltage difference includes advantageously: the application of a first bias voltage difference on said first semiconductor well such that the first group of at least one NMOS transistor in the chain has the lowest threshold voltage and the last group of at least one NMOS transistor in the chain has the highest threshold voltage, each group of at least one NMOS transistor having a threshold voltage greater than the threshold voltage of the preceding group of at least one NMOS transistor in the chain, and applying a second bias voltage difference to said second semiconductor well such that the first group of at least one PMOS transistor of the hane has the highest threshold voltage in absolute value and the last group of at least one PMOS transistor in the chain has the lowest threshold voltage in absolute value, each group of at least one PMOS transistor having a voltage threshold in absolute value greater than the threshold voltage in absolute value of the preceding group of at least one PMOS transistor in the chain.

According to one embodiment, the application of said first polarization voltage difference comprises the application of a third bias voltage to a third semiconductor contact region coupled to a first zone of said first semiconductor box located under said first group of cells. at least one NMOS transistor of the chain and the application of a fourth bias voltage to a fourth semiconductor contact region coupled to a second zone of said first semiconductor well located under said last group of at least one NMOS transistor of the chain, said first and second regions of said first semiconductor well being mutually coupled by a resistive area (path) of said first semiconductor well between said first and second regions, and application of said second bias voltage difference includes application of a fifth bias voltage on a fifth semiconductor contact region coupled to a first zone of said second semiconductor well located under said first group of at least one PMOS transistor in the chain and applying a sixth bias voltage to a sixth semiconductor contact region coupled to a second zone of said second semiconductor well located under said last group of at least one PMOS transistor of the chain, said first and second zones of said second semiconductor well being mutually coupled by a resistive zone (path) of said second semiconductor well between said first and second areas. According to another aspect, a silicon-on-insulator analog-to-digital converter is proposed, in particular a totally desinverted silicon-on-insulator analog to digital converter with an ultra-thin substrate and buried oxide, which comprises: input means intended to receive an analog signal, output means for outputting a corresponding digital signal, a chain of silicon-on-insulator inverting cells, in particular fully descrossed silicon-on-insulator inverting cells with an ultrathin substrate and buried oxide, each inverting cell input being connected to said input means the inverting cell outputs being connected to said output means, a bias input means coupled to at least one semiconductor well located beneath a buried insulating layer under said inverting cell chain for receiving at least one bias voltage difference , said inve cell chain Furthermore, in the presence of said at least one bias voltage, the lower inverting threshold voltage is configured to provide the first inverting cell of the string with the lowest inverting threshold voltage. of the highest inversion and each inverting cell an inversion threshold voltage greater than the inversion threshold voltage of the previous inverting cell in the chain.

According to one embodiment, the input biasing means comprises: a first semiconductor contact region for receiving a first bias voltage and coupled to a first region of said at least one semiconductor well located beneath said first inverting cell, and a second semiconductor contact region for receiving a second bias voltage and coupled to a second zone of said at least one semiconductor well located beneath said last inverting cell, said first and second regions being mutually coupled by a resistive zone (path) of said at least one a semiconductor well extending between said first and second regions. According to one embodiment, each inverting cell is an inverter comprising a group of at least one NMOS transistor and a group of at least one PMOS transistor, and the chain of NMOS transistors groups of the inverters is placed above a first semiconductor box and the chain of PMOS transistors groups of the inverters is placed above a second semiconductor box, different from said first semiconductor box, and said input biasing means comprises: a first input biasing means coupled to said first semiconductor wafer for receiving a first bias voltage difference and a second input bias means coupled to said second semiconductor wafer for receiving a second bias voltage difference, said NMOS transistors group chain being further configured to provide the first group of at least one NMOS transistor of the chain, in the presence of ladit e first polarization voltage difference, the lowest threshold voltage, the last group of at least one NMOS transistor in the chain, the highest threshold voltage, and each group of at least one NMOS transistor a Threshold voltage greater than the threshold voltage of the preceding group of at least one NMOS transistor in the chain, said PMOS transistor group string being further configured to supply the first group of at least one PMOS transistor in the chain in the presence of said second bias voltage difference, the highest threshold voltage in absolute value, at the last group of at least one PMOS transistor in the chain, the lowest threshold voltage in absolute value, and to each group of at least one PMOS transistor, a threshold voltage in absolute value greater than the threshold value in absolute value of the preceding group of at least one PMOS transistor in the chain. According to one embodiment, said first input biasing means comprises a third semiconductor contact region for receiving a third bias voltage and coupled to a first region of said first semiconductor well located under said first group of at least one NMOS transistor of the chain and a fourth semiconductor contact region for receiving a fourth bias voltage and coupled to a second zone of said first semiconductor well located under said last group of at least one NMOS transistor of the chain, said first and second semiconductor second regions being mutually coupled by a resistive zone (path) of said first semiconductor well which extends between said first and second regions, and said second input bias means comprises a fifth semiconductor contact region for receiving a fifth voltage of polarization and coupled to a first zone of said second semiconductor well located under said first group of at least one PMOS transistor of the chain and a sixth semiconductor contact region for receiving a sixth bias voltage and coupled to a second zone of said second semiconductor well under said second a group of at least one PMOS transistor in the chain, said first and second regions of said second semiconductor well being mutually coupled by a resistive area (path) of said second semiconductor well which extends between said first and second regions. Although not required, it is preferred that all NMOS transistors have the same ratio of channel width to channel length. This allows in particular easier adjustment of the different threshold voltages. It is also preferable, although not required, that all PMOS transistors have the same ratio of channel width to channel length. Here again, this allows easier distribution of the different threshold voltages. In addition, of course, the ratio associated with the PMOS transistors is not necessarily equal to the ratio associated with the NMOS transistors. It is also preferable that the space between two inverting cells in the chain be the same. This makes it possible to have a constant threshold voltage gradient. According to another aspect, an integrated circuit is also proposed, which comprises a silicon-on-insulator analog / digital converter as defined above. Other advantages and features of the invention will appear on reading the detailed description of embodiments, which are in no way limiting, and the accompanying drawings, in which: - Figure 1 shows schematically a structure of an FDSOI UTBB transistor, Figures 2 and 3 schematically represent different types of transistors FDSOI UTBB, and Figures 4 to 14 relate more particularly to embodiments of the present invention.

Particular embodiments of the present invention using the "FDSOI UTBB" technology will now be described. In FIG. 1, the MOS transistor TR is produced on and above an SOI (silicon on insulator) substrate, which is here an FDSOI UTBB substrate. The SOI transistor TR is thus called "FDSOI transistor UTBB". It comprises a semiconductor film region 4 delimited laterally by an insulating region 2. A buried insulating layer 3, known to those skilled in the art under the name "box", is located under said semiconductor film region 4 and above. of a support substrate 1. Said support substrate 1 here comprises a semiconductor WLL box containing a buried electrode 5 which is also called "ground plane". This ground plane 5 is located under the buried insulating layer 3.

Generally, the ground plane 5 is obtained by implantation of high energy dopants and therefore has a PRF dopant profile as shown in FIG. 1. Consequently, the ground plane 5 is more doped than the remaining portion of the WLL box. The WLL box further comprises a contact region 7 which is more doped than the underlying portion 6 of the WLL box. This contact region makes it possible to polarize the semiconductor well WLL and therefore the ground plane 5 which therefore acts for the transistor as a "back gate". In addition, as shown in FIG. 1, to make this contact region 7, the insulating layer 3 has been opened. The contact region 7 is also delimited laterally by the insulating region 2. In a UTBB technology, the thickness of the semiconductor film 4 is about 10 nanometers, while the thickness of the insulating layer 3 is about 20 to 30 nanometers.

In a FDSOI UTBB technology, the semiconductor film is also completely deserted, which means that the doping of the semiconductor film 4 is that of the intrinsic semiconductor material, for example that of the intrinsic silicon.

The source and drain regions S and D are generally made by epitaxial growth over the semiconductor film 4. In addition, conventionally, the MOS transistor TR comprises an insulated gate region 2 comprising a gate material which may comprise, for example, a metal layer and / or a polycrystalline silicon layer. As shown schematically in Figures 2 and 3, it is possible, depending on the type of box, to have different families of MOS transistors. More specifically, in FIG. 2, the PMOS transistor is placed above an N WP type well in a P 1 substrate while the NMOS transistor is placed on top of a WN W type well in the substrate. 1. Accordingly, such transistors are referred to as RVT transistors, i.e., transistors that have a mean threshold voltage.

In addition, in FIG. 2, this configuration is a box configuration and standard ground plane. In comparison, in Figure 3, the configuration is what is known as a "box configuration and inverted ground plane". More specifically, the PMOS transistor is placed above a P WP type well while the NMOS transistor is placed above a WN type well. These transistors are thus called LVT transistors, that is to say transistors that have low threshold voltages. FIG. 4 represents an embodiment of a SOI UTBB CAN / digital converter according to the invention.

Specifically, the AD / D converter comprises a MIN input means for receiving an analog signal Vin and a chain of inverter FDSOI UTBB INVI-INVII. Each inverter input BEi is connected to the input means MIN.

The digital output signal is obtained from the inverter output signals provided at the outputs of the BSI-BSn inverters. Each inverter INVi comprises a NMOS transistor TNi whose source is connected to a lower voltage, for example the ground, and whose drain is connected to the inverter output BSi. The inverter INVi further comprises a PMOS transistor TPi whose source is connected to a higher voltage, for example a supply voltage Vdd, and whose drain is connected to the inverter output BSi.

In the present embodiment, the NMOS transistors chain TN i is placed above a first semiconductor casing WB, while the PMOS transistor chain TPi is placed above a second semiconductor casing WA, which is different and electrically isolated from the first semiconductor WB.

The analog / digital converter CAN further comprises a first input biasing means ZCB1, ZCB2 coupled to said first semiconductor box WB for receiving a first bias voltage difference VC-VD and a second input biasing means ZCA1, ZCA2 coupled to the second semiconductor woofer WA for receiving a second bias voltage difference VA-VB. As shown diagrammatically in FIG. 5, the CV curve of the output voltage Vs as a function of the input voltage VIN of an inverter has a first high level V2 followed by a second, lower level, VI. The first level V2 corresponds to a logic "1" while the second level VI corresponds to a logical "0". The logic output "1" is obtained when the input voltage VIN is lower than the inverting threshold voltage VTINv of the inverter while the logic output "0" is obtained when the input voltage VIN is greater than the inversion threshold voltage. In addition, as shown in FIG. 6, the inverter chain INVi is further configured to provide, in the presence of threshold voltage differences, the first invertor INVI of the string, the lowest inverting threshold voltage. VTinvi, at the last invertor INV 'of the chain the highest inversion threshold voltage VTI' '', and at each inverter INV, a inversion threshold voltage VTinvi greater than the inversion threshold voltage VTIi of the previous inverter INV1 in the chain. In the example of FIG. 4, to obtain the evolution of the inversion threshold voltage of FIG. 6, the NMOS transistors chain TN is configured to provide, in the presence of the bias voltage difference VC- VD, at the first NMOS transistor TNi of the chain, the lowest threshold voltage VTHNI, at the last NMOS transistor TN ,, of the chain, the highest threshold voltage VTHN ', and at each NMOS transistor a threshold voltage greater than the threshold voltage of the preceding NMOS transistor in the chain, as illustrated in FIG. 7.

Consider now the chain of PMOS transistors. This is configured to provide, in the presence of the second bias voltage difference VA-VB, the first PMOS transistor TP1 of the chain, the highest threshold voltage in absolute value (I VTHP1 I) to the last PMOS transistor. TP ,, of the chain, the lowest threshold voltage in absolute value (I VTHP ,,), and each PMOS transistor a threshold voltage in absolute value greater than the threshold voltage in absolute value of the PMOS transistor previous in the chain, as illustrated in FIG. 8. With respect to the first input biasing means, it comprises a third semiconductor contact region ZCB1 for receiving a third bias voltage VC. This contact region ZCB1 is coupled to a first zone of the first semiconductor well WB located under said first NMOS transistor TNI of the chain.

The first input biasing means further comprises a fourth semiconductor contact region ZCB2 for receiving the fourth bias voltage VD. This fourth contact region ZCB2 is coupled to a second zone of the first semiconductor well WB located beneath the last TN NMOS transistor of the chain. The first and second zones are mutually coupled by the resistive zone (path) of said first semiconductor well WB extending between said first and second zones. In addition, in FIG. 4, the resistors RB1-RB. + 1 represent the resistive path of the semiconductor well WB between said contact zone ZCB1 and the contact zone ZCB2. Moreover, the coupling of the transistor substrates to the ZCB1-RB1-RBn + 1-ZCB2 bias network in the circuit topology rather than to the power supply or to the ground leads to applying a voltage just below the portion of the layer. isolator located under each NMOS transistor, this voltage being different from one transistor to another due to the intrinsic resistive path of the WB box. This thus modifies the electrostatic control of the transistors and shifts their threshold voltage VTHN. More precisely, the threshold voltage VTHN of an NMOS transistor decreases when the substrate bias Vb of this transistor increases from 0 to Vdd in absolute value.

For example, in a 28nm FDSOI UTBB technology, the threshold voltage decrease is about 80 mV / V for thin gate oxide transistors and about 140 mV / V for gate oxide transistors. thick. Thus, if the voltage VC is the highest voltage, for example 2 volts, and if VD is the lowest voltage, for example the ground, the substrate bias of the NMOS transistor TN decreases from the first transistor TNI to the last one. transistor TN 'because of the resistive path of the semiconductor casing between the contact regions ZCB1 and ZCB2.

By analogy, the second input biasing means comprises a fifth semiconductor contact region ZCA1 for receiving a fifth bias voltage VA. This fifth semiconductor contact region ZCA1 is coupled to a first zone of the second semiconductor well WA located under the first PMOS transistor of the chain. The second input biasing means further comprises a sixth semiconductor contact region ZCA2 for receiving the sixth bias voltage VB. This sixth semiconductor contact region ZCA2 is coupled to a second zone of the second semiconductor well WA located under the last PMOS transistor of the chain. Here again, these two semiconductor contact regions ZCA1 and ZCA2 are mutually coupled by the resistive zone (path) of the second semiconductor well WA between said first and second zones ZCA1 and ZCA2. In addition, the resistors RAi-RAn + i represent the resistive path of the semiconductor case WA between the ZCA1 and ZCA2 contact regions.

Moreover, by analogy with the above description relating to the NMOS transistors, if VA is the highest voltage in absolute value, for example 2 volts, and if VB is the absolute low voltage phis, for example the mass, the first PMOS transistor TP1 has the highest threshold voltage in absolute value while the last transistor TPn has the lowest threshold voltage in absolute value. An example of a topology of such an analog / digital converter is shown in FIGS. 9 and 10. More specifically, the TNI-TNn NMOS transistors are placed on and above the semiconductor film region located above the box 4. semiconductor WB, while the PMOS transistors TP1-TPii are made on and above another semiconductor film region located above the semiconductor wafer WA. The two semiconductor film regions as well as the two semiconductor boxes are mutually isolated by the insulating region 2. Holes in the insulating region 2 and in the underlying buried insulating layer 3 make it possible to form the semiconductive contact regions ZCA1, ZCA2, ZCB1 and ZCB2.

In addition, the GR gate regions of all the transistors are mutually connected and this gate region comprises a first GRN branch forming the gate regions of the NMOS transistors and a second GRP branch forming the gate regions of the PMOS transistors. These two branches meet in a common branch GRA forming the input means MIN for receiving the analog signal Vin. In this topology, the NMOS transistor has the same first W / L ratio between the channel width and the channel length. The PMOS transistor also has the same second W / L ratio. It is well known to those skilled in the art that the threshold voltage of a MOS transistor also depends in first order on the length L of the transistor and in second order on the width W of the transistor. Thus, if all the transistors of a chain have the same W / L ratio, for example the same value of L and the same value of W, the setting of the different threshold voltages depends only on the voltage differences applied to both. ends of the chain. In addition, in this embodiment, the space DD between two inverters is the same. This makes it possible to have a constant inversion threshold voltage gradient. It would have been possible not to have the same width W and the same length L for the transistors of a chain. In this case, however, the setting of the different threshold voltages would have been more complicated. Although in some embodiments above the two semiconductor boxes located below the NMOS transistors and the PMOS transistors are electrically isolated, it would have been possible to have two different semiconductor boxes, but not electrically isolated, having for example a physical point in common where the electrical potential is the same for the two semiconductor boxes. It would also have been possible to have only a semiconductor box, located under the NMOS transistors and PMOS of the inverters. In the previous embodiments, each comparator or inverting cell is a CMOS inverter in an asymmetric architecture. It is possible, however, to use another type of inverting cell forming a comparator, such as a common source assembly transistor (NMOS or PMOS) associated with an active load (for example another transistor operating in the saturation region), possibly in a cascode version, or a passive load, such as a resistor or transistor operating in the triode region. All types of comparators may also have a differential architecture, as illustrated for example in FIG. 11. In this figure, each inverting cell CEL1, CEL2, comprises a differential pair of NMOS transistors in common source assembly TN11, TN12; TN21, TN22 associated with passive loads, such as resistors. Furthermore, as shown in FIG. 12, all the NMOS transistors TN11, TN21,... Having their gate connected to the inputs + BE1, BE2 +, ... share the same semiconductor well WB1, while all the NMOS transistors TN12, TN22, ... having their gate connected to the inputs - BEY, BE2-, ... share the same semiconductor well WB2. The two boxes WB1, WB2 are here mutually electrically isolated, although this is not mandatory, as explained above. Two contact areas ZCB11, ZCB21 respectively electrically coupled to both ends of the well WB1 are respectively adapted to receive the voltages VC and VD to bias the well WB1 with the voltage difference VC-VD.

Two contact areas ZCB12, ZCB22 respectively electrically coupled to both ends of the well WB2 are respectively adapted to receive the voltages VD and VC to bias the well WB1 with the voltage difference VD-VC.

It would also be possible, as shown in Figure 13, that all NMOS transistors share a same semiconductor WB3 box. In this example, it is assumed that the converter comprises six inverting cells TN11, TN12; ; TN61, TN62. The chain of NMOS transistors TN11-TN61 having their gates connected to the inputs + is located in a first part of the well WB3, while the chain of the NMOS transistors TN12-TN62 having their gates connected to the inputs - is located in a second part of the box WB3, TN61 and TN12 transistors being adj acents. In addition, two contact regions ZCB 13 and ZCB23 respectively electrically coupled to both ends of the box WB3 are respectively adapted to receive a voltage VC, while a third contact region ZCB33 is electrically coupled to the part of the box WB3 located between the transistors TN61 and TN12 and is adapted to receive a voltage VD. In FIG. 14, each inverting cell CEL1, CEL2, ... is a CMOS inverter in a differential architecture. More specifically, each inverter, for example the inverter CEL1, comprises a differential pair of NMOS transistors, for example TN11, TN12, and a differential pair of PMOS transistors, for example TP11, TP12. In addition, all NMOS transistors can share two different semiconductor chambers in the same manner as in FIG. 12, or the same semiconductor box in the same manner as in FIG. 13, whereas all the PMOS transistors can share either two other boxes. different semiconductors, ie another same semiconductor casing.

Claims (16)

REVENDICATIONS1. A method of converting an analog signal to a digital signal, comprising providing a "silicon-on-insulator" inverter cell chain (INVi) having their mutually connected inverting cell inputs, applying at least one difference of bias voltage on at least one semiconductor well (WA, WB) located under a buried insulating layer under said inverting cell chain such that the first inverting cell (INVi) of the string has the inverting threshold voltage lower and that the last inverting cell (INV ') of the string has the highest inverting threshold voltage, each inverting cell having an inverting threshold voltage greater than the inverting threshold voltage of the cell in the chain, supplying said analog signal to all the inverting cell inputs, and obtaining said digital signal from the output of the inverting cells. The method of claim 1, wherein applying said at least one bias voltage difference comprises applying a first bias voltage to a first semiconductor contact surface coupled to a first region of said at least one semiconductor box located under said first inverting cell (INVi) and a second bias voltage on a second semiconductive contact surface coupled to a second zone of said at least one semicortducer well located under said last inverting cell (INVii), said first and second regions being mutually coupled by a resistive zone of said at least one semiconductor well extending between said first and second regions. The method of claim 1 or 2, wherein each inverting cell is an inverter comprising a group of at least one NMOS transistor and a group of at least one PMOS transistor, and the chain of the NMOS transistor groups (TN ) of the inverter chain is disposed above a first semiconductor box (WB), the chain of the groups of PMOS transistors (TP,) of the inverter chain is arranged above a second semiconductor box ( WA), which is different from said first semiconductor case, and applying said at least one bias voltage difference comprises applying a first bias voltage difference (VC-VD) to said first semiconductor case (WB ) so that the first group of at least one NMOS transistor (TNi) of the string has the lowest threshold voltage and the last group of at least one NMOS transistor (TP ') of the string has the voltage threshold, each gr orpe of at least one NMOS transistor having a threshold voltage greater than the threshold voltage of the preceding group of at least one NMOS transistor in the chain, and the application of a second bias voltage difference (VA-VB ) on said second semiconductor well (WA) such that the first group of at least one PMOS transistor (TP1) of the string has the highest threshold voltage in absolute value and the last group of at least one transistor PMOS (TP ') of the chain has the lowest threshold voltage in absolute value, each group of at least one PMOS transistor having a threshold voltage in absolute value greater than the threshold voltage in absolute value of the preceding group d at least one PMOS transistor in the chain. The method of claim 3, wherein: applying said first bias voltage difference (VC-VD) comprises applying a third bias voltage (VC) to a third semiconductor contact region (ZCB1) ) coupled to a first region of said first semiconductor well located under said first group of at least one NMOS transistor (TNi) of the chain and applying a fourth bias voltage (VD) to a fourth semiconductor contact region ( ZCB2) coupled to a second zone of said first semiconductor well located under said last group of at least one NMOS transistors (TN) of the chain, said first and second regions of said first semiconductor well being mutually coupled by a resistive zone of said first semiconductor well which extends between said first and second zones, and the application of said second polarization voltage difference (VA-VB) com takes the application of a fifth bias voltage (VA) on a fifth semiconductor contact region (ZCA1) coupled to a first zone of said second semiconductor well located under said first group of at least one PMOS transistor (T131) of the chain and the application of a sixth bias voltage (VB) on a sixth semiconductor contact region (ZCA2) coupled to a second zone of said second semiconductor well located under said last group of at least one PMOS transistor (TP) of the chain, said first and second zones of said second semiconductor well being mutually coupled by a resistive zone of said second semiconductor well which extends between said first and second regions. 5. The method as claimed in claim 1, in which the supply of a chain of silicon-on-insulator inverting cells (INVi) comprises the provision of a totally desorbed silicon-on-insulator reverse-cell chain with an ultrathin substrate and buried oxide. (INVI). 6. "Silicon-on-insulator" analog-to-digital converter comprising input means (MIN) for receiving an analog signal, output means t (BSI-BS ') for outputting a corresponding digital signal, a chain of cells silicon-on-insulator invertors (INVi), each inverting cell input being connected to said input means, the inverting cell outputs being connected to said output means, input biasing means coupled to at least one semiconductor well (WA, WB) located beneath a buried insulating layer (3) beneath said inverting cell chain for receiving at least one bias voltage difference, said inverting cell string being further configured to supply the first inverting cell of the chain, in the presence of of said at least one bias voltage, the lowest inversion threshold voltage, to the last inverting cell of the n of the highest inversion threshold and each inverting cell an inversion threshold voltage greater than the inverting threshold voltage of the previous inverting cell in the chain. A silicon-to-insulator analog-to-digital converter according to claim 6, wherein said input biasing means comprises: a first semiconductor contact region for receiving a first bias voltage and coupled to a first region of said at least one a semiconductor well located under said first inverting cell (INV1), and a second semiconductor contacting region for receiving a second bias voltage and coupled to a second area of said at least one semiconductor well located beneath said last inverting cell (INV). said first and second zones being mutually coupled by a resistive zone of said at least one semiconductor well which extends between said first and second zones. A "silicon-on-insulator" analog-to-digital converter according to claim 6, wherein each inverting cell is an inverter comprising a group of at least one NMOS transistor and a group of at least one PMOS transistor, and the chain of the groups of NMOS transistors (TN,) of the inverters is placed above a first semiconductor casing (WB) and the chain of the groups of transistors PMOS (TP,) of the inverters is placed above a second semiconductor casing (WA ), different from said first semiconductor case, and said input biasing means comprises: a first input biasing means (ZCB1, ZCB2) coupled to said first semiconductor case for receiving a first bias voltage difference (VC-VD) anda second input biasing means (ZCA1, ZCA2) coupled to said second semiconductor well for receiving a second bias voltage difference (VA-VB), said transistor group chain s NMOS being further configured to supply to the first group of at least one NMOS transistor (TNI) of the chain, in the presence of said first bias voltage difference, the lowest threshold voltage, at the last group of at least one minus one NMOS transistor (TN ') of the chain, the highest threshold voltage, and at each group of at least one NMOS transistor 10 a threshold voltage greater than the threshold voltage of the preceding group of at least one NMOS transistor in the chain, said PMOS transistor group chain being further configured to supply to the first group of at least one PMOS transistor (TP1) of the chain, in the presence of said second bias voltage difference, the voltage of the highest threshold in absolute value, to the last group of at least one PMOS transistor (TP) of the chain, the lowest threshold voltage in absolute value, and to each group of at least one PMOS transistor, a threshold voltage in value r absolute greater than the absolute threshold threshold voltage of the previous group of at least one PMOS transistor in the chain. The "silicon-on-insulator" analog-to-digital converter according to claim 8, wherein: said first input biasing means comprises a third semiconductor contact region (ZCB1) for receiving a third bias voltage and coupled to a first zone of said first semiconductor well located under said first group of at least one NMOS transistor of the chain and a fourth semiconductor contact region (ZCB2) for receiving a fourth bias voltage (VD) and coupled to a second zone of said first semiconductor well located under said last group of at least one NMOS transistor in the chain, said first and second regions being mutually coupled by a resistive zone of said first semiconductor well extending between said first and second regions, and said second means of input bias comprises a fifth semiconductor contact region (ZCA1) for receiving a fifth bias voltage (VA) and coupled to a first region of said second semiconductor well located under said first group of at least one PMOS transistor of the chain and a sixth semiconductor contact region (ZCA2) for receiving a sixth bias voltage (VB) and coupled to a second region of said second semiconductor well located under said last group of at least one PMOS transistor in the chain, said first and second regions of said second semiconductor well being mutually coupled by a resistive zone of said second semiconductor well which extends between said first and second regions. A "silicon-on-insulator" analog-to-digital converter according to claim 8 or 9, wherein all NMOS transistors (TN) have the same ratio of channel width to channel length. A "silicon-on-insulator" analog-to-digital converter according to any one of claims 8 to 10, wherein all the PMOS transistors (TP;) have the same ratio of the channel width to the channel length. A silicon to insulator analog-to-digital converter according to any one of claims 6 to 11, wherein the space (DD) between two inverting cells of the chain is the same. A silicon to insulator analog-to-digital converter according to any one of claims 6 to 12, having a differential architecture. The "silicon on insulator" analog-to-digital converter according to claim 13, wherein each inverting cell comprises at least one differential pair of MOS transistors of the same type. A silicon to insulator analog-to-digital converter according to any one of claims 6 to 14, which is a totally desorbed silicon-on-insulator analog-to-digital (CAN) conveyor with an ultrathin substrate and buried oxide, and said silicon inverter cell chain. on insulator (INVi) is a chain of totally desorbed silicon-on-insulator cells with ultrathin substrate and buried oxide (INV,). An integrated circuit comprising an insulator silicon-to-digital converter (ADC) according to any one of claims 6 to 15.