EP3357159A1 - Elementary electronic circuit for stage of amplification or repeat of analog signals - Google Patents

Abstract

The invention relates to an electronic circuit (300) comprising: at least one first multi-gate transistor (301) comprising a first gate (g) and a second gate (bg) different from the first gate; and a regulation unit (303) designed to measure a variable representing the drain-source voltage (V_ds) of the first transistor and to apply a polarisation potential (V_bg) as a function of said variable to the second gate (bg) of the first transistor (301).

Description

 ELEMENTARY ELECTRONIC CIRCUIT FOR STAGE OF AMPLIFICATION OR RECOPIA OF ANALOG SIGNALS

Field

 The present application relates to the field of electronic circuits in general, and more particularly relates to the field of electronic circuits using MOS transistors operating in saturation mode to amplify or recopy analog signals.

Presentation of the prior art

 Many electronic circuits, for example voltage amplifiers or current mirrors, comprise at least one MOS transistor used in saturation mode to amplify or recopy an analog signal. A potential representative of the input signal to be amplified or recopied is generally applied to the gate or to the source of the transistor, and an output signal, an image of the input signal, is provided on a source or drain node of the transistor.

FIG. 1 is a circuit diagram of an example of a voltage amplification circuit comprising a MOS transistor T1 used in saturation mode. In the example shown, the transistor T1 is an N-channel transistor whose source (s) is connected to an application node of a low supply potential GND, for example ground, and whose drain ( ) is connected to a application node of a high power supply potential VDD higher than the low supply potential GND by means of a resistive load R, for example a resistor or a biased MOS transistor in saturation mode.

 In operation, an input voltage v-j to amplify

(referenced with respect to the GND node in this example), is applied to the gate (g) of the transistor T1. Provided that the frequency of the signal v-j is less than the cut-off frequency of the circuit, and that the amplitude of the signal v-j_ remains limited, the assembly of Figure 1 provides, on the drain (d) of the transistor T1, an output voltage v _Q (referenced relative to the node GND in this example), amplified image of the voltage v- j_. In small signals, the voltage gain G _v = v ₀ / v-j_ of the circuit is equal to the product -G _m * R, G _m being the transconductance of transistor Tl polarized in saturation mode, and R being the resistance of the load R. To obtain the desired amplification function, the output voltage v _Q must be between the drain-source voltage ^ _ssa - _| - Minimum to ensure the saturation operation of the transistor T1, and the voltage VDD-V, V being the voltage across the load R.

 FIG. 2 is an electrical diagram of an example of a current copying circuit, comprising a MOS transistor T1 used in saturation mode. In the example shown, the transistor T1 is an N-channel transistor whose source (s) is connected to an application node of a low supply potential.

GND, for example mass. The circuit of FIG. 2 further comprises a MOS transistor T2, for example identical to transistor T1. The transistors T1 and T2 are mounted in current mirror, the transistor T2 forming the input branch of the mirror, and the transistor T1 forming the output branch of the mirror. Source

(s) of the transistor T2 is connected to the source (s) of the transistor T1, the gate (g) of the transistor T2 is connected to the gate (g) of the transistor T1, and the drain (d) of the transistor T2 is connected to the gate (g) of the transistor T2. In operation, an input current ij_ to be copied is applied to the drain (d) of the input transistor T2. The gate (g) of the transistor T2 is auto-polarized so that the transistor T2 absorbs the input current ij_. The output transistor T1 being biased at the same gate-source voltage as the input transistor T2, the transistor T1 is traversed by an output current i _{Q that is} substantially identical to the input current ij_, or, if the transistors Tl and T2 have different dimensions, by an output current i _Q proportional to the input current ij_.

 A problem that arises in circuits of the type described in relation with FIGS. 1 and 2, and, more generally, in any circuit using a saturation mode MOS transistor for copying or amplifying an analog signal, lies in the fact that , Generally, the output conductance of a MOS transistor is relatively high, and varies depending on the drain-source voltage or transistor output voltage. This results in limited performance, especially in terms of gain for the amplification circuits, or in terms of copy accuracy for the current feedback circuits.

 Thus, there is a need for an elementary circuit behaving like a MOS transistor, but having, in saturation mode, a relatively low output conductance and substantially independent of its output voltage.

 For this, it has already been proposed to use an assembly called cascode, consisting of a series association of two transistors

MOS operating in saturation mode, one of the two transistors being mounted in a common gate, that is to say receiving on its gate a constant bias potential, making a copy of its source current on its drain, and another transistor receiving on its gate a potential representative of the input signal to be amplified or copied. A disadvantage of the cascode assembly however lies in the fact that it comprises two transistors in series, the two transistors to be kept biased in saturation mode to ensure the proper operation of the circuit. This results in an increase in minimum value of the output voltage for which the proper operation of the circuit is guaranteed, and therefore a decrease in the range of excursion of the output signals in which the proper operation of the circuit is guaranteed. This is particularly problematic for circuits made in advanced technology sectors, in which the supply voltage VDD is relatively low, typically of the order of 1 to 2 volts, which already significantly limits, in high value, the range. excursion of the output signals.

summary

 Thus, an embodiment provides an electronic circuit comprising: at least one first multi-gate MOS transistor comprising a first gate and a second gate distinct from the first gate; and a control unit adapted to measure a magnitude representative of the drain-source voltage of the first transistor and to apply on the second gate of the first transistor a bias potential depending on said magnitude.

 According to one embodiment, the variations of the bias potential applied by the control unit as a function of the variations of the drain-source voltage of the first transistor follow a law chosen so that, in saturation mode, the output conductance of the first transistor is lower than when a constant bias potential is applied to the second gate of the first transistor.

 According to one embodiment, the variations of the bias potential applied by the control unit as a function of the variations of the drain-source voltage of the first transistor follow a law chosen so that, in saturation mode, the output conductance of the first transistor is substantially independent of its drain-source voltage.

According to one embodiment, the first transistor comprises a channel forming region, a source region and a drain region laterally bordering the channel forming region, the first gate being disposed over the region. channel formation and being isolated from the channel formation region by an insulating layer, and the second gate being disposed below the channel forming region.

 According to one embodiment, the second gate is isolated from the channel formation region by an insulating layer.

 According to one embodiment, the first transistor is a FDSOI type transistor.

 According to one embodiment, the regulation unit comprises a second MOS transistor whose gate is connected to the drain of the first transistor, whose drain is connected to an application node of a first supply potential by a first resistor. and whose source is connected to an application node of a second supply potential different from the first supply potential by a second resistor.

 According to one embodiment, the control unit comprises digital circuits.

 According to one embodiment, the circuit comprises a plurality of first multi-gate MOS transistors each comprising a first gate and a second gate distinct from the first gate, in which the regulation unit is adapted to measure, for each first transistor, a magnitude representative of the drain-source voltage of the transistor, and to apply on the second gate of each first transistor a bias potential according to one or more of said magnitudes.

 According to one embodiment, the regulation unit comprises a calibration module adapted to determine the law of the variations to be applied to the bias potential as a function of the variations of the drain-source voltage of the first transistor, so that, in saturation mode , the output conductance of the first transistor is lower than when a constant bias potential is applied to the second gate of the first transistor.

According to one embodiment, the regulation unit comprises a calibration module adapted to determine the law of the variations to be applied to the bias potential as a function of the variations of the drain-source voltage of the first transistor, so that, in saturation mode, the output conductance of the first transistor is substantially independent of its drain-source voltage.

 According to one embodiment, the control unit is reconfigurable, the calibration module being adapted to configure the control unit to apply the determined law.

 Another embodiment provides an amplification circuit of an analog signal comprising at least one circuit of the aforementioned type.

 Another embodiment provides a circuit for copying a current comprising at least one circuit of the aforementioned type.

 Another embodiment provides a circuit for amplifying or copying a differential signal comprising at least one circuit of the aforementioned type.

Brief description of the drawings

 These and other features and advantages thereof will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings in which:

 Figure 1, previously described, is an electrical diagram of an example of a voltage amplification circuit;

 Figure 2, previously described, is an electrical diagram of an example of a current copy circuit;

 FIG. 3 is a simplified electrical diagram of an example of an embodiment of an elementary circuit that can be used in circuits for amplifying or copying analogue signals;

 Figure 4 is a schematic sectional view of an exemplary embodiment of a MOS transistor of the circuit of Figure 3;

Figures 5, 6 and 7 are diagrams illustrating the operation of the MOS transistor of Figure 4; Figure 8 is a diagram illustrating the operation of the elementary circuit of Figure 3;

 FIGS. 6a and 8b are diagrams corresponding respectively to FIGS. 6 and 8 and illustrating the operation of the circuit of FIG. 3 for another operating point of the MOS transistor;

 FIG. 9 is a circuit diagram of an example of a current feedback circuit comprising an elementary circuit of the type described in relation to FIG. 3;

 FIG. 10 is an electrical diagram of an example of a voltage amplification circuit comprising an elementary circuit of the type described in relation to FIG. 3;

 FIG. 11 is an electrical diagram of another example of a current copying circuit comprising an elementary circuit of the type described with reference to FIG. 3;

 Fig. 12 is an electrical diagram of an exemplary implementation of the current copying circuit of Fig. 11; Fig. 13 is an electrical diagram of another exemplary implementation of the current copying circuit of Fig. 11; and

 FIG. 14 is a circuit diagram of another example of a voltage amplification circuit comprising an elementary circuit of the type described with reference to FIG. 3.

detailed description

The same elements have been designated with the same references in the various figures and, moreover, the various figures are not drawn to scale. In the following description, when reference is made to absolute position qualifiers, such as the terms "forward", "backward", etc., or relative, such as the terms "above", "below", ""superior","lower", etc., or with qualifiers for orientation, such as the terms "horizontal", "vertical", "lateral", etc., reference is made to the orientation of the sectional view of FIG. 4, it being understood that, in practice, the elements described may be oriented differently. Unless otherwise specified, the terms "approximately", "substantially", "about", "almost" and "in the order of" mean within 10%, preferably within 5%. In the present description, the term "connected" is used to denote a direct electrical connection, without intermediate electronic component, for example by means of one or more conductive tracks, and the term "coupled" or the term "connected", for designate either a direct electrical connection (meaning "connected") or a connection via one or more components.

 FIG. 3 is a simplified electrical diagram of an example of an embodiment of an elementary circuit 300 that can be used, in particular, in circuits for amplifying or copying analogue signals, this circuit behaving like a MOS transistor, but presenting in saturation mode, a relatively low output conductance and substantially independent of its output voltage.

 The circuit 300 comprises a MOS transistor 301. In the example shown, the transistor 301 is an N-channel transistor whose source (s) is intended to be connected to an application node of a low supply potential GND , for example the ground (for example a potential equal to 0 V), and whose drain (d) is intended to be connected to an application node with a high supply potential V DD greater than the low supply potential GND, for example via a resistive load not shown.

According to one aspect of an embodiment, the transistor 301 is a double-gate transistor, that is to say that it comprises a channel forming region (c) (FIG. 4) laterally lined on the one hand by a source region (s) and secondly by a drain region (d), and that it further comprises a first control grid (g) or front face grid disposed above the region of channel formation and isolated from the channel formation region by an insulating layer, and a second control gate (bg) or back-face gate, disposed under the channel formation region. In such a transistor, the current flowing between the drain (d) and the source (s) of the transistor is a function not only of the potential applied to the front face gate (g) of the transistor, but also of the potential applied to its gate. back side (bg). In particular, the threshold voltage of the transistor, that is to say the minimum voltage to be applied between the front face gate (g) and the source (s) of the transistor to make the transistor passing, depends on the potential applied to the rear face gate (bg) of the transistor.

 The circuit 300 comprises a regulating unit 303 adapted to measure a magnitude representative of the drain-source voltage of the transistor 301, and to apply to the rear face gate (bg) of the transistor 301 a bias potential (referenced with respect to the node GND in this example) function of the measured quantity. In the example shown, the regulation unit 303 is connected to the source (s) and the drain (d) of the transistor 301, as well as to the rear face gate (bg) of the transistor 301, and is adapted to measure the drain-source voltage of the transistor 301, and to apply on the rear face gate (bg) of the transistor 301 a bias potential depending on the measured drain-source voltage.

 FIG. 4 is a diagrammatic sectional view of an exemplary embodiment of the MOS transistor 301 of the circuit of FIG. 3. In this example, the transistor 301 is a SOI type transistor.

(Semiconductor On Insulator). The transistor 301 is made in and on a semiconductor-on-insulator structure comprising a vertical stack of a semiconductor support substrate 401 coated with a layer 403 of an insulating material, the layer 403 being itself coated with a semiconductor layer 405. The lower face of the semiconductor layer 405 is in contact with the upper face of the insulating layer 403, and the lower face of the insulating layer 403 is in contact with the upper face of the support substrate 401. The transistor 301 is delimited laterally by isolation trenches 407, for example filled with oxide, extending substantially vertically from the upper face of the semiconductor layer 405, passing through the semiconductor layer 405 and the insulating layer 403, and extending into the support substrate 401, for example up to the underside of the substrate 401.

 The transistor 301 comprises, in the semiconductor layer 405, within the region delimited by the trenches 407, a channel forming region (c), as well as a source region (s) and a drain region ( d) laterally bordering the channel formation region (c). In this example, the source (s) and drain (d) regions and the channel formation region (c) extend over the entire thickness of the layer 405. The channel formation region (c) is of conductivity type opposite to that of the source (s) and drain (d) regions. For example, for an N-channel transistor, the channel forming region (c) is N-type doped, and the source (s) and drain (d) regions are P-type doped. support 401 may be of the same conductivity type as the channel forming region (c), or of opposite conductivity type.

 The transistor 301 comprises, above the channel forming region (c), a control gate (g) isolated from the channel forming region (c) by an insulating layer 409, for example an oxide layer . The gate (g) corresponds to the front face gate of the transistor 301. The lower face of the gate (g) is in contact with the upper face of the insulating layer 409, the lower face of the insulating layer 409 being in contact with the the upper face of the channel forming region (c).

 In this example, the backplane gate (bg) of the transistor 301 is formed by the substrate region 401 disposed under the channel forming region (c). Thus, the backside grid (bg) is isolated from the channel forming region (c) by the layer 403.

In a preferred embodiment, the transistor 301 is a FDSOI type transistor, that is to say a SOI transistor. wherein the channel forming region (c) is fully depleted in the absence of polarization of the transistor. Indeed, in an FDSOI transistor, the variations of the control potential applied to the rear face gate (bg) of the transistor cause significant variations in the threshold voltage of the transistor, and therefore the current flowing in the transistor when the latter leads. . As will be clear from the following description, the FDSOI transistors are particularly adapted to the embodiment of the circuit 300 of FIG. 3. More particularly, the illustrative diagrams of FIGS. 5, 6, 7 and 8, which will be described below, are plotted for a transistor 301 of the type generally designated in the art by the acronym UTBB-FDSOI (English "Ultra Thin Body and Box Fully Depleted Silicon On Insulator" - FDSOI transistor to regions of ultra-thin buried body and oxide), with a gate length of the order of 28 nm.

 The described embodiments are however not limited to the case where the transistor 301 is of the SOI or FDSOI type. More generally, the described embodiments apply to all types of MOS transistors with two control gates respectively arranged on the front side side and the rear side side of the channel forming region of the transistor. By way of example, the described embodiments are compatible with a bulk type MOS transistor 301, comprising a semiconductor body region disposed under the channel forming region, the upper face of which is in contact with the lower face. of the channel formation area. In this case, the back-face gate is constituted by the body region of the transistor, and is not isolated from the channel-forming region.

FIG. 5 is a diagram representing a curve CQ illustrating the evolution of the drain-source current I _s (in microamperes, on the ordinate) of the transistor 301, as a function of its drain-source voltage V _S (in volts, on the abscissa ). The curve CQ corresponds to the case where the potential V ^ g applied to the grid of rear face (bg) of the transistor 301 is zero (that is to say substantially equal to the potential of the node GND). In addition, the curve CQ is plotted for a voltage Vg _S between the front face gate (g) and the source (s) of the transistor 301 constant and greater than the threshold voltage of the transistor (that is to say that the transistor 301 is biased in saturation mode).

As shown in Figure 5, the drain-source current increases continuously from 0 to about 1 μΑ for a voltage V ^ _s increasing from 0 to about 1 V. The growth of the CQ curve is non-linear, which shows although the output conductance of the transistor 301 is dependent on the output voltage V _s of the transistor. It is further observed that the slope of the curve CQ increases with the output voltage V _s , which shows that the output conductance of the transistor 301 degrades (increases) when the output voltage V _s increases.

FIG. 6 is a diagram representing, as in FIG. 5, the evolution of the drain-source current (in microamperes, on the ordinate) of the transistor 301, as a function of the drain-source voltage V _s (in volts, on the abscissa) , of this transistor. In Figure 6, have been shown the curve CQ diagram of Figure 5, and curves _C] _, C2, C3, C4, C5, Cg, C7, Cg, C9 and C] _ Q representing the evolution of the current 1 ^ 5 as a function of the voltage V _s under the same polarization conditions of the front face gate (g) as in the case of the CQ curve, but with different potentials V g applied to the gate of rear face (bg) of the transistor 301. In the example shown, the curves C] _, C2, C3, C4, C5, Cg, C7, Cg, C9 and C] _ Q respectively correspond to potentials V ^ g of 0.1 V, 0.2 V, 0.3 V, 0.4 V, 0.5 V, 0.6 V, 0.7 V, 0.8 V, 0.9 V and 1 V.

As shown in Figure 6, regardless of the bias potential V ^ g applied to the gate of rear side of the transistor, the drain-source current increases continuously, but nonlinear, for a voltage V increasing _s 0 V to about 1 V, with a slope increasing as the output voltage V ^ _s increases. In addition, in this example, for a voltage V ^"ds given, the drain-source current is even higher than the potential V ^ g is high. In fact, it was considered in this example a transistor 301 wherein an increase in the bias potential applied to the gate of rear face (bg) of the transistor results in a decrease in the threshold voltage of the transistor, and therefore in an increase in the current flowing through the transistor for a given gate-source voltage greater than the threshold voltage of the transistor. the variation of the threshold voltage of the transistor 301 as a function of the bias potential applied to the rear face gate (bg) of the transistor is substantially linear.

The control unit 303 of the circuit of FIG. 1 is configured to automatically adjust the potential V g applied to the rear face gate (b g) of the transistor 301 as a function of the voltage V _s or a magnitude representative of the voltage V ^" ds' so that, for a given gate-source voltage Vg _S , the drain current of the transistor 301 is substantially constant over a voltage range V _s in which the transistor operates in saturation mode. to obtain an output conductance (ratio between the resulting variation of the current and the corresponding variation of the voltage V _s ) which is particularly low, and in particular significantly lower than if the transistor 301 were used alone (without the control unit 303).

F for determining the law of variation of the potential V ^ g depending on the output voltage V _s, for obtaining a substantially independent drain current of the output voltage V _s can be used a diagram of the type shown in Figure 6, and determine the couples voltage V ^ _s and potential V] 3g for which the current I ^ _s remains equal to a constant target value Ids-targ- the target value ^was Ids-targ P t be selected according the gate-source voltage Vg _S for which the diagram has been plotted. The law f of variation of the potential V ^ g as a function of the output voltage V _s may be approximated by interpolation, for example by linear interpolation, from the determined pairs of values.

Figure 7 is a diagram showing the law VKG = f (^ _s) obtained from the curves of the diagram of Figure 6 to a target value Ids-targ of the current I s ^ 0.5 μΑ. The potential V ^ g and the voltage V ^ _g are represented, in volts, respectively on the ordinate axis and on the abscissa axis. As shown in FIG. 7, the law f is a decreasing quasi-linear law. More particularly, in the example shown, the potential V g to be applied to the rear face gate (b g) of the transistor 301 to maintain a substantially constant drain-source current decreases quasi-linearly from a high value approximately equal to 0, 9 V for a voltage V ^ _g of the order of 0.2 V, to a low value substantially zero for a voltage V ^ _g of the order of 0.75 V.

FIG. 8 is a diagram illustrating the behavior of the circuit 300 of FIG. 3 when the regulation unit 303 applies to the rear face gate (bg) of the transistor 301 a potential V g varying according to the output voltage V _ug of the transistor 301 according to the law f shown in Figure 7. More particularly, Figure 8 includes a curve C _reg showing variation of drain-source current I ^ s ⁽ⁱⁿ microamperes on the ordinate) of the transistor 301, in depending on the drain-source voltage V _g (in volts, on the abscissa) of the transistor. The curve C _re g is plotted for a gate-source voltage Vg _S constant equal to the gate-source voltage Vg _S applied for the drawing of the diagrams of Figures 5 and 6 and for the determination of the law f shown in Figure 7. A As a comparison, the diagram of FIG. 8 furthermore comprises the same curve CQ as the diagrams of FIGS. 6 and 7, representing the evolution of the current I ^ s ^{as a} function of the voltage V ^ _g when a potential V ^ g no is applied to the rear face gate (bg) of the transistor 301. In addition, the diagram of FIG. 8 comprises a horizontal line of equation Ids ^ ds-targ 'representing the target value of the current used to determine the law f from the diagram of FIG.

As shown in Figure 8, after a short growth period (during which the transistor 301 operates in ohmic region) from a zero current value for a zero voltage V _s until a current value ¾s ⁼ ¾s- targ F ^{or a} voltage V _s of the order of 0.2 V, CREG curve stabilizes at a value substantially constant current, the Ids-targ order of ^{'on a pl <3 rd} voltages V ^ _s ranging from 0.2 to 1 V. Thus, it has a substantially independent output conductance of the voltage ^ _s, and less than that of the transistor 301 only, over the range of voltages V ^ _s from 0 , 2 to 1 V. Of course, in practice, once the law f determined and applied automatically by the control unit 303, the gate-source voltage Vg _S applied to the transistor 301 can take values different from the value used to determine the law f, for example representative values of an input signal to amp to read or recopy by means of the transistor 301, and the drain-source current flowing in the transistor may take a different value from the target current Ids-targ chosen to define the law f.

The law f can be determined at the design of the elementary circuit 300, for example by means of a diagram of the type shown in FIG. 6, this diagram being obtainable by simulation or by measurement, and possibly comprising a number of curves Cj_ (corresponding at different potentials V ^ g, with i integer ranging from 1 to 10 in the example of Figure 6) different from that of Figure 6. The law f can be implemented in a fixed manner in the control unit 303, for example by means of analog circuits and / or by means of digital circuits. Alternatively, the law f can be implemented in a reconfigurable manner in the control unit 303, for example by means of analog circuits and / or by means of digital circuits. By way of example, the regulation unit 303 may comprise a calibration module, not shown, adapted to determining the law f to be applied so that the transistor 301 has an output conductance substantially independent of its drain-source voltage, and to reconfigure the regulating unit 303 to apply the determined law f. The calibration module is for example connected to the source (s) and drain (d) nodes and to the rear face gate (bg) of the transistor 301, as well as to the front face gate (g) of the transistor 301. (by a link not shown in Figure 3). During calibration phases, the calibration module is for example adapted to acquire a series of curves Cj_ of the type shown in FIG. 6, and then, from these curves, to determine the law f of variation of the potential V ^ g depending voltage ^ _s , to obtain an output conductance substantially independent of the voltage V ^ _s in a desired range of voltage excursion V ^ _s . To acquire the curves C i, the calibration module can in particular be adapted to vary the drain-source voltage V _s applied to the transistor 301, and measuring the drain-source current flowing through the transistor 301. The determination of the law f can be performed by means of a digital processing unit (not shown). The provision of a reconfigurable regulation unit 303 and of a calibration module has the advantage of making it possible to adjust the law f in the event of any drift, linked for example to temperature variations, to the aging of the transistor 301, or to any other drift factor, for example a drift of a bias voltage of the transistor.

FIG. 6bis is a diagram representing by way of illustration curves C ₀ ', C 1', C ₂ ', C ₃ ', C ₄ ', C ₅ ', C ', C ₇ ', C ', C', C ₁₀ ' similar to the curves CQ, CI, C ₂ , C ₃ , C ₄ , C ₅ , C 8, C 7, C 8, C 9, C 10 of FIG. 6 but for a different operating temperature of the transistor 301, and / or for a state of aging different from the transistor, and / or for a different bias voltage applied to the front face gate of transistor 301. As shown in FIG. 6a, the curves C ₀ ', Ci', C ₂ ', C ₃ ', C ₄ ', C ₅ ', C ₆ ', C ₇ ', C ₈ ', Cg', C ₁₀ 'representative of the evolution of the current as a function of the Voltage ν ₃ for different values of the potential V 4 g no longer have exactly the same shape as the curves C 0, C 1, C 2, C 3, C 4, C 5, C 6, C 7, C 8, C 8, C 14. Q of the example of Figure 6. During a calibration phase, the law f can be updated from these new curves. The target value Ids-targ 'of the current I ^ _s used to determine the new law f may be the same as during the initial calibration, or, as shown in FIG. 6bis, a different target value. In the example shown, the value Ids-targ ' ^is of the order of 1 μΑ. The new law f (not shown) obtained from the curves of FIG. 6bis and for a target value Ids-targ 'of the order of 1 μΑ is, as in the example of FIG. 7, substantially linear.

Figure 8a is a diagram resuming, in solid lines, the curves CQ, C g and _re-targ Ids of ^ ^a Figure 8, and further comprising corresponding curves CQ, C _reg 'and Ids- targ'^'in interrupted line, illustrating the behavior of the circuit 300 of FIG. 3 when the regulation unit 303 applies to the rear face gate (bg) of the transistor 301 a potential V ^ g varying as a function of the output voltage ^" d _s of the transistor according to the new law f determined from the curves of FIG 6bis.As it appears in FIG 8a, after a short growth period (during which the transistor 301 operates ohmic regime), since a current value Ids zero for a voltage v ^"d _s zero, until a current value Ids ⁼ ^ ds-targ 'P ° ^{ur voltage"} d _s of the order of 0.3 V, curve CREG' stabilizes at a value of constant current Ids, of the order of Ids-targ '' ^{on a} pl ^{a <} 3 ^e of voltages ^" d _s ranging from 0.3 at 1 V.

 FIG. 9 is a circuit diagram of a current copying circuit comprising an elementary circuit 300 of the type described above. FIG. 9 details in particular an example of an analog embodiment of the regulation unit 303 of the elementary circuit 300.

The control unit 303 comprises a MOS transistor 901, for example, but not necessarily, of the same type of conductivity than the transistor 301, that is to say N channel in the example shown. In this example, the transistor 901 is a double-gate transistor of the same nature as the transistor 301. For example, the transistor 901 is identical to the transistor 301 (to manufacturing dispersions). Alternatively, the transistor 901 may be different from the transistor 301. For example, the transistor 901 may be a single gate transistor (i.e., having no backplane gate). Alternatively, the transistor 901 may be of the opposite conductivity type to the transistor 301 (that is, P-channel in this example), and / or have a different geometry than that of the transistor 301. The unit regulator 303 further comprises a resistor RI connecting the drain (d) of the transistor 901 to the node VDD, and a resistor R2 connecting the source (s) of the transistor 901 to the node GND. The front face gate (g) of the transistor 901 is connected to the drain (d) of the transistor 301. In this example, the rear face gate (bg) of the transistor 901 is connected to the node GND, that is to say that transistor 901 is used as a single gate transistor. Furthermore, the drain (d) of the transistor 901 is connected to the rear face gate (bg) of the transistor 301.

The operation of the elementary circuit 300 of FIG. 9 is as follows. The drain-source voltage V _s of the transistor 301 is transferred between the front face gate and the source of the transistor 901. Thus, the current flowing through the transistor 901 depends on the value of the drain-source voltage V _s of the transistor.

This current causes the source potential of the transistor 901 to grow because of the voltage drop across the resistor R2. This limits the growth of the current flowing through the transistor 901. It can be shown that if the product of the transconductance gm of the transistor 901 by the value of the resistor R2 is large in front of 1, then the drain-source current of the transistor 901 varies substantially linearly. depending on the drain-source voltage V ^ _s of the transistor 301. As a result, the potential of the drain node (d) of the transistor 901 varies substantially linearly as a function of the drain-source voltage ds of the transistor 301. The drain node (d) of the transistor 901 being connected to the rear face gate (bg) of the transistor 301, the potential V ^ g applied to the rear face gate (bg) of the transistor 301 (referenced relative to the node GND) varies substantially linearly as a function of the drain-source voltage V _s of the transistor 301. More particularly, the variation law of the potential V g of the transistor 301 as a function of the voltage V _s of the transistor 301 is a decreasing linear law whose ordinate at the origin and the slope depend on the values of the resistors RI and R2. The resistors R1 and R2 are for example chosen to obtain a law f of the type shown in the diagram of FIG. 7. As a variant, the resistors R1 and R2 may be replaced by resistors or programmable transistors, which makes it possible to make the control unit 303 reconfigurable.

 The current feedback circuit of FIG. 9 further comprises a MOS transistor 903 of the same conductivity type as the transistor 301, that is to say N-channel in the example shown. In this example, the transistor 903 is a double-gate transistor of the same nature as the transistor 301. The transistor 903 is for example identical to the transistor 301 (to manufacturing dispersions near). By way of a variant, the transistor 903 is a transistor of the same gate length and gate insulation thickness as the transistor 301, but with a different gate width.

The transistors 903 and 301 are mounted in current mirror. The transistor 903 forms the input branch of the current mirror and the transistor 301 forms the output branch of the current mirror. More particularly, the source (s) of the transistor 903 is connected to the source (s) of the transistor 301, the front face gate (g) of the transistor 903 is connected to the front face gate (g) of the transistor 301, and the drain (d) of the transistor 903 is connected to the front face gate (g) of the transistor 903. In this example, the sources (s) of the transistors 903 and 301 are connected to the GND node, and the drain (d) of the transistor 903 is connected to the VDD node via a current source 905 delivering the current ij_ to copy. In addition, in this example, the backplane gate (bg) of transistor 903 is connected to node GND.

The operation of the circuit of FIG. 9 is as follows. When a drain-source current i-j_ is applied to the transistor 903, for example by the current source 905, the front face gate (g) of the transistor 903 is self-biasing so that the transistor 903 absorbs the current ij_. The output transistor 301 being biased at the same gate-source voltage as the input transistor 903, the transistor 301 is traversed by an output current i _Q substantially identical to the input current ij_ (or proportional to the current ij_ if the transistors 903 and 301 have different dimensions). In this example, the drain node (d) of the transistor 301 constitutes an output node of the current copying circuit. The control unit 303 allows the output conductance of the transistor 301 to be relatively small and substantially independent of the drain-source voltage of this transistor, i.e. the output voltage of the circuit. As a result, the circuit of FIG. 9 makes it possible to perform a high accuracy copy of the input current ij_.

 FIG. 10 is an electrical diagram of a voltage amplification circuit comprising an elementary circuit 300 of the type described with reference to FIG.

The elementary circuit 300 of the circuit of FIG. 10 is identical to the elementary circuit 300 of the circuit of FIG. 9. In the circuit of FIG. 10, the source (s) of the transistor 301 is connected to the node GND. Alternatively, the source (s) of the transistor 301 may be connected to an application node of a reference potential distinct from the GND potential. For example, the source (s) may be connected to the GND node via a resistor (not shown). The circuit of FIG. 10 further comprises a resistive load R, for example a resistor or one or more MOS transistors, or one or more circuits. 300 of the type described in relation to FIG. 3, connecting the drain (d) of the transistor 301 to the VDD node.

The operation of the circuit of Figure 10 is as follows. When an input voltage v_j_ to be amplified (referenced with respect to the GND node in this example) is applied to the front face gate (g) of the transistor 301, the circuit of FIG. 10 provides, on the node of drain (d) of the transistor 301, an output voltage v _Q (also referenced with respect to the GND node in this example) amplified image of the voltage v-j_. In small signals, the voltage gain G _v = v ₀ / v-j_ of the circuit is of the order of ~ G _m * R _or - _| -, G _m being the transconductance of the transistor 301, and R _or t being the equivalent resistance between the resistance of the load R and the resistor R ^ _s output of the transistor 301, placed in parallel in the small signal equivalent arrangement. R ^ _s output resistance of the transistor 301 is equal to the inverse of the output conductance (Rds ⁼ l /% ls) · ^Assuming R great before Rd _s, ^ ^e circuit voltage gain Gv may be approximated by = -Gm * Rds = -Gm / gds. The control unit 303 allows the output conductance of the transistor 301 to be relatively low and substantially independent of the drain-source voltage of this transistor, i.e. the output voltage of the circuit. As a result, the circuit of FIG. 10 makes it possible to achieve faithful amplification of the input voltage v-j, with a high voltage gain due to the decrease in the output conductance of the assembly.

FIG. 11 is a circuit diagram of another example of a current feedback circuit comprising an elementary circuit 300 of the type described above. The circuit of FIG. 11 differs from the circuit of FIG. 9 mainly in that, in the example of FIG. 11, the regulation unit 303 of the circuit 300 regulates not only the potential of the backplane gate of the transistor 301 , but also regulates the potential of the rear face gate of transistor 903. In addition, to achieve regulation, unit 303 can take into account not only the drain-source voltage of transistor 301, but also the voltage drain-source of the transistor 903. This makes it possible to further improve the accuracy of copying the current ij_ and thus to obtain a particularly low output conductance. In FIG. 11, the regulation unit 303 has not been detailed, and is schematized by a block comprising an input inl connected to the drain node of the transistor 301, monitoring or monitoring the drain-source voltage of the transistor 301, a In2 input connected to the drain node of transistor 903, monitoring or monitoring the drain-source voltage of transistor 903, an out1 output connected to the backplane gate of transistor 301, regulating the potential applied to the backplane gate of transistor 301 , and an out2 output connected to the rear face gate of the transistor 903, regulating the potential applied to the rear face gate of the transistor 903. By way of example (not limiting), the outputs out1 and out2 of the regulation can be confused, that is to say that the same potential can be applied to the rear face gate of the transistor 301 and the rear face gate of the transistor 903. Alternatively, only the potent The potentials applied to the rear face gates of the transistors 301 and 903 can be defined by the same law, taking into account the signals inl and in2, and the backside gate of the transistor 903 can be regulated by the control unit 303. (out1 = out2 = f (in1, in2)), or by the same law taking into account only the signal inl for the transistor 301 and only the signal in2 for the transistor 903 (out1 = f (inl) and out2 = f ( in2)), or by separate laws f1 and f2 respectively taking into account the signal inl for the transistor 301 and the signal in2 for the transistor 903 (out1 = fl (inl) and out2 = f2 (in2)), or by laws f1 and f2 are distinct taking into account each of the signals in1 and in2 (out1 = f1 (in1, in2) and out2 = f2 (in1, in2)). As a variant, only the potential applied to the rear-face gate of the transistor 301 is regulated, by a law taking into account the single signal inl (outl = f (inl)), or by a law taking into account the signals inl and in2 (out1 = f (in1, in2)). In another variant, only the potential applied to the backplane gate of transistor 903 is regulated, by a law taking into account the only signal inl (outl = f (inl)), or by a law taking into account the signals inl and in2 (out2 = f (inl, in2)). FIG. 12 is an electrical diagram of an exemplary implementation of the circuit of FIG. 11. FIG. 11 details in particular an example of an analog implementation of the regulation unit 303 of the elementary circuit 300.

 In this example, the regulation unit 303 (not referenced in FIG. 12) is produced by a single wire (or conducting track) connecting the drain of the transistor 301 to the rear face gate (bg) of the transistor 903. in this example, the backplane gate (bg) of the transistor 301 is connected to the GND node. In other words, in the example of FIG. 12, by repeating the notations of FIG. 11, the regulation unit 303 has its input node in1 connected to its output node out2, its output node out1 connected to the node GND, and its input node in2 not used (not connected).

The operation of the elementary circuit 300 of FIG. 12 is as follows. The voltage applied to the rear-face gate of transistor 903 follows the drain-source voltage of transistor 301, which can vary for example between 0 and 1 V. When the drain-source voltage of transistor 301 increases, the threshold voltage of transistor 903 accordingly, the gate-source voltage applied to the two transistors of the mirror decreases to maintain the output current i _Q , i.e., the drain current of the transistor 301, substantially the same as the current input ij_ (or proportional to current ij_ if transistors 903 and 301 have different dimensions).

The slope of the variation curve of the output current i _Q as a function of the drain-source voltage of the transistor 301 can be controlled by varying the channel length (or gate length) of the transistors 301 and 903. for example, the channel length of transistors 903 and 301 is chosen so that this slope is substantially horizontal in a voltage range drain-source of the transistor 301, that is to say so that the current i _Q is substantially independent of the drain-source voltage of the transistor 301 in this operating range, so as to obtain an output conductance of the transistor 301 relatively low (compared to an assembly that does not include rear-end gate regulation).

 FIG. 13 is an electrical diagram illustrating an alternative embodiment of the circuit of FIG. 12.

 The circuit of FIG. 13 differs from the circuit of FIG. 12 in that, in the circuit of FIG. 13, the rear-face gate (bg) of the transistor 301 is connected not to the GND node but to the drain (d) of the Transistor 903. In other words, in this example, by repeating the notations of FIG. 11, the regulation unit 303 has its input node in1 connected to its output node out2, and its input node in2 connected to its output node outl.

 In the variant of Figure 13, the mounting of the two transistors 903 and 301 is symmetrical, so that the two transistors behave in the same manner.

The exemplary embodiments of FIGS. 12 and 13 apply in all moderate and low inversion modes of transistors 903 and 301. The drain voltage of transistor 301 controls the back-face gate of transistor 903 so as to decrease the front-end gate voltage common to the two transistors when the drain voltage of the transistor 301 increases, which leads to decrease the output conductance of the transistor 301 relative to a mounting having no rear-end gate regulation. By varying the size, and more particularly the gate length of the transistors, it is possible to modify the output conductance and the transconductance of the transistors. There is a gate length for which the transconductance compensates the output conductance. Beyond this grid length, it is possible to obtain a strong negative output resistance. FIG. 14 is a circuit diagram of another example of a voltage amplification circuit comprising an elementary circuit of the type described with reference to FIG.

The circuit of FIG. 14 is a differential voltage amplification circuit. The circuit of FIG. 14 differs from the circuit of FIG. 10 essentially in that, in the circuit of FIG. 14, the elementary circuit 300 is of the differential type. More particularly, in the example of FIG. 14, the elementary circuit 300 comprises the same elements as in the example of FIG. 3, and furthermore comprises a transistor 301 'identical or similar to the transistor 301. The source (s) of the transistor 301 'is connected to the source (s) of the transistor 301 in a common mode node v _mc . The common mode node v _mc is for example connected to a current source not shown in FIG. 14 supplying the pair of differential transistors. In the example of FIG. 14, the regulation unit 303 regulates the potential of the rear-face gate of the transistor 301 as a function of the drain-source voltage of this transistor, and regulates the potential of the back-face gate of the transistor. transistor 301 'as a function of the drain-source voltage of this transistor. In FIG. 14, the regulation unit 303 has not been detailed, and is shown schematically by a block comprising an input connected to the drain node of the transistor 301, monitoring the drain-source voltage of the transistor 301, an input connected to the drain node of transistor 301 ', monitoring the drain-source voltage of transistor 301', an output out connected to the rear-face gate of transistor 301, regulating the potential applied to the back-face gate of transistor 301, and an output out 'connected to the rear face gate of the transistor 301', regulating the potential applied to the rear face gate of the transistor 301 '. More generally, the potentials applied to the rear face grids of the transistors 301 and 301 'can be defined by the same law taking into account the signals in and in' (out = out '= f (in, in')), or by the same law taking into account only the signal in for the transistor 301 and only the signal in 'for the transistor 301' (out = f (in) and out '= f (in')), or by separate f and f laws respectively taking into account the signal in for the transistor 301 and the signal in 'for the transistor 301 '(out = f (in) and out' = f (in ')), or by separate f and f laws taking into account each of the signals in and in' (out = f (in, in ') and out '= f' (in, in ')).

The high potentials v i + and low v i of the differential voltage to be amplified are respectively applied to the gate node (g) of the transistor 301 'and to the gate node (g) of the transistor 301. v _Q v _Q + and low - of the amplified differential voltage output of the circuit are provided respectively at the drain node (d) of the transistor 301 and the drain node (d) of the transistor 301 '. The potentials high v _Q + and low v _Q - of the amplified differential output voltage of the circuit can be generated by resistors or load transistors not shown in FIG. 14 placed respectively between the drains of transistors 301 and 301 'and a high power supply. As an example, this high power supply is the VDD potential.

 It will be noted that unlike the cascode assembly, the elementary circuit 300 has the advantage of not limiting, with respect to circuits of the type described in relation to FIGS. 1 and 2, the range of excursion of the output voltages. in which the proper functioning of the circuit is guaranteed.

 Particular embodiments have been described.

Various variations and modifications will be apparent to those skilled in the art. In particular, although an exemplary embodiment has been described above in which the double gate MOS transistor 301 of the elementary circuit 300 is an N-channel transistor, the embodiments described can be implemented with a transistor having P channel. The skilled person will then adapt the described examples to obtain the desired operation.

In addition, although an exemplary embodiment has been described in which the transistor 301 has a threshold voltage decreasing linearly as a function of the potential of bias V ^ g applied to its rear face grid (bg), the described embodiments are not limited to this particular case. Those skilled in the art will be able to implement the desired operation, and in particular to determine the law f making it possible to obtain an output conductance substantially independent of the drain-source voltage of the transistor 301, in the case where the threshold voltage of the transistor 301 increases when the potential V ^ g increases, and / or in the case where the variation of the threshold voltage of the transistor 301 as a function of the potential V ^ g is nonlinear. More generally, those skilled in the art will be able to adapt the described embodiments to all types of multi-gate transistors, and in particular to transistors having a number of gates greater than two.

In addition, the described embodiments are not limited to the exemplary embodiment of the control unit 303 described with reference to FIG. 9. In particular, other analog circuits adapted to automatically regulate the potential V ^ g of the transistor 301 as a function of its drain-source voltage can be provided. Moreover, the regulation unit 303 can be realized in digital form. By way of example, the regulation unit 303 may comprise a sampling and digitizing circuit of the drain-source voltage V _s of the transistor 301, a digital circuit adapted to determine, as a function of the value of the voltage V ^ _s measured, using the law f, the potential V ^ g for application to the gate rear side of transistor 301, and a digital-analog conversion circuit for applying to the transistor 301 the potential V ^ g determined. For example, the law f can be stored in the digital potential determination circuit V g, in the form of an analytical formula, or in the form of a correspondence table.

In addition, the described embodiments are not limited to the case where the control unit 303 is directly connected to the source and the drain of the transistor 301. Alternatively, the control unit can not directly measure the voltage drain-source V ^ _s transistor 301, but another magnitude representative of the voltage V ^ _s , and deduce from this magnitude, using the law f, the potential V ^ g to be applied to the rear face gate of the transistor 301 (and / or transistor 903).

In addition, the control unit 303 can be shared by several transistors 301. It is then assumed that the different transistors 301 all have substantially the same drain-source voltage V ^" ds' and the same potential Vg is applied to the gates rear of the different transistors 301. In this case, the regulation unit 303 can be connected to the source (s) and the drain (d) of a single transistor 301, but be connected to the rear face grids (bg ) This mode of operation is, for example, well suited to applications in which several identical or similar circuits, for example analogue signal copy or amplification circuits, are connected in parallel.

 Furthermore, the described embodiments are not limited to the examples of applications described in relation to FIGS. 9 and 10. More generally, the proposed elementary circuit 300 can be used in many circuits using MOS transistors operating under saturation to copy or amplify analog signals, for example voltage-voltage amplifiers, voltage-current amplifiers, current-voltage amplifiers or current-current amplifiers. In particular, the proposed elementary circuit 300 can be used to make circuits for copying or amplifying differential analog signals. In addition, the elementary circuit 300 can be used for other applications than for the amplification and / or the duplication of analog signals.

In addition, the described embodiments are not limited to the examples described above in which the control unit 303 comprises one or two inputs and one or two outputs. More generally, the control unit may have n inj inputs, or n is any integer greater than or equal to 1 and j is an integer from 1 to n, and m outputs outk, where m is any integer greater than or equal to 1 and k is an integer from 1 to m. Each input inj receives a signal representative of the drain-source voltage of a double-gate MOS transistors. Each input inj is for example connected to a drain node of a double gate MOS transistor. The signal provided by each outk output serves to regulate the potential of the backplane gate of a dual gate MOS transistor. Each output outk is for example connected to the rear face gate of a dual gate MOS transistors. The signal provided on each outk output can be determined as follows according to a law fk taking into account at least one of the input signals:

 outl = fl (inl, in2, inn),

 out2 = f2 (inl, in2, inn), outm = fm (inl, in2, inn).

Moreover, the described embodiments are not limited to the aforementioned examples of law determination methods f, based on the acquisition of a beam of curves CQ, C _] , C2, ···, etc., of the type described in relation to FIG. 6, and then on the interpolation, from this beam of curves of a regulation law f of the type illustrated in FIG. 7. More generally, other methods of determining the law can be obtained. can be provided, for example indirect determination methods, for example methods based on maximizing the gain when the transistor is mounted amplifier. By way of example, in the arrangement of FIG. 10, the objective that one seeks to achieve by applying a regulation on the back-face gate of transistor 301 is to maximize the gain in voltage of the amplifier. Without going through the steps of acquiring a beam of curves of the type represented in FIG. 6 and by extracting a regulation law f of the type represented in FIG. 7, it is possible to optimize the choice of the RI resistors. and R2 of the assembly so as to maximize its voltage gain G _v = v ₀ / v-j_. In case the RI resistors and R2 are programmable resistors, their values can be readjusted during subsequent calibration phases, to take account of any drifts and / or changes in the conditions of use of the assembly.

Claims

An electronic circuit (300) comprising:  at least one first multi-gate MOS transistor (301) having a first gate (g) and a second gate (bg) separate from the first gate; and a control unit (303) adapted to measure a magnitude representative of the drain-source voltage (V _s ) of the first transistor and to apply to the second gate (bg) of the first transistor (301) a bias potential (g ) function of said quantity,  in which the variations of the polarization potential (V ^"bg) applied by the regulating unit (303) based on variations in the drain-source voltage (^ _s) of the first transistor (301) follow a law (f) selected so that, in a voltage range drain-source (^ _s ) in which the first transistor (301) operates in saturation mode, the output conductance of the first transistor (301) is lower than when a constant bias potential (V ^ g) is applied to the second gate of the first transistor (301). 2. Circuit (300) according to claim 1, wherein the variations in the bias potential (V ^ g) applied by the regulating unit (303) based on variations in the drain-source voltage (^ _s) of the first transistor (301) follow a law (f) selected so that, within said range of drain-source voltages (^ _s) wherein the first transistor (301) operates in saturation mode, the output conductance of the first transistor (301) is substantially independent of its drain-source voltage (V ^ _s ). 3. Circuit 300 according to claim 1 or 2, wherein the variations in the bias potential (^ g) applied by the regulating unit (303) based on variations in the drain-source voltage (^ _s) of the first transistor (301) follow a law (f) chosen so that, for a given voltage (Vg _S ) applied between the first gate (g) and the source of the first transistor (301), the drain-source current (Id _s ) ^ u first transistor (301) is substantially constant in said drain-source voltage range (V _s ) in which the first transistor (301) operates in saturation mode.  The circuit (300) according to any one of claims 1 to 3, wherein the first transistor (301) comprises a channel forming region (c), a source region (s) and a drain region (d). ) laterally bordering the channel forming region (c), the first gate (g) being disposed above the channel forming region (c) and being isolated from the channel forming region (c) by a layer insulator (409), and the second gate (bg) being disposed under the channel forming region (c).  The circuit (300) of claim 4, wherein the second gate (bg) is isolated from the channel forming region (c) by an insulating layer (403).  6. Circuit (300) according to any one of claims 1 to 5, wherein the first transistor (301) is a FDSOI type transistor.  7. Circuit (300) according to any one of claims 1 to 6, wherein the control unit (303) comprises a second MOS transistor (901) whose gate (g) is connected to the drain (d) of the first transistor (301), whose drain (d) is connected to a node (VDD) for applying a first supply potential by a first resistor (RI), and whose source (s) is connected to a node (GND) application of a second supply potential distinct from the first supply potential by a second resistor (R2).  The circuit (300) according to any one of claims 1 to 6, wherein the control unit (303) comprises digital circuits. A circuit (300) according to any one of claims 1 to 8, comprising a plurality of first multi-gate MOS transistors (301; 903; 301 ') each having a first gate (g) and a second gate (bg) separate from the first grid, in which the control unit (303) is adapted to measure, for each first transistor, a magnitude representative of the drain-source voltage of the transistor, and to apply to the second gate (bg) of each first transistor a bias potential according to one or more of said magnitudes. 10. Circuit (300) according to any one of claims 1 to 9, wherein the control unit (303) comprises a calibration module adapted to determine the law (f) of the variations to be applied to the bias potential (V g) as a function of the variations of the drain-source voltage (V _s ) of the first transistor (301) so that, in saturation mode, the output conductance of the first transistor (301) is lower than when constant bias potential (V ^ g) is applied to the second gate of the first transistor (301). 11. Circuit (300) according to any one of claims 1 to 10, wherein the control unit (303) comprises a calibration module adapted to determine the law (f) variations to be applied to the bias potential (V g) as a function of the variations of the drain-source voltage (V _s ) of the first transistor (301) so that, in saturation mode, the output conductance of the first transistor (301) is substantially independent of its drain voltage -source (V ^ _s ).  12. Circuit (300) according to claim 10 or 11, wherein the control unit (303) is reconfigurable, the calibration module being adapted to configure the control unit. (303) to apply the determined law (f). The circuit (300) according to any one of claims 1 to 6, wherein the regulating unit (303) comprises a third multi-gate MOS transistor (921) having a first gate (g) and a second gate ( bg) distinct from the first gate, the first (301) and third (921) transistors being mounted in current mirror, and the second gate (bg) of the first transistor (301) being connected to the drain (d) of the third transistor ( 921). 14. Circuit (300) according to claim 13, wherein the second gate (bg) of the third transistor (921) is connected to the drain (d) of the first transistor (301).  15. Circuit for amplifying an analog signal comprising at least one circuit (300) according to any one of claims 1 to 12.  16. Circuit for copying a current comprising at least one circuit (300) according to any one of claims 1 to 12.  17. Circuit for amplifying or copying a differential signal comprising at least one circuit (300) according to any one of claims 1 to 12.