FR2737325A1 - Digital image scale uniform alteration circuit for image scaling system - has vertical and horizontal scaling controllers, with the vertical controller using sweep line storage and buffers which can have horizontal points added - Google Patents

Abstract

The circuit has a line memory (3) connected to the image memory (2) to store the (n+1)th sweep line taken from the memory. A line buffer (4) connected to the line memory stores the nth sweep line. A linear interpolator (5) is connected to the line memory and to the line buffer. A change of vertical scale controller (6) is connected to the image memory, to the line buffer and to the linear interpolator, and controls storage of image lines and operation of the linear interpolator. A change of horizontal scale controller connects to a point buffer to insert points in the line buffer under appropriate conditions.

Description

DEVICE FOR CHANGING THE SCALE OF A DIGITAL IMAGE OF
UNIFORM WAY
The invention relates to an image processing device and more particularly to a device capable of changing the scale of a digital image uniformly in real time in two dimensions.

 The ability to combine digital images is essential in multimedia computer applications.

Usually, a digital image is preprocessed before it can be combined with another digital image.

The preprocessing is usually accomplished by increasing the size of the digital image (which will be referred to hereinafter by enlargement), or by reducing the size of the digital image (which will be designated hereinafter by reduction ), by cutting out a selected part of the digital image and shifting it to another location, etc.

 The enlargement and reduction of digital images are usually accomplished using a computer programmed for this purpose. The enlargement is carried out by linear interpolation on each pair of scanning lines of the digital image to obtain at least one interpolated scanning line which is inserted between the two lines and by performing a linear interpolation on each pair of pixel data in each scan line, so as to obtain at least one interpolated pixel data item which is inserted between the pixels of the pair. Reduction is accomplished by deleting some of the scan lines from a digital image and deleting some of the pixel data from each of the selected scan lines.

 When enlarging digital images, linear interpolation of the original image data by the computer is relatively slow. For this reason, we have created various dedicated materials to allow real-time enlargement of digital images.

 Unfortunately, most dedicated hardware devices are only able to magnify digital images to a limited extent. When enlarging a digital image having (N) scan lines, the total number of scan lines to be interpolated must be a multiple of (Nl) so as to allow the insertion of an equal number of interpolated scan lines into each pair of original scan lines of the original digital image, so as to ensure uniformity. The same is true when enlarging a scan line having (N ') pixel data.

 Currently, two-dimensional scaling of a digital image can be achieved by using a special graphics processor to perform variable expansion and shrinking of the image, or by using a dedicated hardware device to get the same result. Initially, the original image is stored in an image memory. The original image then undergoes a change of scale in a first dimension, and the resulting one-dimensional modified scale image is stored in the image memory. The scaled-up image then undergoes a scale change in a second dimension, and the resulting two-dimensional scaled image is stored in the image memory before being supplied to an output device, such as '' a computer screen or printer. The conventional methods of scaling up do not present an attractive cost given their relatively large memory requirement, in particular when a large magnification ratio is used. In addition, conventional scaling methods use a large number of processing steps and thus have relatively low efficiency since the one-dimensional modified scale image must be stored in the image memory before it may undergo a change of scale in the second dimension, and since the two-dimensionally modified scale image must be stored in the image memory before it can be supplied to the output device. Thus, conventional scaling methods are not suitable for use in live video applications.

 Accordingly, the object of the present invention is to provide a device which is capable of changing the scale of a digital image uniformly in real time in two dimensions.

 More particularly, the aim of the present invention is to provide a device for scaling up at an attractive cost and highly efficient, suitable for use in live video applications.

 According to the present invention, a device is capable of processing an original digital image to obtain a desired digital image on a uniformly modified scale. The device includes an image memory for storing the original digital image therein. The original digital image has a number (N) of successive original scan lines and a number (N ') of successive original pixel data per original scan line. The device further comprises a vertical scale change unit for changing the scale of the original digital image in a vertical direction to obtain a desired number (M) of successive scan lines, and a color change unit 'horizontal scale for changing the scale of the desired scan lines from the vertical scale change unit in a horizontal direction to obtain a number (M') of successive pixel data desired per scan line.

 In order to allow the vertical scale change unit to change the scale of the original digital image when the number (M) is greater than the number (N), the vertical scale change unit includes : a line memory connected to the image memory for storing therein the (n + 1) iÔ original scan line coming from the image memory; a line buffer connected to the line memory for storing the (n) i "original scan line therein; a first linear interpolator connected to the line memory and the line buffer; and a scale change controller vertical connected to the image memory, the line buffer and the first linear interpolator. The vertical scale change controller controls the storage of the original scan lines in the line memory and the line buffer, and controls furthermore the first linear interpolator so as to perform a linear interpolation between the (n) '6 "' and the (n + 1) th original scan lines from the line memory and the line buffer so as to produce a residual interpolated scan line which is inserted between the interpolation data when the division of (MN) by (Nl) leaves a remainder (S) and when (n) is a minimum number which fulfills the condition (n + l ) * (S) 2 (s) * (N), where (s) varies from 1 to (S).

 In order to allow the vertical scale change unit to change the scale of the original digital image when the number (M) is less than the number (N), the vertical scale change controller includes a first address generator, connected to the image memory, for controlling the image memory so as to output a first original scan line for storage in the line memory; first means for generating a number (U), which is the remainder of the division of (N) by (M); a first data register of the first adding means, connected to the first generation means and to the first data register, provided for adding (U) and the number stored in the first data register so as to obtain a sum and first means of calculation, connected to the first adding means, to the first address generator and to the first data register, intended to compare the sum with the number (M) and to activate the first address generator so as to control the line memory of so that it provides at output another original scan line for storage in the line memory, this other original scan line being offset with respect to the immediately preceding original scan line which appeared at the output of the image memory of a number (V) equal to the quotient of the division of (N) by (M) when the sum is less than (M), and of a number (V + 1) when the sum is a u less equal to the number (M). The first calculation means memorize the difference between the number (M) and the sum in the first data register when the sum is at least equal to (M), and memorize the sum in the first data register when the sum is less to (M).

 In order to allow the horizontal scaling unit to scale the desired scan lines from the vertical scaling unit when the number (M ') is greater than the number (N'), the horizontal scaling unit comprises a point register connected to the first linear interpolator to store therein the (n '+ l) i "pixel data of one of the scanning lines originating from the first linear interpolator; a buffer of point connected to the point register to store therein the (n ') t pixel data of said scanning line; a second linear interpolator connected to the point register and the point buffer; and a horizontal scale change controller connected to the line memory, the line buffer, the point buffer and the second linear interpolator. The horizontal scaling controller controls the storage of pixel data in the point register and the point buffer t, and further controls the second linear interpolator so as to perform a linear interpolation between the (n ') iH and the (n' + l) i- pixel data from the point register and the point buffer so as to produce residual interpolated pixel data which is inserted between the interpolation data when the division of (M'-N ') by (N'-l) leaves a remainder (S') and when (n ') is a number minimum which fulfills the condition (n '+ l) * (S') 2 (s ') * (N'), where (s ') varies from 1 to (S').

 In order to allow the horizontal scaling unit to scale the desired scan lines from the vertical scaling unit when the number (M ') is less than the number (N'), the horizontal scale change controller comprises: a second address generator, connected to the line memory, for controlling the line memory so as to output a first original pixel data of one of the lines of original scan; second means for generating a number (U '), which is the remainder of the division of (N') by (M '); a second data register; second adding means, connected to the second generation means and to the second data register, provided for adding (U ') and the number stored in the second data register so as to obtain a sum; and second calculating means, connected to the second adding means, to the second address generator and to the second data register, intended to compare the sum with the number (M ′) and to activate the second address generator so as to controlling the line memory so that it outputs another original pixel data from said original scanning line, this other original pixel data from said original scanning line being offset with respect to to the immediately preceding original pixel data appearing at the output of the line memory of a number (V ') equal to the quotient of the division of (N') by (M ') when the sum is less than (M '), and a number (V' + 1) when the sum is at least equal to the number (M '). The second calculation means stores the difference between the number (M ') and the sum in the second data register when the sum is at least equal to (M'), and stores the sum in the second data register when the sum is less than (M ').

 The output of the second linear interpolator from the horizontal scaling unit can be supplied directly to an output device.

Other characteristics and advantages of the invention will appear better on reading the following description of an advantageous embodiment. The description refers to the accompanying drawings, in which
Figure 1 is a block diagram of an advantageous embodiment of a scale change device according to the invention;
Figure 2 is a block diagram of a bilinear adder usable in the advantageous embodiment
Figure 3 is a block diagram of a vertical scale controller in the advantageous embodiment
FIG. 4 is a block diagram of a residue distributor of the vertical scale change controller
Figure 5 is a block diagram of an alpha series generator of the vertical scale change controller
FIG. 6 is a block diagram of an address generator of the vertical scale change controller
FIG. 7 is a timing diagram showing the vertical enlargement operation of a vertical scale change unit in the advantageous embodiment, when N = 5 and AN = 2;
FIG. 8 is a timing diagram showing the vertical enlargement operation of the vertical scale change unit when N = 5 and AN = 6;
FIG. 9 is a timing diagram showing the vertical reduction operation of the vertical scale change unit when N = 5 and AN = 2;
FIG. 10 is a timing diagram showing the horizontal enlargement operation of a horizontal scale change unit in the advantageous embodiment when N '= 5 and AN' = 2; and
FIG. 11 is a chronogram showing the operation of horizontal reduction of a unit of change of horizontal scale when N '= 5 and AN' = 2.

 The advantageous embodiment shown in FIG. 1, intended for uniformly changing the scale of a digital image in accordance with the present invention comprises a vertical scale change unit and a horizontal scale change unit. The vertical scale change unit is capable of enlarging or reducing a digital image in the vertical direction and has a line memory 3, a line buffer 4, a bilinear adder 5 and a scale change controller vertical 6. The horizontal scale change unit makes it possible to enlarge or reduce a digital image in the horizontal direction and comprises a point register 7, a point buffer 8, a bilinear adder 9 and a change controller d horizontal scale 10.

 During implementation, a digital image to be processed is initially stored in an image memory 2 using the device of the advantageous embodiment.

The digital image can come from an image decoder or an image capture system. The vertical scaling controller 6 controls the image memory 2 so as to provide a selected scan line of the digital image to the line memory 3. The vertical scaling controller 6 further controls the line buffer 4 so as to store an earlier scan line from line memory 3. Bilinear adder 5 receives scan line data from line memory 3 and line buffer 4, and performs a bilinear interpolation by applying a pair of weighting coefficients a, 1-a from the vertical scale change controller 6.

 The output of the bilinear adder 5 is received by the point register 7. The horizontal scale change controller 10 controls the point buffer 8 to store therein previous pixel data coming from the point register 7. The adder bilinear 9 receives pixel data from the point register 7 and the point buffer 8, and performs bilinear interpolation by applying a pair of weighting coefficients a, 1a from the horizontal scaling controller 10.

 FIG. 2 is a block diagram of the bilinear adder 5. As shown, a scan line data item originating from the line buffer 4, which corresponds to one (n) ie scan line of the digital image in the image memory 2 is multiplied by the coefficient la, while the scan line data coming from the line memory 3, which corresponds to a (n + l) I scan line of the digital image in the image memory 2, is multiplied by the coefficient a. The resulting products are then added to provide an interpolated scan line when the coefficient a is a fraction, that is to say is neither equal to O nor to 1. The operation of the bilinear adder 5 will be described further by the after.

 The structure of the bilinear adder 9 is similar to that of the bilinear adder 5 shown in Figure 2. In the bilinear adder 9, however, the pixel data from the point buffer 8, which correspond to (n ') the pixel data of the scan line data coming from the bilinear adder 5, are multiplied by the coefficient la, while the pixel data coming from the point register 7, which correspond to (n + l) i The pixel data of the scan line data coming from the bilinear adder 5, are multiplied by the coefficient a. Thus, point register 7 is equivalent to line memory 3 of the vertical scale change unit, while point buffer 8 is equivalent to line buffer 4 of the vertical scale change unit .

 FIG. 3 shows a vertical scale change controller 6 which comprises a set of programmable registers 30 comprising a first register 30a for storing the number (N) of original scan lines of the digital image in the memory of image 2, a second register 30b for memorizing the number (AN) of scan lines to be interpolated or to be deleted and a third register 30c for memorizing an INC / DEC flag 38 intended to indicate whether an enlargement or a reduction of the digital image in a vertical direction.

The vertical scale change controller 6 also includes first, second and third calculation circuits 31, 32, 33 which read the content of the first, second and third registers 30a, 30b, 30c. The first calculation circuit 31 provides at output a quotient T of the division of (AN) by (Nl), while the second calculation circuit 32 provides a remainder S of the division of (bN) by (N-1). The quotient T corresponds to the minimum number of interpolated scanning lines to be inserted between the two lines of each pair of original scanning lines of the digital image stored in the image memory 2, while the remainder S corresponds to the number total of residual interpolated scan lines to be distributed uniformly among the original scan lines of the digital image stored in the image memory 2 when the digital image is enlarged. The third calculation circuit 33 provides at output a remainder U of the division of (N) by (N-AN). The rest
U corresponds to the total number of residual scanning lines to be deleted in the digital image stored in the image memory 2 when the digital image is reduced.

A two-input selector 34 has a first input which receives the remainder U from the third computing circuit 33 and a second input which receives the remainder S from the second computing circuit 32. The selector 34 also has a control input which receives the pennant
INC / DEC 38 from the third register 30c. The output 42 of the selector 34 drives a residue distributor 35. The residue distributor 35 also receives the quotient T coming from the first calculation circuit 31, and has a command input which receives the INC / DEC flag 38 coming from the third register 30c and a control output 39 connected to a series generator of a 36 and to an address generator 37. The residue distributor 35 determines whether a residual interpolation step is to be carried out during the enlargement of the image digital and if a residual scan line should be deleted during the reduction of the digital image. The series generator of a 36 receives the quotient T from the first calculation circuit 31 and the flag INC / DEC 38 from the third register 30c, and generates the coefficients a, la for the bilinear adder 5 and a control signal from storage for line buffer 4 (see figure 1). The address generator 37 also receives the quotient T coming from the first calculation circuit 31 and the flag
INC / DEC 38 from the third register 30c, and it supplies line address data to the image memory 2.

 FIG. 4 shows that the residue distributor 35 includes a calculating circuit 40 which provides at its output the difference between (N) and (AN), and a selector with two inputs 41 whose first input receives the output of the calculating circuit 40 and the second entry receives the number (N) from the first register 30a. I1 has a control input which receives the INC / DEC flag 38 from the third register 30c. A median data register 56 receives the output 42 of the selector 34 (see FIG. 3). Its output is connected to one of the inputs of a two-input adder 43. The other input of the adder 43 receives the output 42 of the selector 34. The output of the adder 43 and the output of the selector 41 constitute the inputs of a calculation circuit 44 which subtracts the second from the first and which supplies a validation signal on its control output 39 when the output of the adder 43 is greater than or equal to the output of the selector 41. A selector with two inputs 45 has a first input which receives the output of the adder 43, a second input which receives the difference between the outputs of the adder 43 and of the selector 41 coming from the calculation circuit 44, a control input connected to the control output 39 of the calculation circuit 44 and an output which is connected to the median data register 56.

 A clock modification circuit 46 receives the original input line clock and modifies it as a function of the signal on the control output 39 and of the quotient T coming from the first calculation circuit 31.

The original input line clock may be the display scan line clock so that the vertical scaling operation can be performed as the image data d The original is output for display on an output device, such as a printer or computer screen. When the control output 39 is in the high logic state, the clock modification circuit 46 provides on its output a clock divided by (T + 2) whose duration is (T + 2) times that of the clock original entry line. When the control output 39 is in the low logic state, the clock modification circuit 46 provides as output a clock divided by (T + 1) whose duration is (T + 1) times that of the clock of original entry line. The output of the clock modification circuit 46 and the original input line clock constitute the inputs of a selector 47. The INC / DEC flag 38 coming from the third register 30c constitutes the control input of the selector 47. The middle data register 56 has a loading pin LD which receives a clock signal mH1 coming from the selector 47.

 The series generator of a (FIG. 5) 36 includes a coefficient generator 363 connected to the control output 39 of the calculation circuit 44 and which receives the original input line clock and the quotient T coming from the first calculation circuit 31. When the control output 39 is in the high logic state, the coefficient generator 363 successively supplies coefficients a equal to 1, 1 / (T + 2), 2 / (T + 2),. . . . . . (T + 1) / (T + 2) respectively, during (T + 2) successive line clock periods; when the control output 39 is in the low logic state, the coefficient generator 363 successively supplies coefficients a equal to 1, 1 / (T + 1), 2 / (T + 1), ...... (T) / (T + 1) respectively during (T + 1) successive line clock periods. A selector 364 has a first input which is permanently at 1, a second input which receives the output of the coefficient generator 363 and a control input which receives the INC / DEC flag 38. The output of selector 364 constitutes the coefficient a and is applied to one of the inputs of a subtractor circuit 365. The other input of the subtractor circuit 365 is permanently at 1. One of the outputs of the subtractor circuit 365 is the coefficient la.

The other output of the subtractor circuit 365 is the storage control signal for the line buffer 4 (see FIG. 1). The subtractor circuit 365 generates the storage control signal when the coefficient l-a is zero, that is to say when a = 1.

 FIG. 6 shows that the address generator 37 comprises a calculation circuit 371 which supplies as output a quotient V of the division of (N) by (N-AN). The quotient V corresponds to a number of shifts between two selected scanning lines of the digital image in the image memory 2 when the digital image is to be reduced. The quotient V and the control output 39 constitute the inputs of an adder 372. The output of the adder 372 constitutes one of the inputs of a selector 373. The other input of the selector 373 is fixed at 1. The INC / DEC flag 38 is used as control input for selector 373. Selector 373 generates an offset number which is applied to an adder 374. The output of adder 374 is connected to an address register 375. The output of the address register 375 constitutes the line address data and, in turn, is received by the adder 374. The address register 375 has an "outgoing" entry intended to preposition a line address which is that of the first of the original scan lines stored in the image memory 2. The address register 375 also has a loading pin LD for controlling the storage of a new address in the register.

 A latch circuit 376 (latch network) samples and blocks the signal at control output 39, at the rate of the original input line clock.

A clock modification circuit 377 receives the original input line clock and modifies it as a function of the output of the latch circuit 376 and of the quotient T coming from the first calculation circuit 31. When the output of the circuit 376 is in the high logic state, the clock modification circuit 377 supplies as output a clock divided by (T + 2) whose duration is (T + 2) times that of the line clock of original entry. When the output of the latch circuit 376 is in the low logic state, the clock modification circuit 377 provides as output a clock divided by (T + 1) whose duration is (T + 1) times that of the original input line clock. A selector 378 receives the original input line clock and the output of the clock modification circuit 377. I1 is controlled by the INC / DEC flag 38 so as to output one of the inputs, under form of a clock input mH2 which is received by the address register 375 on the loading pin
LD.

 The structure of the horizontal scale controller 10 is substantially similar to that of the vertical scale controller 6 shown in Figures 3 to 6. There are minor differences between the two controllers 6 and 10. For example, in the horizontal scale controller 10, the first register of the set of programmable registers is used to store the number (N) of pixel data per original scan line of the digital image in the image memory 2 , and the second register is used to store the number (AN ') of pixel data to be interpolated or deleted per scan line. The third register stores an INC / DEC flag which is used to indicate whether to enlarge or reduce the digital image in a horizontal direction. The first calculation circuit generates the quotient T 'corresponding to the minimum number of interpolated pixel data to be inserted between the two data of each pair of pixel data of scanning line data coming from the bilinear adder 5. The second circuit of calculation generates the remainder S 'corresponding to the number of displays so that the horizontal scale change operation can be performed as the original image data is output for display on the device Release. The address output of the address register of the horizontal scaling controller 10 is a point address which is used to control the line memory 3 and the line buffer 4. Thus, during enlargement in one direction horizontal, all the pixel data of the (n) i ^ and the (n + l) t'e original scan lines and scan lines interpolated between them, if any, cross the adder bilinear 5. When reducing in both the vertical and horizontal directions, only selected pixel data from the selected original scan lines pass through the bilinear adder 5.

Thus, the advantageous embodiment operates so as to simultaneously perform an enlargement or reduction in the vertical direction and an enlargement or reduction in the horizontal direction. The operation of the advantageous embodiment will now be described in the following paragraphs
A. To facilitate the explanation of the vertical enlargement operation in the advantageous embodiment, an example will be given in which an original digital image having five original scanning lines and five pixel data per line of scan is enlarged to obtain a desired digital image having seven desired scan lines and five pixel data per scan line.

The Set of programmable registers 30 of the vertical scale change controller 6 (FIG. 3) is initially programmed by memorizing the number "5" in the first register 30a, the number "2" in the second register 30b and a "1" logic in the third register 30c. The number "5" corresponds to the number (N) of original scan lines of the original digital image in the image memory 2. The number "2" corresponds to the total number (bN) of scan lines to interpolate. The logic "1" in the third register 30c indicates that the original digital image must be enlarged in the vertical direction. The Programmable Register Set of the Horizontal Scale Change Controller 10 is then programmed to indicate that there are five pixel data in each of the original scan lines, that there is no data to interpolate. pixels for each original scan line, and that the original digital image must be enlarged in a horizontal direction. 1
The first calculation circuit 31 supplies the quotient T of the division of (AN) by (Nl) as an output. Since (AN) is less than (N-1), the quotient T is 0. The second calculation circuit 32 provides as an output the remainder S of the division of (AN) by (N-1). In the example, the remainder S is equal to 2. The output of the third calculation circuit 33 is unused, since the selector 34 supplies the output of the second calculation circuit 32 to the residue distributor 35 during the enlargement operation. . The outputs of the first, second and third calculation circuits of the horizontal scale change controller 10 are equal to 0 since there is no need to perform a horizontal enlargement or reduction operation.

 The address register 375 of the address generator 37 (FIG. 1 and FIGS. 3 to 7) initially fixes the line address of a first original scan line stored in the image memory 2 and controls the memory. frame 2 so as to provide the first original scan line to the line memory 3 during a start line clock signal. At the same instant, the remainder S is stored in the middle data register 56, and the adder 43 then adds the rest S to the content of the middle data register 56. Since the output of the adder 43, which is equal to 4 at this instant, is less than (N), which is equal to 5, the control output 39 of the calculation circuit 44 is in the low logic state. The selector 45 provides the output of the adder 43 to the middle data register 56, and the clock input mHl supplied to the middle data register 56 is the clock divided by (T + 1), which is exactly the same than the original input line clock since the quotient T is equal to 0.

 Since the control output 39 is in the low logic state and the quotient T is equal to o, the coefficient generator 363 supplies the number "1" to the selector 364. Since the INC / DEC flag 38 is a logical "1", the selector 364 chooses the output of the coefficient generator 363 as the weighting coefficient a. Since the coefficient a is equal to 1, the coefficient la is equal to 0, and the storage command signal is generated so as to control the line buffer 4 in order to memorize the first of the original scanning lines, originating from the line memory 3. The output of the bilinear adder 5 is then the first of the original scan lines.

 The selector 373 provides an offset number equal to 1 to the adder 374. The adder 374 then increments the output of the address register 375 by one unit when the next clock pulse mH2 arrives and thus controls the memory 2 to provide the second original scan line to line 3 memory.

 When the next clock pulse mH1 arrives, the middle data register 56 stores the previous output of the adder 43, which is the number "4". At this time, the output of the adder 43, now equal to 6, is greater than (N), which is equal to 5, so that the control output 39 of the calculation circuit 44 is in the state high logic. Selector 45 provides the difference between the outputs of adder 43 and selector 41 to the middle data register 56, and the clock input mHî of the middle data register 56 is now the clock divided by (T + 2 ), the duration of which is twice the duration of the original input line clock.

 Now that the control output 39 is in the high logic state, the coefficient generator 363 successively supplies two outputs, 1 and, during a clock pulse mH1, that is to say two periods of consecutive original input line clock. During the first original input line clock period, the bilinear adder 5 provides the second original scan line; at the same time, the latter is stored in line buffer 4 since the coefficient a is equal to 1. During the second original input line clock period, the content of address register 375 is incremented by one on receipt of the next pulse mH2 so as to control the image memory 2 and to supply a third original scan line to the line memory 3. At this time, the output of the generator coefficients 363 is equal to 4, the coefficient a is equal to 4, the coefficient 1-a is equal to 4, and no storage command signal is generated. Thus, the original second scan line remains in line buffer 4.

The output of the bilinear adder 5 is then the bilinear interpolation between the second and third original scan lines.

 The content of the median data register 56 is updated and goes to 1, which is the difference between the output of the adder 43 and (N), when the next clock pulse mH1 arrives. The output of the adder 43 is equal to 3, which is less than (N), so that the control output 39 is in the low logic state. The selector 45 provides the output of the adder 43 to the middle data register 56. The clock input mH1 supplied to the middle data register 56 is the clock divided by (T + 1) and the coefficient a from the generator of series of a 36 is equal to 1. The output of the bilinear adder 5 is constituted by the third original scan line and, since the coefficient a is equal to 1, the third original scan line is stored in line buffer 4.

 The subsequent operation of the vertical scale change unit is similar to the above until the fifth original scan line appears at the output of the bilinear adder 5.

 FIG. 7 is a timing diagram which shows the enlargement operation according to the advantageous embodiment in this example, that is to say for N = 5 and AN = 2.

 It has thus been shown that the vertical scale change controller 6 controls the bilinear adder 5 so as to perform a bilinear interpolation between the (n) t '"original scan line, which is stored in the line buffer 4, and the (n + 1) i * - 'original scan line, which is stored in the line memory 3, so as to produce a residual interpolated scan line which is inserted between the (n) th and the (n + l) iêae original scan lines, when the division of (AN) by (N-1) provides a remainder (S) and when (n) is a minimum number which fulfills the condition (n + l ) * (S) 2 (s) * (N), where (s) varies between 1 and (S).

 Referring again to FIG. 1, since there is no need to perform a horizontal scaling operation, the horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to supply the pixel data stored therein sequentially to the bilinear adder 5.

The original and interpolated pixel data from the bilinear adder 5 are received by the point register 7 which, in turn, supplies these to the bilinear adder 9. At this time, the coefficient a is always equal to 1 and the output of the point buffer 8 is not taken into account by the bilinear adder 9. The output of the bilinear adder 9 is equal to that of the bilinear adder 5 and can be supplied directly to the output device (not shown).

 In this example, the quotient (T) of the division of (AN) by (Nl) is 0. If the quotient T is different from zero, that is to say if (AN) is greater than or equal to (Nl ), the vertical scale controller 6 controls the bilinear adder 5 to perform a bilinear interpolation between the (n) 'C and the (n + 1) io original scan lines, in order to provide an additional number T of successive interpolated scan lines which are inserted between the (n) iêu and the (n + 1) iêlo original scan lines.

FIG. 8 shows, by way of example, a timing diagram of a vertical enlargement operation carried out using the advantageous embodiment, when N = 5 and AN = 6. In this example, the quotient T is equal to 1 and the remainder S is equal to 2. Naturally, an additional interpolated scanning line is inserted in each interval between the (n) line and the (n + l) i * 'lines original scan.

 B. In the following example, an original digital image having five original scan lines and five pixel data per scan line is reduced to obtain a desired digital image having three desired scan lines and five data pixels per scan line.

 Referring again to FIG. 3, the Set of programmable registers 30 is initially programmed by memorizing the number "5" in the first register 30a, the number "2" in the second register 30b and a logic "0" in the third register 30c. The number "5" corresponds to the number (N) of original scan lines of the original digital image in the image memory 2. The number "2" corresponds to the total number (AN) of scan lines to delete. The logic "0" in the third register 30c indicates that a reduction of the original digital image must be carried out. The Programmable Register Set of the Horizontal Scale Change Controller 10 is then programmed to indicate that there are five pixel data in each of the original scan lines, which need not be interpolated. pixel data for each original scan line, and that the original digital image must be enlarged in a horizontal direction.

 The outputs of the first and second calculation circuits 31, 32 are unused during the reduction operation. The third calculation circuit 33 provides on its output the remainder U of the division of (N) by (N-AN), (N-AN) being the number of original scan lines to be kept.

In the example, the remainder U is equal to 2. The selector 34 supplies the output of the third calculation circuit 33 to the residue distributor 35.

 FIG. 1, FIGS. 3 to 6 and FIG. 9 show that the address register 375 of the address generator 37 initially supplies the line address of the first original scan line stored in the image memory 2 and controls the image memory 2 so as to supply the first original scan line to the line memory 3 during a start line clock signal. Simultaneously, the remainder U is stored in the middle data register 56 and the adder 43 then adds the rest U to the content of the middle data register 56. The calculation circuit 44 subtracts the number (N-AN) coming from the selector 41 of the output of the adder 43.

Since the output of the adder 43, which is then equal to 4, is greater than the number (N-AN), which is equal to 3, the control output 39 of the calculation circuit 44 is in the logic state high. The selector 45 applies the difference between the outputs of the adder 43 and of the selector 41 to the median data register 56. The original line clock signal is supplied to the median data register 56 via the selector 47 .

 As seen in FIGS. 3 and 5, since a logic "0" is stored in the third register 30c, the selector 364 maintains the coefficient a at 1. The coefficient la is therefore equal to 0 and the control signal of storage is ALWAYS generated to activate line buffer 4 which will continuously store an original scan line from line memory 3. In addition, the output of bilinear adder 5 is always the output of line memory 3.

 The calculation circuit 371 (FIG. 6) provides on its output the quotient V of the division of (N) by (N-AN). In the example, the quotient V is equal to 1. The adder 372 generates the sum of the quotient V and the logic state of the control output 39, which is then in the high logic state.

The selector 373 chooses the output of the adder 372, which is equal to 2, and transmits it to the adder 374. The output of the address register 375 is therefore incremented by two units when the next pulse mH2 arrives, this which controls the image memory 2 so that the third original scan line is supplied to the line memory 3.

 Referring again to FIG. 4, it can be seen that on arrival of the next line clock pulse, the median data register 56 stores the number "1", which is the previous difference calculated by the calculation circuit 44. At this time, the output of the adder 43, which is equal to 3, is equal to the output of the selector 41. The control output 39 of the calculation circuit 44 is in the logic state top, and the selector 45 provides the difference between the outputs of the adder 43 and of the selector 41 to the median data register 56.

 Returning to FIG. 6, it can be seen that the adder 372 once again generates the sum of the quotient V and of the current logic state of the control output 39. The output of the adder 372, which is equal to 2, is transmitted to the adder 374 via the selector 373. Therefore the output of the address register 375 is again incremented by two when the next mH2 pulse arrives, thus controlling the image memory 2 of so that the original fifth scan line is supplied to the line memory 3. Figure 9 is a timing diagram which shows the vertical reduction operation in the advantageous embodiment for this example, i.e. for N = 5 and AN = 2. The operation of the horizontal scale change unit for this example is similar to that described above and will not be described again.

 The above shows that the address generator 37 of the vertical scale change controller 6 controls the image memory 2 so as to output only selected original scanning lines. The original scan lines which do not appear at the output of the image memory 2 are indeed rejected. It will be noted that the original scanning line appearing at the output of the image memory 2 is offset with respect to the immediately preceding original scanning line appearing at the output of the memory 2 by the number V when the output of the adder 43 of the residue distributor 35 is less than the difference (N-AN), and offset by the number (V + 1) when the output of the adder 43 is at least equal to the difference (N-AN).

 C. In the following explanation of the horizontal enlargement operation of the advantageous embodiment, an example is given in which an original digital image having five original scan lines and five pixel data per scan line is enlarged to obtain a desired digital image having five desired scan lines and seven pixel data per scan line.

 The set of programmable registers 30 of the vertical scale change controller 6 is initially programmed to indicate that there are five original scan lines in the image memory 2, that there is no need to interpolate scan line, and you need to magnify the original digital image in a vertical direction. The set of programmable registers of the horizontal scale change controller 10 is then programmed by memorizing the number "5" in the first register, the number "2" in the second register, and a logical "1" in the third register. The number "5" corresponds to the number (N ') of pixel data in each of the original scan lines in the image memory 2.

The number "2" corresponds to the total number (AN ') of pixel data to be interpolated per scan line. The logical n 1 n in the third register indicates that an enlargement of the original digital image must be carried out in the horizontal direction.

 The outputs of the first, second and third calculation circuits 31, 32, 33 of the vertical scale change controller 6 are equal to 0 since no vertical enlargement or reduction operation is to be carried out. The first calculation circuit of the horizontal scale change controller 10 supplies the quotient T 'of the division of (AN') by (N'-1). As (AN) is less than (N'-1), the quotient T 'is equal to 0. The second calculation circuit of the horizontal scale change controller 10 outputs the remainder S' of the division of (AN ') by (N'-l). In this example, the remainder S 'is equal to 2. The output of the third calculation circuit of the horizontal scale change controller 10 has no effect since the output of the second calculation circuit is supplied to the residue distributor during l 'horizontal enlargement operation.

 Since no vertical scaling operation is to be performed, the vertical scaling controller 6 controls the image memory 2 to supply the original scan lines to the line memory 3 sequentially. The horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to supply the pixel data stored therein sequentially to the bilinear adder 5. At this time, the coefficient a from the vertical scale controller 6 is ALWAYS equal to 1, and the output of line buffer 4 is not taken into account by the bilinear adder 5. The output of the bilinear adder 5 is equal to that of the line memory 3.

 As mentioned previously, the enlargement operation of the horizontal scale change unit is substantially similar to that of the vertical scale change unit. However, unlike the vertical scale change controller 6, the horizontal scale change controller 10 controls the bilinear adder 9 to perform bilinear interpolation between the (n ') i *' original pixel data , which is stored in point buffer 8, and the (n '+ l) i * original pixel data, which is stored in point register 7, so as to produce residual interpolated pixel data which is inserted between the (n1) iêae and the (n '+ l)' a "original pixel data when the division of (AN ') by (N'-l) leaves a remainder (S'), and when ( n ') is a minimum number which fulfills the condition (n' + l) * (S ') 2 (s') * (N'), where (s') varies between 1 and (S '). (N '), (AN') and (S ') are respectively 5, 2 and 2, you must insert the residual interpolated pixel data between the second and third original pixel data and between the fourth and fifth original pixel data e of a scan line.

 The horizontal scaling controller 10 initially sets the point address of a first pixel data of the scan line data stored in the line memory 3 and controls the line memory 3 to provide the first line data. pixel to the bilinear adder 5 so that it is received by the point register 7 during a starting pixel clock signal. The coefficient a coming from the horizontal scale change controller 10 is equal to 1, and the locking command signal is generated so as to control the point buffer 8 in order to store therein the first original pixel data originating from of the point register 7. The output of the bilinear adder 9 at this time is the first original pixel data and can be supplied directly to the output device (not shown).

 At this time, the horizontal scale change controller 10 controls the line memory 3 to supply a second original pixel data to the bilinear adder 5 so that it is received by the point register 7 The horizontal scale change controller 10 successively generates two coefficients a, 1 and 4, during two original pixel clock periods. During the first original pixel clock period, the bilinear adder 9 outputs the second original pixel data and, simultaneously, the latter is stored in the point buffer 8 since the coefficient a is equal to 1. During the second original pixel clock period, the line memory 3 supplies a third original pixel data to the bilinear adder 5 so that it is received by the register of point 7. The coefficient a is now equal to 4, and the second original pixel data remains in the buffer of point 8. The output of the bilinear adder 9 at this time is the bilinear interpolation of the second and third original pixel data.

 During the next original pixel clock period, the coefficient a from the horizontal scale controller 10 returns to 1, and the output of the bilinear adder 9 is the third original pixel data which is simultaneously stored in the point buffer 8.

 The subsequent operation of the horizontal scaling unit is similar to the above until the fifth original pixel data of a scanning line has been output by the bilinear adder 9.

 FIG. 10 is a timing diagram which shows the horizontal enlargement operation in the advantageous embodiment for this example, that is to say for N '= 5 and AN' = 2.

 In this example, the quotient (T ') of the division of (AN') by (N'-1) is 0. If the quotient T 'is different from zero, that is to say if (AN') is greater than or equal to (N'-l), the horizontal scale change controller 10 controls the bilinear adder 9 to perform a bilinear interpolation between the (n ') im' and the (n '+ l) i " original pixel data of a scan line, in order to provide an additional number T 'of successive interpolated pixel data which are inserted between the (n') i1e and the (n '+ l)' L "data of original pixel.

 D. In the following example, an original digital image having five original scan lines and five pixel data per scan line is reduced to obtain a desired digital image having five desired scan lines and three data pixels per scan line.

 The Programmable Register Set 30 of the vertical scale change controller 6 is initially programmed to indicate that there are five original scan lines in the image memory 2, that there is no interpolation scan line, and you need to magnify the original digital image in a vertical direction. The set of programmable registers of the horizontal scale change controller 10 is then programmed by memorizing the number "5" in the first register, the number "2" in the second register, and a logical "0" in the third register. The number "5" corresponds to the number (N ') of pixel data per original scan line of the digital image in the image memory 2. The number "2" corresponds to the total number (AN') of pixel data to be deleted per scan line. The logic 0 "in the third register indicates that the original digital image must be reduced in the horizontal direction.

 The outputs of the first, second and third calculation circuits 31, 32, 33 of the vertical scale change controller 6 are equal to 0 since there is no need to perform a vertical enlargement or reduction operation. Thus, the vertical scaling controller 6 controls the image memory 2 to supply the original scan lines to the line memory 3 sequentially. The horizontal scale change controller 10 controls the line memory 3 and the line buffer 4 to supply data selected from the pixel data stored therein to the bilinear adder 5. For this example, the coefficient a from of the vertical scale change controller 6 is always equal to 1, and the output of the line buffer 4 is not taken into account by the bilinear adder 5.

The output of the bilinear adder 5 is equal to the output of the line memory 3.

 The reduction operation of the horizontal scale change unit is substantially similar to that of the vertical scale change unit. However, in the horizontal scaling unit, the horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to output only data selected from the pixel data of origin. The original pixel data to appear at the output of the line memory 3 and of the line buffer 4 is offset with respect to the immediately preceding original pixel data which appeared at the output of the latter by the number V ', which is the quotient of the division of (N ') by (N'-AN'), when the output of an adder of the residue distributor of the horizontal scale change controller 10 is less than the difference (N'-AN ' ), and the number (V '+ 1) in all other cases.

The outputs of the first and second calculation circuits of the horizontal scale change controller 10 are unused during the horizontal reduction operation. The third calculation circuit outputs the remainder U 'of the division of (N') by (N'-AN '), (N'
AN ') being the number of original pixel data to be retained per scan line. In this example, the rest
U 'is equal to 2 and is supplied to the residue distributor of the horizontal scale change controller 10.

 The horizontal scale change controller 10 initially sets the point address of a first pixel data of a scan line data stored in the line memory 3, and controls the line memory 3 to provide the first pixel data to the bilinear adder 5 during a starting pixel clock period.

 As a logical "0" is stored in the third register of the horizontal scale change controller 10, the coefficient a from the horizontal scale change controller 10 is kept at 1. Thus, the point buffer 8 is activated to continuously store therein pixel data originating from the point register 7, and the output of the bilinear adder 9 is always the output of the point register 7.

 At this time, the output of the adder of the residual distributor of the horizontal scale change controller 10 is greater than the difference (N'-AN '), which produces an offset number (V' + 1 ) or 2. The horizontal scale controller 10 controls the line memory 3 and the line buffer 4 to supply the third pixel data of the scan line data stored therein to the bilinear adder 5 so that it be received by the point register 7.

 On arrival of the next pixel clock pulse, the output of the adder of the residual distributor of the horizontal scale change controller 10 is equal to the difference (N'-AN '), thus producing a offset number (V '+ 1) or 2. The horizontal scale controller 10 controls the line memory 3 and the line buffer 4 to provide the fifth pixel data of the scan line data stored therein to the bilinear adder 5 so that it is received by the point register 7.

FIG. 11 is a timing diagram which illustrates the horizontal reduction operation in the advantageous embodiment for this example, that is to say for N '= 5 and
AN '= 2.

 The device of the present invention is a dedicated hardware device which makes it possible to change the scale of digital images in real time in two dimensions.

In addition, the device of the present invention is relatively inexpensive compared to its relatively low memory requirement, independently of the magnification ratio, and uses fewer processing steps, which provides higher efficiency, since the output of the vertical scaling unit is supplied directly to the horizontal scaling unit without the need to store it in an intermediate image buffer, and since the output of the horizontal scaling unit can be supplied directly to an output device without the need to store this output in an output image buffer. The present invention is therefore ideal for use in live video applications.

Claims (16)

 1. Device for processing an original digital image to obtain a desired digital image on a uniformly modified scale, the device comprising an image memory (2) for storing therein the original digital image, the original digital image having a number (N) of successive original scan lines and a number (N ') of successive original pixel data per original scan line, the device further comprising a vertical scale change to change the scale of the original digital image in a vertical direction to obtain a number (M) of successive desired scan lines, and a horizontal scale change unit to change the scale of desired scan lines from the vertical scale change unit in a horizontal direction to obtain a number (M ') of successive desired pixel data per scan line, the number (M) being greater r to the number (N), the number (M ') being greater than the number (N'), characterized in that  the vertical scale change unit comprises: a line memory (3) connected to the image memory (2) for storing therein the (n + l) t ^ original scan line coming from the memory d 'image (2); a line buffer (4) connected to the line memory (3) for storing therein the (n) th original scan line; a first linear interpolator (5) connected to the line memory (3) and to the line buffer (4); and a vertical scale controller (6) connected to the image memory (2), the line buffer (4) and the first linear interpolator (5), the vertical scale controller (6) controlling the storage of the original scan lines in the line memory (3) and the line buffer (4), the vertical scale change controller (6) further controlling the first linear interpolator (5) performing a linear interpolation between the (n) '"and the (n + l) l-' original scan lines from the line memory (3) and the line buffer (4) so as to produce a residual interpolated scan line which is inserted between the original lines when the division of (MN) by (Nl) leaves a remainder (S) and when (n) is a minimum number which fulfills the condition (n + l) * (S) 2 (s) * (N), where (s) varies from 1 to (S); and in that  the horizontal scale change unit comprises: a point register (7) connected to the first linear interpolator (5) for storing therein the (n '+ l)' a "pixel data of one of the scanning lines coming from the first linear interpolator (5); a point buffer (8) connected to the point register (7) for storing therein the (n ') i pixel data of said scanning line; a second linear interpolator (9) connected to the point register (7) and the point buffer (8); and a horizontal scale change controller (10) connected to the line memory (3), the line buffer (4), the point buffer ( 8) and at the second linear interpolator (9), the horizontal scale change controller (10) controlling the storage of the pixel data in the point register (7) and the point buffer (8), the change controller horizontal scale (10) further controlling the second linear interpolator (9) so as to perform an interpolation li between the (n ') t- and the (n' + l) i "pixel data from the point register (7) and the point buffer (8) so as to produce residual interpolated pixel data which is inserted between said (n ') iêae and (n' + l) I 'pixel data when the division of (M'-N') by (N'-1) leaves a remainder (S ') and when (n' ) is a minimum number which fulfills the condition (n '+ l) * (S') 2 (s ') * (N'), where (s ') varies from 1 to (S')  whereby the output of the second linear interpolator (9) can be supplied directly to an output device.  2. Device according to claim 1, characterized in that the vertical scale change controller (6) also controls the first linear interpolator (5) to perform a linear interpolation between the (n) 'and the (n + l ) t ^ - original scan lines to obtain an additional number (T) of successive interpolated scan lines which are inserted between the original lines when (MN) is greater than (N-1), the number (T ) being equal to a quotient resulting from the division of (MN) by (N 1).  3. Dispostive according to claim 2, characterized in that the first linear interpolator (5) is a bilinear adder.  4. Device according to claim 1, characterized in that the horizontal scale change controller (10) further controls the second linear interpolator (9) so as to perform a linear interpolation between the (n ') t ^' and the (n '+ l) ie pixel data of said scan line coming from the first linear interpolator (5) in order to produce an additional number (T') of successive interpolated pixel data which are inserted between said (n ') ie and (n + l) same pixel data when (M ' N ') is greater than (N'-1), the number (T') being equal to a quotient resulting from the division of (M'-N ') by (N'-1).  5. Device according to claim 4, characterized in that the second linear interpolator (9) is a bilinear adder.  6. Device for processing an original digital image to obtain a desired digital image on a uniformly modified scale, the device comprising an image memory (2) for storing therein the original digital image, the original digital image having a number (N) of successive original scan lines and a number (N ') of successive original pixel data per original scan line, the device further comprising a vertical scale change to change the scale of the original digital image in a vertical direction to obtain a number (M) of successive desired scan lines, and a horizontal scale change unit to change the scale of the desired scan lines from the vertical scale change unit in a horizontal direction to obtain a number (M ') of successive desired pixel data per scan line, the number (M) being greater ur to the number (N), the number (M ') being less than the number (N'), characterized in that  the vertical scale change unit comprises: a line memory (3) connected to the image memory (2) for storing therein the (n + i) iêae original scan line coming from the memory of picture (2); a line buffer (4) connected to the line memory (3) for storing therein (n) the original scan line; a linear interpolator (5) connected to the line memory (3) and to the line buffer (4); and a vertical scale change controller (6) connected to the image memory (2), the line buffer (4) and the linear interpolator (5), the vertical scale change controller (6 ) controlling the storage of the original scanning lines in the line memory (3) and the line buffer (4), the vertical scale change controller (6) also controlling the linear interpolator (5) of so as to perform a linear interpolation between the (n) iêH and the (n + l) i "original scan lines from the line memory (3) and the line buffer (4) so as to produce a line of interpolated residual scanning which is inserted between the original lines when the division of (MN) by (N-1) leaves a remainder (S) and when (n) is a minimum number which fulfills the condition (n + l) * (S) 2 (s) * (N), where (s) varies between 1 and (S); and in that  the horizontal scale change unit includes a horizontal scale change controller (10), the horizontal scale change controller (10) comprising  an address generator (37), connected to the line memory (3) and to the line buffer (4), for controlling the line memory (3) and the line buffer (4) in order to provide an output first original pixel data from one of the scan lines  means for generating (33) a number (U '), which is the remainder of the division of (N') by (M ')  a data register (56)  adding means (43), connected to the generating means (33) and to the data register (56), provided for adding (U ') and the number stored in the data register (56) so as to obtain a sum; and  calculation means (44), connected to the adding means (43), the address generator (37) and the data register (56), intended to compare the sum and the number (M ') and to activate the generator address (37) for controlling the line memory (3) and the line buffer (4) so as to output another original pixel data from said scanning line, said other pixel data from origin of said scanning line being offset from the immediately preceding original pixel data which appeared at the output of the line memory (3) and of the line buffer (4) by a number (V ′) equal to the quotient by dividing (N ') by (M') when the sum is less than (M '), and by a number (V' + 1) when the sum is at least equal to (M ')  the calculating means (44) storing the difference between the number (M ') and the sum in the data register (56) if the sum is at least equal to (M'), and storing the sum in the data register (56) if the sum is less than (M ')  whereby the output of the horizontal scaling unit can be supplied directly to an output device.  7. Device according to claim 6, characterized in that the vertical scale change controller (6) also controls the linear interpolator (5) so as to perform a linear interpolation between the (n) t and the (n + l) i * "original scan lines so as to produce an additional number (T) of successive interpolated scan lines inserted between the original lines when (M N) is greater than (N-1), the number (T) being equal to the quotient of the division of (M-N) by (N-1).  8. Device according to claim 7, characterized in that the linear interpolator (5) is a bilinear adder.  9. Device for processing an original digital image to obtain a desired digital image on a uniformly modified scale, the device comprising an image memory (2) for storing therein the original digital image, the original digital image having a number (N) of successive original scan lines and a number (N ') of successive original pixel data per original scan line, the device further comprising a vertical scale change to change the scale of the original digital image in a vertical direction to obtain a number (M) of successive desired scan lines, and a horizontal scale change unit to change the scale of the desired scan lines from the vertical scale change unit in a horizontal direction to obtain a number (M ') of successive desired pixel data per scan line, the number (M) being less r to the number (N), the number (M ') being greater than the number (N'), characterized in that  the vertical scale change unit comprises a vertical scale change controller (6) and a line memory (3) connected to the image memory (2), the vertical scale change controller (6 ) including  an address generator (37), connected to the image memory (2), for controlling the image memory (2) so that it outputs a first original scan line for storage in the line memory (3);  means for generating (33) a number (U), which is the remainder of the division of (N) by (M)  a data register (56);  adding means (43), connected to the generating means (33) and to the data register (56), provided for adding (U) and the number stored in the data register (56) so as to obtain a sum; and  calculation means (44), connected to the adder means (43), the address generator (37) and the data register (56), intended to compare the sum and the number (M) and to activate the generator d address (37) so as to control the image memory (2) so that it outputs another original scan line for storage in the line memory (3), this other scan line d origin being offset from the immediately preceding original scan line appeared at the output of the image memory (2) by a number (V) equal to the quotient of the division of (N) by (M) when the sum is less than (M), and by a number (V + 1) when the sum is at least equal to the number (M)  the calculating means (44) storing the difference between the number (M) and the sum in the data register (56) when the sum is at least equal to (M), and storing the sum in the data register (56 ) when the sum is less than (M); and in that  the horizontal scaling unit comprises: a point register (7) connected to the line memory (3) for storing therein the (n '+ 1)' "pixel data of one of the scanning lines coming from line memory (3); a point buffer (8) connected to the point register (7) for storing therein the (n ') i "' pixel data of said scan line from the line memory ( 3); a linear interpolator (9) connected to the point register (7) and to the point buffer (8); and a horizontal scale change controller (10) connected to the line memory (3), the stitch buffer (8) and the linear interpolator (9), the horizontal scale change controller (10) controlling the storage of pixel data in the point register (7) and the point buffer (8), the horizontal scaling controller (10) further controlling the linear interpolator (9) so as to perform a linear interpolation between the (n ') island and the (n' + l) i- 'pixel data from the point register (7) and the point buffer (8) so as to produce a residual interpolated pixel data which is inserted between said (n ') ie and (n' + l) t 'pixel data when the division of (M'-N') by (N'-l) leaves a remainder (S ') and when (n ') is a minimum number which fulfills the condition (n' + l) * (S ') 2 (s') * (N'), where (s') varies between 1 and (S ')  whereby the output of the linear interpolator (9) can be supplied directly to an output device.  10. Device according to claim 9, characterized in that the horizontal scale change controller (10) further controls the linear interpolator (9) so as to perform a linear interpolation between the (n ') i * and the (n '+ l)' "" pixel data of said scan line from the line memory (3) to produce an additional number (T ') of successive interpolated pixel data which are inserted between said (n' ) iêH and (n + 1) ith pixel data when (M'-N ') is greater than (N'-1), the number (T') being equal to a quotient resulting from the division of (M'- N ') by (N'-1).  11. Device according to claim 10, characterized in that the linear interpolator (9) is a bilinear adder.  12. Device for processing an original digital image to obtain a desired digital image on a uniformly modified scale, the device comprising an image memory (2) for storing therein the original digital image, the original digital image having a number (N) of successive original scan lines and a number (N ') of successive original pixel data per original scan line, the device further comprising a vertical scale change to change the scale of the original digital image in a vertical direction to obtain a number (M) of successive desired scan lines, and a horizontal scale change unit to change the scale of the desired scan lines from the vertical scale change unit in a horizontal direction to obtain a number (M ') of successive desired pixel data per scan line, the number (M) being less eur to the number (N), the number (M ') being less than the number (N'), characterized in that  the vertical scale change unit comprises a vertical scale change controller (6) and a line memory (3) connected to the image memory (2), the vertical scale change controller (6 ) including  a first address generator (37), connected to the image memory (2), for controlling the image memory (2) so as to output a first original scan line for storage in the memory line (3)  first means of generation (33) of a number (U), which is the remainder of the division of (N) by (M)  a first data register (56)  first adding means (43), connected to the first generation means (33) and to the first data register (56), provided for adding (U) and the number stored in the first data register (56) so as to obtain an amount ; and  first calculation means (44), connected to the first adding means (43), to the first address generator (37) and to the first data register (56), intended to compare the sum and the number (M) and to activate the first address generator (37) to control the image memory (2) so that it outputs another original scan line for storage in the line memory (3), this other line original scan line being offset from the immediately preceding original scan line that appeared at the output of the image memory (2) by a number (V) equal to the quotient of the division of (N) by ( M) when the sum is less than (M), and by a number (V + 1) when the sum is at least equal to (M);  the first calculation means (44) memorizing the difference between the number (M) and the sum in the first data register (56) if the sum is at least equal to (M), and memorizing the sum in the first data register data (56) if the sum is less than (M); and in that  the horizontal scale change unit includes a horizontal scale change controller (10), the horizontal scale change controller (10) comprising  a second address generator (37), connected to the line memory (3), for controlling the line memory (3) so that it outputs a first original pixel data of a line of original scan  second means (33) for generating a number (U '), which is the remainder of the division of (N') by (M ')  a second data register (56)  second adding means (43), connected to the second generation means (33) and to the second data register (56), provided for adding (U ') and the number stored in the second data register (56) so as to get a sum; and  second calculation means (44), connected to the second adding means (43), to the second address generator (37) and to the second data register (56), intended to compare the sum and the number (M ') and activating the second address generator (37) so as to control the line memory (3) so that it outputs another source pixel data from said source scan line, said other data of original pixel of said original scan line being shifted with respect to the immediately preceding original pixel data appearing at the output of the line memory (3) by a number (V ′) equal to the quotient of dividing (N ') by (M') when the sum is less than (M '), and by a number (V' + 1) when the sum is at least equal to the number (M ');  the second calculation means (44) memorizing the difference between the number (M ') and the sum in the second data register (56) when the sum is at least equal to (M'), and memorizing the sum in the second data register (56) when the sum is less than (M ')  whereby the output of the horizontal scaling unit can be supplied directly to an output device.  13. Method for processing an original digital image, in order to obtain a desired digital image on a uniformly modified scale - the original digital image having (N) successive image data and the desired digital image having (M) successive desired image data, (M) being greater than (N) - characterized in that it comprises the following steps  a first linear interpolator (5) b is provided; and  the linear interpolator (5) is controlled so as to perform a linear interpolation of the (n) island and the (n + 1) i 'original image data so as to produce a residual interpolated image data which is inserted between the original data when the division of (MN) by (Nl) leaves a remainder (S) and when (n) is a minimum number which fills the conduit on (.. + 1) * (S) > (s) * (N), where (s) varies from 1 to (S).  14. A method of processing an original digital image to obtain a desired digital image on a uniformly modified scale, wherein the original digital image has (N) successive image data and the desired digital image a (M) successive image data, (M) being less than (N), characterized in that it comprises the following steps  (1-1) the original image data is stored in a memory (2)  (I-2) an address generator (37) is provided which controls the memory (2) so as to output a first original image data  (I-3) a number (U), which is the remainder of the division of (N) by (M), is stored in a data register (56)  (1-4) the number (U) is added to the number stored in the data register (56) to obtain a sum  (I-5) we compare the sum with (M)  (I-6) the address generator (37) is activated to control the memory (2) so that it outputs another original image data, offset by an image data of immediately preceding origin provided by the memory (2) of a number (V) equal to the quotient of the division of (N) by the number (M) when the sum is less than (M), and by the number (V + 1) when the sum is at least equal to (M)  (I-7) if the sum is at least equal to (M), the number (M) is subtracted from the sum and the difference is stored in the data register; and, if the sum is less than (M), the sum is stored in the data register (56); and  (1-8) repeating steps (I-4) to (I-7) until (M) original image data has been supplied to the memory output.  15. Device for processing an original digital image to obtain a desired digital image on a uniformly modified scale, the original digital image having (N) successive original image data, the digital image desired having (M) successive desired image data and (M) being greater than (N), characterized by  a first linear interpolator (5); and  first control means (6), connected to the first linear interpolator (5), for controlling the linear interpolator (5) so that it performs a linear interpolation between the (n) jumper and the (n + 1) iêlo original image data to produce residual interpolated image data inserted between the interpolation data if the division of (MN) by (Nl) gives a remainder (S) and if (n) is a minimum number which fulfills the condition (n + l) * (S) 2 (s) * (N), where (s) varies from 1 to (S).  16. Device for processing an original digital image to obtain a desired digital image on a uniformly modified scale, the original digital image having (N) successive original image data, the digital image desired having (M) successive image data and (M) being less than (N), characterized in that it comprises  a first memory (2) for storing the original image data  a first address generator (37), connected to the first memory (2), for controlling the first memory (2) so as to supply a first data item from the original image data  first means of generation (33) of a number (U) which is the remainder of the division of (N) by (M)  a first data register (56)  first adding means (43) connected to the first generation means (53) and to the first data register (56), provided for adding (U) and the number stored in the first data register (56) so as to obtain a sum; and  first calculation means (44), connected to the first adding means (43), to the first address generator (37) and to the first data register (56), intended to compare the sum and the number (M) and to activate the first address generator (37) to control the first memory (2) so that it outputs another original image data which is offset from the immediately preceding original image data which appeared at the output of the first memory (2) of a number (V) equal to the quotient of the division of (N) by (M) when the sum is less than (M) and of a number (V + 1) when the sum is at least equal to (M)  said first calculating means (44) storing the difference between the number (M) and the sum in the first data register (56) if the sum is at least equal to (M) and storing the sum in the first data register (56) if the sum is less than (M).