[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

FR2791471B1 - Procede de fabrication de puces de circuits integres - Google Patents

Procede de fabrication de puces de circuits integres

Info

Publication number
FR2791471B1
FR2791471B1 FR9903536A FR9903536A FR2791471B1 FR 2791471 B1 FR2791471 B1 FR 2791471B1 FR 9903536 A FR9903536 A FR 9903536A FR 9903536 A FR9903536 A FR 9903536A FR 2791471 B1 FR2791471 B1 FR 2791471B1
Authority
FR
France
Prior art keywords
integrated circuit
circuit chips
manufacturing integrated
manufacturing
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9903536A
Other languages
English (en)
Other versions
FR2791471A1 (fr
Inventor
Olivier Brunet
Bernard Calvas
Didier Elbaz
Philippe Patrice
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Priority to FR9903536A priority Critical patent/FR2791471B1/fr
Priority to PCT/FR2000/000546 priority patent/WO2000057467A1/fr
Priority to AU31719/00A priority patent/AU3171900A/en
Publication of FR2791471A1 publication Critical patent/FR2791471A1/fr
Application granted granted Critical
Publication of FR2791471B1 publication Critical patent/FR2791471B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
    • B29C43/32—Component parts, details or accessories; Auxiliary operations
    • B29C43/58—Measuring, controlling or regulating
    • B29C2043/5825—Measuring, controlling or regulating dimensions or shape, e.g. size, thickness
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
FR9903536A 1999-03-22 1999-03-22 Procede de fabrication de puces de circuits integres Expired - Fee Related FR2791471B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR9903536A FR2791471B1 (fr) 1999-03-22 1999-03-22 Procede de fabrication de puces de circuits integres
PCT/FR2000/000546 WO2000057467A1 (fr) 1999-03-22 2000-03-03 Procede de fabrication de puces de circuits integres
AU31719/00A AU3171900A (en) 1999-03-22 2000-03-03 Method for making integrated circuit chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9903536A FR2791471B1 (fr) 1999-03-22 1999-03-22 Procede de fabrication de puces de circuits integres

Publications (2)

Publication Number Publication Date
FR2791471A1 FR2791471A1 (fr) 2000-09-29
FR2791471B1 true FR2791471B1 (fr) 2002-01-25

Family

ID=9543483

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9903536A Expired - Fee Related FR2791471B1 (fr) 1999-03-22 1999-03-22 Procede de fabrication de puces de circuits integres

Country Status (3)

Country Link
AU (1) AU3171900A (fr)
FR (1) FR2791471B1 (fr)
WO (1) WO2000057467A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2817656B1 (fr) * 2000-12-05 2003-09-26 Gemplus Card Int Isolation electrique de microcircuits regroupes avant collage unitaire
DE10151657C1 (de) * 2001-08-02 2003-02-06 Fraunhofer Ges Forschung Verfahren zur Montage eines Chips auf einem Substrat
FR2843742B1 (fr) 2002-08-26 2005-10-14 Commissariat Energie Atomique Microstructure a surface fonctionnalisee par depot localise d'une couche mince et procede de fabrication associe
FR2843828A1 (fr) 2002-08-26 2004-02-27 Commissariat Energie Atomique Support de garniture et procede de garniture selective de plages conductrices d'un tel support
FR2843830A1 (fr) * 2002-08-26 2004-02-27 Commissariat Energie Atomique Support de garniture et procede de test du support
FR3103809B1 (fr) * 2019-11-29 2022-05-27 Saint Gobain Procédé d’obtention de vitrages munis de motifs électroconducteurs

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0051165A1 (fr) * 1980-11-03 1982-05-12 BURROUGHS CORPORATION (a Michigan corporation) Boîtier réparable à circuits intégrés fixés par un produit thermoplastique
GB2179001A (en) * 1985-08-16 1987-02-25 Burr Brown Corp Method of bonding using paste or non-dry film adhesives
US4793883A (en) * 1986-07-14 1988-12-27 National Starch And Chemical Corporation Method of bonding a semiconductor chip to a substrate
WO1996013066A1 (fr) * 1994-10-20 1996-05-02 National Semiconductor Corporation Procede de fixation de puces de circuit integre consistant a appliquer a l'aide d'un cylindre des adhesifs sur des tranches de semi-conducteurs
JPH113909A (ja) * 1997-06-11 1999-01-06 Nitto Denko Corp フリップチップ部材、シート状封止材料、半導体装置およびその製造方法

Also Published As

Publication number Publication date
FR2791471A1 (fr) 2000-09-29
WO2000057467A1 (fr) 2000-09-28
AU3171900A (en) 2000-10-09

Similar Documents

Publication Publication Date Title
DE69943120D1 (de) Integrierte Halbleiterschaltung
DE69927658D1 (de) Integrierte Halbleiterschaltung
EP0973191A4 (fr) Procede de production de circuit integre
SG87191A1 (en) Method for manufacturing semiconductor chips
GB0027232D0 (en) Semiconductor integrated circuit fabrication
FR2825834B1 (fr) Procede de fabrication d'un disositif a semi-conducteur
FR2851373B1 (fr) Procede de fabrication d'un circuit electronique integre incorporant des cavites
AU2003236002A8 (en) Method for manufacturing semiconductor chip
FR2798209B1 (fr) Procede de fabrication de cartes a puce
DE60003312D1 (de) Parallelprüfer für halbleiterschaltungen
FR2788375B1 (fr) Procede de protection de puce de circuit integre
NO20006133L (no) Elektronisk halvlederkomponent
DE60135728D1 (de) Integrierte Halbleiterschaltung
DE60025067D1 (de) Cmos Halbleiter integrierte Schaltung
DE69930586D1 (de) Integrierte Halbleiterspeicherschaltung
DE69920486D1 (de) Halbleiterschaltung
AU2003291315A8 (en) Split manufacturing method for semiconductor circuits
FR2776796B1 (fr) Procede de fabrication de cartes a puce
DE60221625D1 (de) Integrierte Halbleiterschaltung
FR2791471B1 (fr) Procede de fabrication de puces de circuits integres
DE60042381D1 (de) Integrierte Halbleiterschaltungsanordnung
SG89410A1 (en) Manufacturing method of semiconductor integrated circuit device
FR2780552B1 (fr) Procede de polissage de plaquettes de circuits integres
FR2736208B1 (fr) Procede de fabrication de circuits integres
FR2781577B1 (fr) Procede de fabrication d'un circuit optique integre

Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20091130