FR2541052A1 - Improved, centralised remote-control method - Google Patents

Abstract

The centralised remote-control message comprises, on the one hand, a digitally coded binary section, including an address segment SA, an address mask segment SMA and a segment able to code for a group of orders, and, on the other hand, a non-coded binary section, each binary element of which is selectively associated with a particular order in each group of orders. At the site of each receiver member, a comparison 50 is made of the address segment SA received with a local address number NAL, apart from 51, 52, 53 of the binary elements of the address which are neutralised by the address mask segment SMA, in order to determine whether this receiver member is involved.

Description

 The invention relates to centralized remote control, a technique used in a network of electrical conductors leading to geographically distributed user devices, in particular in an electrical energy distribution network.

 In general, the centralized remote control consists in transmitting at nodal points of the network a remote control message based on pulses or wave trains of low frequency, of predetermined number, length and spacing, starting with a start pulse. , whereas at the level of at least some of the use members known as receiving members, this message is received to determine and execute the order or orders that it contains.

 At present, the applicant uses a message consisting of 40 order pulses preceded by a start pulse. All the pulses are formed by a 175 Hz wave train of duration 1 second.

The interval between the start pulse and the first command pulse is 2.75 s, while the interval between the command pulses is 1.5 s. Each order pulse is associated, according to its rank, with a particular order. It follows that there are only 40 orders. However, as two orders are necessary to perform an "off" function, there are a maximum of 20 "off" functions available. This number now appears to be insufficient to achieve fine management of the load of power stations, in particular as part of the new tariff provisions planned to reduce demand - annual peak days ("erasing peak days").

 The difficulty is that one cannot increase the number of orders thus transmitted without increasing the length of the message, and consequently the time taken for its execution, taking into account that a confirmation by a second message is most often necessary.

The present invention aims in particular to resolve this difficulty, while retaining the advantage of being able to transmit several different orders in the same message.
The object of the invention is also to offer a transmission of orders which is selectively addressed to only some of the user bodies which are fitted with receivers.

 To this end, according to the invention, a start pulse of different length is emitted than that of the other pulses; these other pulses each have a binary meaning, and together they define, on the one hand, a digitally coded binary section, comprising an address segment, an address mask segment and a segment suitable for coding for a group of orders, and on the other hand an uncoded binary section, each binary element of which is selectively associated with a particular order in each group of orders. At the level of each receiving unit, the address segment received is compared with a local address number , apart from the binary elements of the address which are neutralized by the address mask segment, the order group segment is compared to at least one local order group number, and, if the two comparisons reveal an identity, the order or orders defined by the binary element (s) received for the non-coded section are recorded in the group of orders concerned.

 The invention also aims to allow the immediate execution of certain orders. For this, the message further comprises, after the start pulse, an immediate order segment; in response to a predetermined binary configuration of this immediate execution segment, each receiving member immediately executes the corresponding order or orders, for example an immediate load shedding of the network.

In the absence of this predetermined configuration, the orders are only executed after the end of the message, with delays programmed locally.
Another object of the invention is to allow the message to be restored if it has been disturbed by a micro-cut. To this end, the message comprises a binary parity element relating to all of its pulses of binary meaning, and each receiving member comprises a device for detecting micro-cuts in the network, and means using the binary parity element. to restore, if necessary, a binary element missed during the message if the latter has only known a micro-cut.

Other characteristics and advantages of the invention will appear on examining the detailed description which follows, as well as the appended drawings, in which - Figure 1 illustrates a portion of the distribution network.
increase in electrical energy, with means for
emitting a centralized remote control message; - Figure 2 illustrates the block diagram of a reception
centralized remote control for setting
of the invention; - Figures 3A and 3B illustrate the nature of the message
centralized remote control used according to this
invention - figure 4 illustrates a central remote control message
complete line according to the present invention - Figure 5 illustrates in the form of an electrical diagram
the use of address segment and mask
of address of the message of figure 4 ;; and - Figure 6 illustrates in the form of a state diagram
the whole reception of the remote control message
centralized according to the invention.

 In Figure 1 is shown a high voltage line denoted HT. This line supplies a high voltage transformer l medium voltage, noted THM, and followed by the secondary of a TI injection transformer.

The other end of this secondary is connected to a series of medium voltage lines, marked MT. Each medium voltage line supplies one or more medium voltage / low voltage transformers, such as TMB1. Finally, the low voltage output of such transformers feeds user devices, some of which are fitted with RR receiver relays. The expression "receiver relay" is understood here to mean receiver units for the remote control, provided with relays for executing the remote control commands.

 A source ST is capable of emitting pulses or wave trains of low frequency, also called tones, under the control of a control circuit denoted CST. These wave trains are received by a parallel resonant circuit CR, and applied to the primary of the injection transformer TI. By means of this injection transformer, the wave trains in question will therefore be distributed to all the medium voltage lines, in the direction of receiver relays such as RR. The THM transformer is possibly equipped with blocking circuits preventing the ascent of these wave trains upstream, in order to prevent them from passing to other medium voltage lines across the high voltage line.

In Figure 2, the RR receiver relay starts with a circuit 10 allowing protection to
overvoltages which may exist on the supply lines.

Although only two alternative power supply lines are shown, in the hypothesis of a user station working in single phase, those skilled in the art will understand that the circuit 10 can receive three or four lines, if the user works in three-phase current.

 The output of circuit 10 is first applied to a circuit 11 allowing the supply of direct current to all the other devices.

To this end, the supply circuit It is connected to the circuits 12, 13, 14, 20 and 21. On the contrary, the order execution relays are in principle supplied directly from the alternating current.

 The hot spot or "phase" available at the output of the protection circuit 10 is that which includes the remote control wave trains, relative to the neutral line of the sector. This hot spot is connected to a filter 12 tuned to the low frequency of these wave trains.

The filter 12 is followed by a rectification and shaping circuit 13, at the output of which a detected signal is obtained consisting of the envelope of the low frequency wave trains. This detected signal is applied to a microprocessor 20. This is associated with a programmable read-only memory PROM 21, as well as with a watchdog circuit 14, which supplies it with an initialization signal, at the same time as it monitors the proper functioning of the microprocessor. The microprocessor 20 finally receives the voltage present at the hot spot at the output of the circuit 10, with dewlap able to check the permanence of the mains supply voltage. Finally, the microprocessor 20 controls a certain number of order execution relays, which are here 3 in number, and denoted 31 to 33. The respective contacts of these three relays will, when they are closed, produce the execution of orders according to the remote control.

 Reference will now be made to FIGS. 3A and 3B, which illustrate the start of a remote control message according to the present invention, respectively in the form of wave trains for FIG. 3A (output of the filter 12), and in the form of the envelope of the wave trains for FIG. 3B (output of circuit 13).

 In the preferred embodiment, the starting pulse denoted ID has a length different from that of the other pulses. In this case, the starting pulse consists of a wave train of duration 2 s, followed by a blank of duration 1 s. The pulses which follow it each have a binary meaning. Each bit is associated with a time slot of 1 s. The binary element or bit is worth 1 if it begins with a wave train of 0.5 s followed by a blank of the same length. It is worth zero if no wave train appears during the duration of 1 s assigned to this binary element.

 We thus distinguish in Figure 3 two bits assigned to a section called SEO, and other bits corresponding to the start of another part of the message, denoted SA.

 Figure 4 illustrates a complete remote control message according to the present invention. At the start, you recognize the ID starting pulse. This is followed by the SEO segment, which has two bits, and constitutes an immediate execution order, as we will see below.

 The rest of the message can be broken down into two parts. The first part is a digitally coded binary section, comprising a 6-bit SA address segment, a 6-bit SMA address mask segment, and a 5-bit SGO order group segment.

The second part, denoted SO, is a 30-bit uncoded binary section. Each bit in this section is selectively associated with a particular order in each group of orders. Finally, the message ends with a parity bit BP, relating to all of these binary-meaning pulses, namely SEO, SA,
SMA, SGO and SO.

 Reference will now be made to FIGS. 2 to 4, as well as to FIG. 6. The microprocessor 20 is normally in the standby state, illustrated by the status line 60 of FIG. 6. On the arrival of any train wave, the microprocessor 20 will first examine the start of this wave train, to see if it is indeed a starting pulse. We know that a microprocessor has an internal clock. It can therefore control the duration of the wave train, check if it measures 2 s, and if it is followed by a blank of 1 s. The detection of the start of a pulse is illustrated at 71 in FIG. 6, and results in the transition to the state 11 start of code on line 61. When a complete start pulse has been seen, what detects operation 71, we pass to the lioness 62 which prepares the microprocessor to detect the sequence of other pulses of binary meaning.

 With the message in FIG. 4, the first two binary pulses relate to the direct order section, which is detected in step 73. After this detection, the working memory (not shown) of the microprocessor 20 stores the two bits of direct orders, and we go to line 63 which starts the address detection. Step 74 consists of detecting and recording the 6 address bits, after which we go to line 64. Step 75 consists of detecting the 6 bits of the address mask segment, after which we go to line 65 which consists of calculating the masked address.

 In the microprocessor, these calculations are carried out in programmed logic, but it is also simple to describe them in wired logic with reference to FIG. 5.

For this, it is assumed that the 6 address bits received are introduced at the rate of a clock H in a register
SA receiving the address segment. Another NAL register receives at the same clock rate H a locaecod address number normally stored in the memory 21 of FIG. 2. The clock pulses are again applied to unload the registers SA and NAL synchronously in a EXCLUSIVE OR gate 50. The output of this gate will therefore only be at level 1 when a bit of the received address differs from the corresponding bit of the local address. Always to the rhythm of the same clock
H, the output of the EXCLUSIVE OR gate 50 is stored in a buffer register 51. At the same time or before the clock H ensures the loading of the address mask segment in the SMA register.

 In the preferred embodiment of the message of FIG. 4, the address mask segment comprises bits arranged in the same order as those of the address segment. When the mask bit is zero, the corresponding bit of the address segment must be taken into account. When the mask bit is 1, the corresponding address bit must on the contrary be ignored.

Under these conditions, the output of the SMA register of FIG. 5 is applied to an inverter 52, the output of which is in turn applied to an AND gate 53, at the same time as the output of the register 51. When the mask bit is at 1, the AND gate 53 will therefore see a zero input on the output of the inverter 52, and will therefore be forced to zero, even if the corresponding bit recorded in the buffer memory 51 indicated a difference between the address received and the local address. Finally, at the same clock pulse rate which ensures the discharge of the registers SMA ′ and 51, the output of the AND gate 53 is introduced into a last register 54. When the 6 stages of this register are at zero, a gate NI 55 produces a validation signal indicating that the receiver relay in question is concerned by the rest of the message (step 76 of FIG. 6, which leads to line 67 of order detection).

 In the opposite case, when the validation signal is at zero, one goes through step 77 of FIG. 6 which ends at line 66 defining a wait for the end of the frame. This means that the end of the counting of the total number of bits expected in the message is awaited, after which step 81 brings the microprocessor 20 back to the standby state on line 60.

 We will better understand address masking on an example. It is assumed that the coded address 1 0 1 0 0 0 is sent in the message, and that it is followed by a mask 0 0 0 0 1 1. In this case, the RR receiver relays having the following addresses 1 0 1 0 0 O, 1 0 1 0 0 1, 1 0 1 0 1 O, and 1 0 1 0 1 1.

With reference to the wired embodiment illustrated in FIG. 5, the number of clock pulses used will be 6 in synchronism with the reception of the address segment, for its introduction into the SA register at the same time as the local address. is entered in the NAL register. Six more clock pulses will be required to introduce the mask segment into the SMA register, along with the registers.
SA and NAL are emptied, and that the output of gate 50 is introduced into the buffer register 51. Finally, six other clock pulses will be necessary to jointly empty the registers SMA and 51, and introduce the output of gate 53 into the terminal register 54. The realization of these functions in programmed logic is carried out in a very simple manner, for example using the time counter at the step 0.5 s already mentioned.

 In passing, it will be noted that in an analogous manner, the other pulses with binary meaning of the message can either be received by wired logic circuits, or operated directly by the microprocessor, in an equivalent manner.

 Assuming that the RR receiver relay considered is concerned by the message, we will now return to line 67 of FIG. 6. The next step 78 consists in first detecting the 5 bits of the group of SGO order segment , then the 30 bits of the actual orders denoted SO in FIG. 4. After that, the parity bit BP is detected on line 68.

The next step 79 consists in verifying that we are indeed at the end of the frame, the clock counter in steps of 0.5 s having recorded a number of bits corresponding exactly to those of a message.

 Line 69 performs a parity check.

If the parity is correct, step 80 moves to line 70, which consists in interpreting the orders received.

 After that, we return to the standby state 60.

If the parity observed on line 69 is bad, it is also possible to return directly by step 82 to the standby state. In this case, any detection of a cut in the mains voltage in step 83 will also result in a return to the standby state 60.

 Furthermore, the detection at 84 of a start pulse on any one of the lines 62 to 70 results in a return to the state 61 of the start of the code. In the state diagram of FIG. 6, all the returns coming from a line other than 70 result in a cancellation of the recorded message.

 The state diagram of FIG. 6 can be easily implemented as the main program of the microprocessor 20, taking into account the description given above. However, operations 83 and 84 (detection of a power cut or of a new starting pulse) can also be carried out in the form of interruptions.

 An interesting variant of the invention consists in treating differently the presence of a power outage if it is very brief ("micro-outage", up to a few hundred milliseconds). In such a case, instead of returning to the standby state, the instant of appearance and the duration of the micro-cutoff are simply memorized in the frame (according to the basic clock of the step 0.5 s ), then continue the normal path in the state diagram.

 At the end, -if the parity bit is correct, the micro-cut is ignored, and the message is recorded normally. If the parity bit is incorrect, a bit '1' is restored if possible at the location of the micro-cut, so as to reconstruct a correct message which is then recorded normally. If this is not possible, the message is canceled.

 Although a similar correction process can be envisaged in the presence of several micro-cuts in the same frame, the Applicant currently prefers to simply cancel a message which has experienced several micro-cuts (unlikely event) and whose bit of parity is incorrect.

 The "network sync" line going to the microprocessor 20 in FIG. 2 allows monitoring of network cuts and micro-cuts. It also allows synchronization of a clock on the network, for the detection of the bits in the message frame. Of course, the power supply 11 is provided with sufficient autonomy to allow the operation of the microprocessor during micro-cuts and relatively brief cuts.

There are two ways to use received messages - for a message beginning with an instruction "order
direct "(for example code '11'), the corresponding order
will be executed immediately; this is particularly useful
send an urgent load shedding order.

- in other cases, the order is simply saved,
and will only be executed after a predetermined time, from
preferably programmed locally, in order to avoid
in sudden network load, synchronized with the message.

Those skilled in the art will understand that the present invention offers the following possibilities - 32 groups of 30 orders, ie 960 orders available - 64 zone addresses, groupable by masking - 1 immediate order for urgent load shedding - protection against micro-cutting by verification
parity - possibility to cancel a message in progress by another
more urgent by sending a new impulse from
start-up.

 Each message therefore allows the sending of 30 different orders, which can therefore be fully confirmed by a single repetition of the message, in an overall duration of 2 minutes.

 The address with masking allows geographic areas to be both fine and flexible - to selectively transmit orders to them and play over time: progressive loading of hot water tanks by area, selective load shedding, etc.

 Furthermore, it has been observed with regard to FIG. 1 that the transmission of messages upstream (high voltage / medium voltage transformation and high voltage line) is normally blocked. However, this blocking can disappear, thereby producing an upstream "remote control messages". These then disturb a region where a different remote control should be applied.

 The disappearance of the blockage of upstream lifts can be explained as follows: the electrical energy network is meshed, so as to always have a variant supply circuit (zone B) ready to replace a supply circuit normal faulty (zone A); but during such a substitution, the remote control of the variant circuit (zone B) is applied to zone A for which it was not intended. Upwelling can be done by the High Voltage network when the downstream impedance (Medium Voltage network) is low compared to the upstream impedance (High Voltage network). Normally, the upstream impedances are low compared to the downstream impedances, which does not cause upwelling.

 The present invention solves this problem masked addressing not only prevents zone A from receiving the remote control for zone B, but also quickly re-establishes a correct and selective remote control for zone A.

 The order groups complete this advantage by considerably enriching the remote control possibilities. Besides that at least part of the bits in question can also be used for unmasked addressing, these allow to group together the orders which are related to each other and will have to be confirmed together by the same message, therefore in short time. In other words, the different groups of orders may be distinguished by the family of orders of each, as well as by the category of users concerned by each, and / or the geographic area.

 It therefore finally appears that the arrangements according to the invention have considerable advantages over those used up to now.

 In practice, for the distribution of electrical energy, the low frequency of the wave trains is a frequency between 100 and 400 Hz, not a multiple of the frequency of the electrical supply voltage.

 Preferably, one chooses a frequency rather located at the bottom of the range, for example 195 Hz, to make the difference with the frequency of 175 Hz currently used.

 Of course, the present invention is not limited to the embodiment described, and extends to any variant included within the scope of the claims below.

Claims (9)

CLAIM  1. A method of centralized remote control in a network of electrical conductors leading to geographically distributed user bodies, in particular in an electrical energy distribution network, in which a point is emitted at nodal points of the network (THM, TI) remote control message based on pulses or wave trains of low frequency, of predetermined number, length and spacing, starting with a starting pulse (ID), while at the level of at least some of the operating members ( RR), called receiving organs, we receive this message to determine and execute the order or orders it contains, characterized by the fact that we send a start pulse (ID) of length different from that of the other pulses, these other pulses each have a binary meaning, and that they together define, on the one hand, a binary section digitally coded, comprising an address segment (SA), an address mask segment (SMA) and a segment able to code for a group of orders (SGO), and on the other hand a non-coded binary section (50), each binary element of which is selectively associated with a particular order in each group of orders, and thereby that at the level of each receiving organ, the address segment (SA) received is compared with a local address number (NAL), apart from the binary elements of the address which are neutralized by the mask segment address (SMA), the order group segment (SGO) is compared to at least one local order group number (NGOL), and, if the two comparisons reveal an identity, the order or orders defined by the binary element (s) received for the non-coded section (SO), in the group of orders concerned.  2. Method according to claim 1, characterized in that the message further comprises after the start pulse, an oath of immediate order (SEl), and in that in response to a predetermined binary configuration of this immediate order segment (SEI), each receiving unit immediately executes the corresponding order or orders, whereas in the absence of this predetermined configuration, the orders are only executed after the end of the message.  3. Method according to one of claims 1 and 2, characterized in that the message comprises a binary parity element (BP) relating to all of its pulses with binary meaning, and by the fact that each receiving organ ( RR) includes a device for detecting micro-cuts in the network, and means using the parity binary element (BP) to restore, if necessary, a binary element missed during the message if it has not known a queue microcut.  4. Method according to claim 3, characterized in that the message is canceled at the level of the receiving member (RR), If it has experienced several micro-cuts.  5. Method according to one of claims 1 to 4, characterized in that the address segment (SA) and the address mask segment (SMA) are of the same length.  6. Method according to one of claims 1 to 5, characterized in that the address segments (SA) and address mask (SMA) occupy 6 bits, the group segment of order 5 bits, and the 30-bit uncoded section.  7. Method according to one of claims 1 to 6, characterized in that the starting pulse consists of a wave train of 2 seconds followed by a silence of 1 second.  8. Method according to one of claims 1 to 7, characterized in that the pulses with binary significance consist of a wave train of 0.5 seconds followed by a blank of 0.5 seconds.  9. Method according to one of claims 1 to 8, characterized in that the low frequency of the wave trains is a frequency between 100 and 400 Hz, not multiple of the frequency of the power supply voltage.