CH411026A - Installation for the transmission of coded signals over telephone lines - Google Patents

Description

Installation for the transmission of coded signals over telephone lines The object of the invention is a transmission installation capable of correcting groups of errors occurring in coded signals transmitted by telephone lines. The expression group of errors designates a set of several errors generated during the transmission. These groups can be caused, for example, by lightning strikes. The installation, according to the invention, is simple and inexpensive, its synchronization being easy to ensure.

Known methods for detecting and correcting errors are not capable of dealing with several successive errors or require complicated installations that are difficult to synchronize.

Error correction devices are not necessary for the transmission of signals such as spoken language or television, since these signals have a very high redundancy which reduces the disturbing effects caused by errors. On the other hand, in Information transmitted in the form of digits, an error in a single digit may render an entire group of digits unintelligible.

The installation according to the invention makes it possible to correct groups of errors of any length. In general, plus the 1st group of errors. The maximum length will be short, plus the installation will be simple. Likewise, the shorter the error groups, the shorter the error-free interval between two consecutive error groups.

The installation according to the invention comprises a circuit serving to correct a group of errors, this circuit comprising at least one position change register, means for applying a series of digits to said change register of Position, means for successively moving

sively said digits to successive digit positions in the position change recorder during successive intervals of time, and connected monitoring devices with at least two digit positions, spaced from each other, of the recorder position change for forming the check digits, characterized in that it comprises a device for inserting each check digit in said series of digits at a point remote from the digits, which are controlled by said check digit.

The design represents, by way of example, one form of execution of the installation which is the subject of the invention. FIG. 1 is a block diagram of the installation according to the invention; fig. 2 is an explanatory diagram of the operation of the installation according to FIG. 1; fig. 3 is a detail diagram of the installation according to FIG. 1; fig. 4 is a block diagram of an error detection circuit, which can be used in the installation according to FIG. 1; fig. 5 is a detail diagram of the error detection circuit shown in FIG. 4; fig. 6 is a diagram explaining the operation of the error detection circuit according to FIG. 5; fig. 7 shows an example of a group of correctable errors; the figs. 8 and 9 respectively represent a group of errors likely to be detected.

fig. 1 is a block diagram of a continuous error detection and correction device. In fig. 1, the information, which consists of digits one of which is zero and the other one, is provided from a source 22 to a position change recorder 24. The positions of the digits in the recorder Position change recorder 24 are indicated by the numbers 1 to 7. following memory devices: they could, if necessary, be constituted by intermediate-tapped delay lines from which the signals introduced can be taken at regular time intervals.

Check digits are formed from the information digits present in the position change recorder 24, by means of a circuit 26 forming these check digits. The check digits are added to the information digits by means of a switching circuit 28 and the resulting encrypted message is applied to a transmission channel 30. It should be noted that the circuit 26 forming the check digits receives its input signals from digit positions 1 and 4 of the Position change register 24 and that each of these check digits is inserted in the transmitted message at a point separate from Position 4 of the Digit, by various additional information and by other check digits. This digit spacing makes it possible to correct groups of errors whose length is equal to or less than six digit periods, as will be explained in detail later.

The use of check digits for error detection or correction is well known. However, it should be noted that a Check Digit may be formed by the sum of the digits of a group of binary digits. In the first case of FIG. 1, the relationship between each Check Digit and the information digits adopted by the check can be given by the following equation D1 -f- D4 = C (Mod 2) (1) where D1 and D4 are the binary digits stored in the Position Change Recorder at positions 1 and 4, and C is the resulting Check Digit. Thus, for example, if both data digits in positions 1 and 4 are 1's or if they are 0's, the Check Digit is a 0'. However, if only one of the two information digits is a 1, then the Check Digit is a 1.

The deciphering device is visible on the right of fig. 1. The binary digits coming from the transmission channel 30, which is disturbed by parasitic signals, are separated by means of the switching circuit 32, the information digits being directed to a register 34 reserved for the information digits. This register being a position change register and the check digits being applied to a position change register 36 intended for the check digits. The groups of non-simultaneously transmitted digits which will be further discussed below, and each of which comprises two information digits and a check digit, are formed in the cipher device. Further, each Information Digit is first included in such a group when in Position 1 of the position change register 24 of the cipher device and then is included in such another group when It is in Position 4 of this same position change recorder. In the deciphering device, the preservation of the relations formed at these two positions is examined at the same time by the R control circuit 38 and by the S control circuit 40. Thus, the control circuit 38 receives its signals from digit positions 1 and 4 of info digit register 34 and from Digit Position 7 of check digit register 36. positions 4 and 7 of register 34 and Digit Position 10 of check digit register 36. The only common input for both control circuits 38 and 40 is connected to Digit Position 4 of 1 information digit recorder 34.

If both control circuits indicate an error at the same time, Digit 4 is the one with the highest probability of being false. Consequently, the Et circuit 42 is energized to activate a correction device 44.

It should be noted that if an error indication is given by the check circuit 40, but not by the check circuit 38, this indicates that the Check Digit 10 is erroneous and this conclusion is reached by the elimination of other possibilities. Indeed, the control circuit 40 has two inputs connected respectively to Digit Position 4 and to Digit Position 7 of the register 34. If the information Digit in Digit Position 4 was incorrect, a an error signal would appear at the output of the two equality control circuits 38 and 40 and thus this possibility is eliminated. The Digit in Digit Position 7 cannot be wrong because all of the digits are corrected between positions 4 and 5 of the Position Change Recorder 34. Therefore, only Check Digit 10 can then be wrong. If the deciphering circuit shown is to be used as a relay station to provide retransmission across an RTI ID="0002.0537" WI="8" HE="4" LX="1654" LY="2245"> other disturbed channel There must be circuitry to change the Check Digit to Digit Position 10 of the register 36 after an error indication has been issued only by the check circuit 40.

It should be noted that the output circuit 46 of the decryptor is cut off at the output of Digit Position 5 of the recorder 34. Digit Position 5 is chosen to reduce delays, since it constitutes the first point at which the corrected figures of information are available. If output circuit 46 were coupled to Digit Position 7, an additional delay equal to two time units would be introduced.

The diagram of fig. 2 indicates the first mode of operation of the circuit of FIG. 1 with more details. In the diagram of fig. 2 are represented a succession of information digits and the corresponding check digits as well as the transmitted signals. Successive rows of this diagram indicate successive time intervals of movement in the position change recorder 24 of FIG. 1. In the initial state shown in the top row of this diagram, digit positions 1 and 4 both include a 0 .

Therefore, the corresponding check digit is a 0; it is visible in the column designated by C . In the next period, the check digit as well as the information digit that was in Digit Position 7 are both transmitted, as indicated by the right end of the second line of the diagram. It should be noted here that a check digit is generated during each Period and that an information digit and a check digit are transmitted during each Period.

To make it possible to follow, on the first diagram of FIG. 2, the First group of two check digits which occurs, these two digits as well as the corresponding check digit are marked with a square surrounding these digits. In another group of two check digits which is formed by using a diamond around each digit and the corresponding check digit. It can easily be seen that the information digit which originally occupied Digit Position 1 is on the position change recorder in the upper row of the diagram. moved ddp1.ace to the number 4 position in the fourth row of the chart. Thus, it is then comprised in a group of check digits marked by a square and in a group of check digits marked by a diamond. In the deciphering device, this digit, which is included in the two groups of digits checked, should then end up in Digit Position 4 of the position-changing register 34. Then, the circles of count 38 and 40 determine whether the groups indicated by the diamonds and squares respectively in Fig. 2 have been transmitted correctly or not, and they correct the common digit if further action is required. .

fig. 3RTI ID="0003.0276" WI="5" HE="4" LX="429" LY="2263"> is a detailed diagram of the installation according to fig. 1. To simplify the representation of the circuit and to avoid crossing the wires, an has used the method of separated contacts to represent the relays. In this method of representation, a relay is designated by a capital letter and by an index where the contacts belonging to these relays are designated in the same way. The working contacts of a relay, which are closed when the relay is energized, are indicated by a cross on the conductor in which these contacts are mounted. The symbol for the work contacts of the Al relay is 1e following

The rest contacts are represented by a short straight line which is perpendicular to the conductor in which they are mounted.

To facilitate identification of the elements represented in fig. 1 in the circuit shown in FIG. 3, the greater part of the elements of FIG. 3 has been designated by the same indices quo in fig. 1, these are however assigned a prime sign. Thus the source 22' of information signals which are in digital form is coupled to the position change recorder 24' of FIG. 3 in the same way that the source 22 is coupled to the position change recorder 24 of FIG. 1. Other elements of fig. 3, already shown in FIG. 1, are the check digit circuit 26', the switching circuits 28' and 32', the transmission channel 30', the position change registers 34' and 36', the control circuits 38' and 40', the 1st correction circuit 44' and the 1st output circuit 46'. It should be noted quo the first circuit 44 'of FIG. 3 assumes either the function of the Et circuit 42 or that of the correction circuit 44 of FIG. 1.

The installation according to fig. 3 requires different synchronization or control pulses, and it is assumed that these signals are, if not otherwise, available in the transmitter and in the receiver. To avoid the use of a special channel for the transmission of these signals, one can provide in the deciphering device known circuits for forming the synchronization signals.

Three control circuits are shown, left in the lower part of FIG. 3. These three circuits are constituted by frequency divider circuits, they are for example such quo those described in the book The Design of Switching Circuits. by William Keister, D. Van Nostrand Company, Inc., New York 1951. Their W1 and Z1 RTI Relays ID="0003.0546" WI="19" HE="4" LX="1683" LY="2102"> work at half the speed of the Y relay, and they do not work exactly simultaneously. Likewise, the relays W2 and 7@ work at a speed equal to half that of the relays W1 and Z1 and they do not work at exactly the same time either. It should be noted that these relays are designated by W1, Z1, W2 and Z2; some of their contacts are at different points in the circuit of FIG. 3, points which are remote from the corresponding circuits.

The reoption of the information signals coming from the source 22' is controlled by a contact W2. The position change recorder 24' comprises seven pairs of relays, one of which is designated A, and the other B, the letters being provided with the appropriate indices 1 to 7. Each relay comprises two relays designated by the upper parts and of the corresponding rectangle. The transfer of information in the position change recorder is controlled by a pair of make and break contacts of relay Z2, pair which is indicated on the left in the lower part of the change recorder. from Position 24'. Relay Z2 is energized For a Period of time exceeding the Period during which relay W2 is energized, the energization of relay W2 being interrupted with the release of relay 22. After the interruption of the energization of relay 22, 1 The supply of the two relays is interrupted for a short period of time, before the supply of relay W2 resumes.

The information is received by relay A1 as soon as break contacts W2 are closed. At this moment, the work contacts of relay ZZ are closed. When relay ZZ changes position, its rest contacts are closed before its work contacts are opened. Relay A1 is then maintained in the Position corresponding to the information at the time of interruption of the power supply to relay Z2, this, thanks to contacts Al, which constitute a holding circuit for relay A1 through rest contacts Z2. In addition, when the rest contacts of relay 72 are closed, the first relay B1 takes the position of relay Al.

When relay ZZ is energized again, information is moved from relay B1 to relay A2 in the same manner as previously described. The supply of relay 7@ and the opening of break contacts 7@ cause the interruption of the supply of relay Al prior to the reception of an input information from source 22'. In a similar manner, information is conveyed from relays A to relays B in position change registers 34' and 36'.

Circuit 26' is a simple network formed from rest and work contacts of relays Al and A4. It comprises an arm constituted by the work contacts A4 in series with the break contacts Al, this arm being mounted in parallel with an arm made up of the break contacts A4 in series with the work contacts Al.<B> This circuit does not give a negative output voltage when both relays are in the same energized state, and gives a negative output voltage when one of the two relays is energized.

The RTI circuit ID="0004.0275" WI="20" HE="4" LX="587" LY="2329"> switching 28' takes the information present at the output of the last relay (B7) from 1 Position change recorder 24' or Gel present at the output of circuit 26', depending on whether the power supply to relay ZZ is ensured or interrupted. Relay Z1, when the operating speed is greater than that of relay Z2, controls the generation of pulses of a length appropriate to the application to transmission channel 30'. The switching circuit 32' arranged at the input of the receiver likewise comprises a pair of rest and work contacts associated with the relay Z2. The output signals from switching circuit 32' are directed to the information digit recorder 34' and the check digit recorder 36'. A buffer relay designated BF is used to synchronize the output signals applied to the last two position change registers. Each of the position change recorders 34' and 36' is provided with transformer control circuits including the relay Z2, as described above for the recorder 24'. Correction circuit 44' is located in the middle of position change recorder 34'. The control circuits 38' and 40' control or as hereinafter referred to control the supply to the relays R and S, which in turn control the correction circuit 44'.

The maintenance of the relationship between the first and fourth information digits and the seventh check digit is examined in the control circuit 38'. Cola is made possible thanks to the presence of contacts associated with relays Al and A4 of the position change recorder SR., and by the presence of contacts associated with relay A; of the position change recorder SR, in the supply circuit of the relay R. Similarly, the supply circuit of the relay S of the control circuit 40' comprises the contacts designated by A4 and A7 of the Position change recorder SR" and the Alo contacts associated with the position change recorder SR3.

It will be recalled that it is necessary to reverse the information digit between digit positions 4 and 5 in position change register 34 when both monitoring circuits indicate an error. In the first circuit of FIG. 3 a toll error, is indicated by the simultaneous powering of the R and S relays. rest of relay A, this Jans 1st supply circuit of relay B4. Thus, if the power supply to relay A4 is interrupted, the energization of relays R and S produces the inverse state of relay B4 after the arrival of a Position change signal. Similarly, the break contacts of relays R and S are connected in series with the make contacts of relay Aa to prevent relay B4 from being energized when relay A4 has been energized. However, when only one of the R and S relays is energized, the status of relay A4 is transferred to relay B,1. Consequently, the information digits are corrected only when the R and S relays are energized simultaneously.

Circuit 46' receives the input signals from relay B4, which is the first point in position change register 34' at which the corrected information digits are available. Make contacts W1 and break contacts Z2 perform monitoring functions and route signals to output circuit 46'.

The circuit of fig. 1 can correct groups of six errors. When longer groups of errors occur, it is advisable to activate an alarm circuit. Most of these longer groups can be detected by examining the sequence of output signals from the R and S circuits. will pass naturally undetected. Further, if two check digits separated by six digit positions in the transmitted message are reversed, this error results in the reversal of a correct information digit.

However, most error groups longer than six digits can be detected by means of a simple circuit which is shown in fig. 4. This figure actually shows the receiver and error correction circuitry of fig. 1, as well as some additional error detection circuitry. These error detection circuits include a source of synchronization pulses 48, a start circuit 50, a counter 52, an error group classification circuit 54, an alarm circuit 56, and a circuit 58 of cycle repetition. The appearance of an output signal in monitor R circuit 38 initiates the operation of counter 52. Circuit 54 compares the output signals of monitor circuits 38 and 40 during successive time periods with the signals transmitted when clusters of correctable errors occur. In order to be able to carry out this comparison, the groups of errors capable of being corrected are classified by the circuit 54. The signals from the monitoring circuits 38 and 40 are applied to the group of errors classification circuit 54 During the successive intervals of Position change counted by the circuit 52. The groups of errors are classified as erroneous information digits, or as erroneous check digits. Once this classification of the output signals from the control circuits has been made, the errors. code likely to be corrected can be seen more easily. When such an error occurs, the alarm circuit 56 is activated. After a group of correctable errors has been fully identified, the RTI repeater circuit 58 ID="0005.0276" WI="8" HE="4" LX="945" LY="2130" "> cycle is energized and the elements of the error correction circuits are reset to their initial states.

fig. 5 represents the relays of the additional error detection circuits represented in FIG. 4. The notation used in fig. 5 is that of FIG. 3. In fig. 5, the R, S and Z relays are represented only by their contacts.

The main circuit element shown in fig. 5 is a pad switch which acts as a counter and which comprises an on coil 60, a reset coil 62 and three banks of ten contacts each comprising an Off Position, and ten contacts intended to cooperate with the contacts. mobiles. The contact switch cooperates with designated contacts off the normal circuit shown at two points in FIG. 5. These normal off contacts are closed whenever the stud switch is moved from the rest position. Thus, for example, after an initial pulse has been applied to the on coil 60, thanks to the closure of the work contacts R of the relay R shown in FIG. 3, the normal off-circuit make contacts allow the continuous advancement of the step switch by means of position changing pulses generated by the make contacts Z2. The circuit of fig. 5 classifies errors into two categories; With a view to this classification, the succession of operations of the circuits for checking equality R and S is examined, and the groups of errors which exceed the possibilities of correction of the set described cause the feeding of the alarm relay AL.

The operation of the circuit of fig. 5 is represented in fig. 6. In general, errors are initially classified as correctable, ie, errors initiated by an erroneous check digit or an erroneous information digit. In fig. 6, this determination is represented by the rectangle designated by the circled letter D. In particular, the Home Position of the circuit 5 is indicated by a large rectangle designated by the circled letter A. This Home Position is - presents the first circuit of fig. 5 in its normal state. Under these conditions, the stud switch is in its normal position, with the movable contact associated with each of the banks in the positions shown in fig. 5, and all relays AL, M, N and T in tripped position.

If no fault of the West equality detected by the circuit 38 of FIG. 4, RTI ID="0005.0549" WI="3" HE="4" LX="1444" LY="1721"> 1st circuit of fig. 5 remains in this Resting Position. After a d6 fault is detected by the R circuit, the pad switch advances one step. In; this state, designated by the circled letter B in fig. 6, the power supply to relays M and N remains interrupted. It should be noted that in fig. 6, each arrow represents the passage of the switch from one state to the next. These arrows are designated by one or more letters R, R', S or S'. The designation R indicates a fault detected by the circuit R of FIG. 4. Failure to detect a fault by circuit R is indicated by R'. Similarly, the letters S and S' respectively indicate a fault or the absence of a fault in the circuit S of FIG. 4.

Each operating cycle of the Synchronization relay 7-2 of fig. 5 is represented by a bit of FIG. 6. Thus, during the cycles in which the circuit R does not detect a fault, the state of the circuit of FIG. 5 follows the arrow designated by R′ associated with state A in FIG. 6. The fact that the state of the circuit has not undergone any change is represented by the bit R' situated on the rectangle A and which indicates that the circuit has remained in the same state A. The bit which couples the states A and B is denoted by R and indicates that the change of state was caused by a fault detected by the circuit R. 2 and 3, respectively, independently of the signals supplied by circuit R during these stepping intervals.

The circuit advances from state D to state E or state L, depending on the nature of the signal coming from circuit R. If circuit R does not emit any output signal as represented by symbol R', The error resides in the check digit, an error which is capable of being corrected, and the circuit of FIG. 5 is switched to state E of FIG. 6. However, if circuit R indicates a fault, the circuit of FIG. 5 is switched to Fstate L, the error being in the information digit which can be corrected.

This follows from examination of the upper and lower position change registers of FIG. 4 and connections with the first circuit 38. More precisely, after. the arrival of an Initial Fault Signal from the circuit which caused the transition from State A to State B, the information digit in the First Stage of the Upper Position Change Recorder , or the check digit in the seventh stage of the lower position change recorder may be incorrect. If <B>C</B> is the information digit which is erroneous, a second fault signal is emitted by circuit R after three cycles of Position change. The resulting signal denoted by R produces the transition from state D to state L, as indicated in fig. 6. However, if it is the Control Signal in the seventh Position of the lower register which is in error, there is no such thing. expect other error signals from circuit R. Therefore Signal R' will represent the transition from state D to state E.

Referring to state E (FIG. 6), it should be noted that the pin switch is in the position of pin 4 and that relays M and N have their power interrupted. However, in the L state, the stud switch is in the quiescent state, and the N and M relays are energized. The step-by-step comparison between the state diagram according to FIG. 6 and the first circuit diagram of FIG. 5 Will now be made in more detail. Initially, as mentioned, the closing of the make contacts R results in the energization of the coil 60, which causes the pad switch to leave its normal or rest position. The normal off work contacts parallel the R work contacts shunting the R contacts, and the work contacts 22 energize the coil 60 during each cycle until the stud switch is returned to the rest position. Consequently, advancing the switch to Pins 1, 2 and 3 to produce states B, C and D is frequent since, as shown in FIG. 6 there are no other alternatives. However, after Plot 4, the bifurcation represented in the diagram requires the action of the following elements of fig. 5. When placed in the Start Position, the Pin Switch always moves to Level 4. In this Position, if the R relay is energized, the T relay is energized through the path including conductor 63, a break contact M, a break contact N, a make contact R, a make contact of the contact switch, the conductor being on the right side to the top In the diagram of fig. 5, work contacts Z2 and the 1st negative point. The supply of the relay T causes the closing of the work contacts T mounted in series with the break contacts 22 and the actuation of the coil 62. The contact switch is therefore returned to the rest position during the second half of the walk cycle.

In accordance with the remark made previously, during the 1st transition from state D to state L, relays N and M are energized. Indeed, the work contacts T mounted in series with the 1st relay M and the 1st negative point connected with the 1st bank 2 of the contact switch cause the supply of the relay M. The contacts of the relay M are arranged in such a way that the iron - breaking of its work contacts takes place before the break of those of rest to ensure the supply of the relay M through the work contacts M. In addition, the 1st relay N is supplied immediately after the interruption of the supply of the relay T. The the supply path of relay N begins at the negative point located below bank 1, passes through the push button BP with make contact, the break contacts T, the make contacts M, the coil of relay N and resistor 64. Make contacts N which shunt make contacts M and break contacts T form a holding circuit for relay N.

In the preceding paragraph, an considered the bifurcation of the diagram of fig. 6 from state D to state L; in the case where the relay R is not energized, an passes to state E. State E can lead to additional states F to K, and state L can lead to states M, N, O and P to X. Each of these two paths will now be described with reference to the circuits of FIG. 5.

If the 1st relay E is not energized (this is the case of the transition from state D to that E in fig. 6), the 1st contactor with pads of fig. 5 continues its normal stepping action. This action can continue from state E to state K in which the pin switch reaches pin 10. in states E to K of fig. 6, the first alarm circuit is then energized. Referring to fig. 5, it is seen that this takes place by connection with the 1st alarm relay AL, connection which is established by the common connection of the Pins 5 to 10. close only if a fault is signaled by the current R during the stepping motion and the stepping make contacts located on the Passing conductor on the very top right side of fig. 5, the Z. contacts, and the 1st negative point. Closing of work contacts R in this circuit supplies power to the alarm relay when a fault is signaled by circuit R During the transition from state E to state K.

Advancement of the stud switch to the tenth level automatically resets the switch circuit during the second part of the stepping cycle. This is accomplished by the negative potential applied to level 10 of bank 3 of the pad switch. This source of negative potential energizes relay T at the end of the first half of the stepping cycle. During the second half of this cycle, after the closing of the break contacts Z 1 , the reset coil 62 of the contact switch is energized. It should be noted that this action is similar to that executed after the transition from state D to state L (fig. 6). However, the N and M relays are not powered when the contact switch is reinstalled on the tenth level, since the supply circuits of the N and M relays are not connected to level 10 of bank 2 of the switch. ä Plots. As in the previous case in which the supply of the relay T was discussed, the relay T is returned to the Rest position in which it is not supplied by the opening of the normal off-circuit work contacts in its holding circuit, after the resetting of the switch to pads.

* In the preceding paragraphs we have considered the possible sequences of errors beginning with an error in a Check Digit, an error likely to be corrected. The class of groups of errors indicated by the transition from state D to state L is that in which the initial error is an error in the information digit, an error capable of being corrected. rigid. The circuits shown in fig. 5 to examine whether groups of errors of this class can be corrected, will now be considered.

Referring to fig. 6, it is seen that the diagram can branch off from state L to states M or P. In addition, starting from state L, the circuit of FIG. 5 can pass to the state Y in which the alarm relay AL is energized. This corresponds to the state shown in FIG. 4, in which it was determined at the beginning that <RTI ID="0007.0278" WI="3" HE="4" LX="437" LY="2210"> the 1st Information Digit in stage 4 of the Position change recorder is wrong. Therefore, when the Check Digit is moved from stage 9 to stage 10 an error will be reported. This error is obviously part of a group of large errors and the supply of the alarm relay is caused.

The three states M, N and O correspond to situations in which the error in the Check Digit has not yet been signaled because this Digit has not arrived at Position 10. When an error has occurred in a Check digit, the state of the circuit according to fig. 5 passes from state L, M or N to state P. In all cases, passing through state O, leads to state P. States L, M, N and O are characterized by 1 the supply of relays N and M. The passage through the state P, causes the triggering of relay M, while the relay, N remains energized. The transition from state L, M and N to state P requires that relay R be energized and that the supply of relay S be interrupted. Under these conditions, make contacts R and break contacts S are closed. Referring now to FIG. 5, pads 1, 2, 3 of bank 3 are connected with a negative point through make contacts M, rest contacts S, make contacts R, make contacts of the contact switch and work contacts 72. Relay T is therefore energized. When the 1st relay T is energized, the working contacts T close the 1st circuit between the. contacts 1 to 4 of bank 2 through the make contacts N of the positive side of the coil of relay M. It should be noted that a negative point is connected with the movable contact of bank 2 of the switch ä Plots. Consequently, when the contacts T close, both sides of the coil of the relay M are brought to the same negative potential and the supply to the relay is interrupted. Resistor 65 is provided to prevent the power source from being short-circuited.

When the first circuit of FIG. 5 is in state O, the next step of the pin switch which momentarily reaches pin 4 produces the Transition to state P where the pin switch is in the rest state. This is accomplished by connecting to contact 4 of bank 3, which energizes relay T if relays M and N are energized and work contacts M and N are closed. RTI ID="0007.0552" WI="8" HE="4" LX="1192" LY="1746"> In this case, a similar sequence of operations performed by the contacts leads to the result mentioned before, e.g. relay N remains energized and the 1st relay M releases.

From state L and M, energizing relay S without energizing relay R produces the circuit's transition to state Y, in which the power supply to the alarm relay is interrupted. This operation is carried out by contacts 1 and 2 of bank 1 of the contact switch. These contacts are connected on the one hand by the 1st movable contact of the switch with studs with the 1st alarm relay AL and on the other hand with a point at negative potential by the work contacts M, the rest contacts R, the work contacts S , the make contacts of the contact switch ä Plots and the make contacts 2#. The supply of the circuit of the alarm relay after the arrival of a signal S at state N is accomplished by the circuits coupled with the contact 3 of bank 1. The negative potential is applied to the alarm relay by means of work contacts N, M and S, the work contacts of the contact switch and the work contacts of relay Z2. Going to State P indicates that at least one error has occurred and further indicates that the circuit can tolerate only two additional errors in the check digits and no errors in the information digits. These criteria can be verified by considering the condition of the deciphering device in fig. 4, after an error in the information digit has caused the transition from state D to state L. Under these conditions, the transition from state P or Q to alarm state Y has takes place after relay S is energized. After state Q, no new error is allowed. Consequently, a fault signaled by the circuit R causes the transmission of an alarm signal.

The protection interval between the successive groups of errors is formed by the steps corresponding to States T to X of the state diagram of FIG. 6. Some additional errors that occur to the deciphering device of FIG. 4 are controlled first by the equality control circuit R and the circuit of FIG. 5 goes immediately to the alarm state Y. It should be noted that the States W and X correspond closely to the States F and G discussed above; The pin switch is on pin five and it tends to move step by step if the R relay fails to operate and to close the alarm relay if the R relay operates. As previously indicated, the alarm relay supply circuit AL includes the movable contact on bank 1 and the circuit connected to contacts 5 and 6 of bank 1 which includes make contacts R, the working contacts of the switch ä. Studs and work contacts Z2. For the states T and V from which the contact switch reaches contacts 3 and 4 respectively, the circuit for activating the alarm relay AL is still the same. Thus, when the contact switch reaches contact 3 from state T, the alarm relay actuation circuit comprises work contacts N, break contacts M and T and work contacts R in addition to the make contacts of the jog relay and relays 72. When state X is reached without an additional error occurring, the switching circuit is returned to its rest position, or state A. This means the protection interval has elapsed and the circuit is ready to RTI ID="0008.0278" WI="12" HE="4" LX="313" LY="2156" > correct a new group of errors. The reset operation is performed by the seventh level contacts of banks 2 and 3. More specifically, the level 7 contact of bank 3 energizes relay T to initiate the usual put back in place, and the application of a negative potential to contact 7 of bank 2 eliminates the first short-circuit of relay N. The circuit of FIG. 5 is therefore again in the quiescent state, with the contact switch in the quiescent state and the relays N, M and T not energized.

When the 1st alarm relay is energized, it is necessary to operate the tripping pushbutton, the contacts of which are designated by BP in fig. 5. Actuation of the pushbutton contacts causes the holding circuits for the alarm relay and the N and M relays to open. It therefore contains the contacts which reset the contactor switch. Two signal lamps are provided, which indicate the state of the error detection circuit according to FIG. 5. The yellow alarm lamp is on during operation of the circuit of FIG. 5 when it is not in the resting state corresponding to state A in FIG. 6. The red alarm lamp is on, when the alarm relay operates.

An example of each possible kind of error is given below, together with an explanation of the corresponding behavior of the circuits according to FIGS. 4 and 5 will facilitate a good understanding of the operation of the installation.

Suppose that a group of 28 digits represented in the first row of fig. 7 is applied to channel 30 (fig. 1). This group consists of 14 check digits C and 14 information digits D. Let us further assume that the check digit Clo at the far right is transmitted as Prime and that all digits following the group of 28 digits include a 0. .

Assume that the group of transmitted digits includes errors. In particular, suppose that the three consecutive digits underlined are incorrect. At time <I>to</I> the check digits C in positions 1 to 10 are stored respectively in digit positions 1 to 10 of register ä. Position change for check digits 36 (FIG. 4) and information digits D Jans positions 1 to 7 are stored respectively in digit positions 1 to 7 of the position change recorder for digits. information 34. At this time RTIID="0008.0552" WI="10" HE="3" LX="1591" LY="1704"> control circuit R 38 is receiving signals from digit positions 1 and 4 of the information digit register 34 and from Digit Position 7 of the check digit register 36 and indicates an error. Therefore, circuit 38 provides Signal R which energizes the coil of relay R (Fig. 3).

The start coil 60 (fig. 5) of the contact switch is then energized through a work contact R, when the coil of the relay ZZ is energized and it closes the work contact ZZ (fig. 5). . The energized coil 60 causes the advancement by one step of a movable bottom of each bank of the contactor with pins so that it comes to Position 1. This advancement corresponds to the passage of the Aat of rest A (fig. 6) in state B.

At time t1 (Fig. 7) the digits have been moved two digit positions to the right. Then, the R control circuit 38 indicates an error. The Plot switch advances to Plot 2, which corresponds to state C (Fig. 6). At time t2 a change of Position of the digits takes place and the circuits R and S do not supply any Signal from dHaut. The switch ä. Plots advances to Plot 3, which corresponds to state D (fig. 6). At time t3 a change of Position of the digits takes place. The R and S circuits both provide a Fault Signal. The fault signal supplied by circuit R causes the circuit to go to state L.

At time t4, the information and control digits are moved two digit positions to the right. The erroneous information digit is corrected by the circuit 44 (FIG. 4), because the two control circuits R and S simultaneously indicate an error and they feed the circuit Et 42. In fig. 7 The corrected 1st information digit D in row t4 is underlined and circled.

Consecutive Position changes of digits take place in a similar manner as described. Subsequently, the two erroneous information digits are corrected and state X is reached. Finally, the control circuit R 38 provides a Signal R' which resets the circuit to the rest state A (FIG. 6).

Thus, the circuits according to FIGS. 4 and 5 automatically correct the two erron6s information digits D without the activation of the alarm circuit 56 (FIG. 4). These two figures of information could be corrected, because the group of errors represented in fig. 7 is three digit positions long.

Let us now assume the presence of a group of errors with a length equal to 8 digit positions. Such a group of errors cannot be corrected automatically by the installation described which must in this case activate the alarm circuit 56 (FIG. 4). This group of errors is represented in fig. B. The top row of digits corresponds to a group of digits provided without errors and the second row (t) comprises three erroneous digits belonging to the group of digits of the top row, which have been reversed during transmission.

The consecutive changes of Position of the digits represented in fig. 8 cause the passages of the circuit according to FIG. 5 from state A to state B, to state C and to state D. At time t3 circuit 5 supplies a fault signal, because digit D4 is incorrect, but circuit R does no fault signal, because digits D4 and C7 are wrong & . The circuit according to FIG. 5 therefore passes from state D to state E. At time t4, circuit S does not supply any signal from Maut, but circuit R supplies one, which causes RTI to pass ID="0009.0279" WI="10" HE="4" LX="439" LY="2149"> circuit from state E to state Y. Thus, the coil of the alarm relay AL is energized and the red lamp (fig. 5) s 'alight.

Thus, an has shown that a group of errors of a length equal to 8 digit positions causes the activation of the alarm circuit 56 (fig. 4) to signal the presence of a type of error which cannot be corrected by installing according to figs. 1 and 4.

It can easily be shown in the same way that the first group of errors according to fig. 9 causes meine the actuation of the alarm circuit 56. In the previous description the first deciphering device shown in FIGS. 1 and 4 includes a position change register for the check digits and another for the information digits. These recorders can of course be constituted by a single recorder connected with the equality control circuits.

In the circuits described, the group of equalization control circuits were connected in a single well-defined way. In some cases, it may be desirable to reduce redundancy by providing the ability to use two or more equalization control systems in a single installation.

The circuits described were designed to use binary digits. It is of course necessary to provide installations using bases larger than two. For example, the check digits can be formed by adding the information digits contained in the equality check circuit with the module forming the basis of the number system. So, if for example an needs to form an equality check digit to check two input decimal digits which are 7 and 9, for example, the resulting equality check digit will be 4.

This number can be obtained by adding 7 and 9 and subtracting it from the next decimal number, which ends in 0. Mathematically an can describe 9 -I- 7 = 6 mod 10) (2) The remainder 6 is then subtract from 10 to give the digit @de, control. The resulting control group includes the numbers 9, 7, and 4, which add to 0 (mod 10).

In these circuits an can apply the binary-serial coupling technique. Using this technique, pulse repetition rates of over one million pulses per second can be achieved. In these circuits, the position change registers can be constituted by delay lines, the logic functions can be executed with diodes, and suitable pulses can be obtained by means of electronic regenerators of impulses.

Claims (12)

CLAIM Installation for transmitting coded signals On telephone lines, comprising a circuit serving to correct a group of errors, this circuit comprising at least one Position change recorder, means for applying a series of digits to said Position change register, means for successively moving said digits to successive digit positions in the Position change register during successive time intervals, and control devices connected with at least two positions of digits, spaced from each other, of the Position change register to form the check digits, characterized in that it comprises a device for inserting each check digit in said series of digits. at a point remote from the digits, which are controlled by said check digit. SUB-CLAIMS 1. Transmission installation according to claim, characterized in that the checking devices comprise means for checking the equality of the digital information and for repeating the operation of checking the legality. 2. Transmission installation according to claim, characterized in that the circuit comprises an encryption device, a decryption device, the installation comprising a transmission line subjected to disturbing effects and connecting said encryption device and said decryption device, said decryption device comprising at least one Position change register, means for progressively moving the information received and the check digits through the Position change register of the encryption device, circuitry for checking the validity of at least two check operations performed in said encryption device and encompassing a common digit and for producing two corresponding output pulses, and means responsive to at least two of said output pulses for correcting the digits incorrect receipts. 3. Transmission installation according to sub-claim 2, characterized in that said deciphering device comprises an equality control Position change register and a group of equality control circuits connected with said equality control Position change recorder. 4. Transmission installation according to sub-claim 2, characterized in that it comprises means in the first encryption device. to transmit at least two digits @of information for each check digit that is transmitted. 5. Transmission installation according to sub-claim 2, characterized in that the deciphering device comprises means for indicating errors which exceed the ability of the deciphering device to correct the error, said correction circuit comprising means responsive to said output check signals for classifying errors as information errors or check errors, means for determining correctable errors, in which the error initially appears as a check digit . 6. Transmission installation according to sub-claim 2, characterized in that said deciphering device comprises an error detection circuit for indicating errors which exceed the capacity of the deciphering device to correct the errors, said circuit of detection comprising means for classifying the errors, and means for consecutively determining the correctable groups in each class of errors. 7. Transmission installation according to sub-claim 2, characterized in that said deciphering device comprises a check digit position change register and at least one position change register for applying the check digits. only to said check digit position change register, and an equality check circuit connected to a digit position of said check digit position change register and to at least two spaced digit positions, the other Position change register in the deciphering device. B. Transmission installation according to sub-claim 2, characterized by a First and a second group of equality control circuits, each of which comprises at least three input connections with different digit positions in said circuit. position change register, one of said connections being made with a same digit position, and means responsive to output signals from said groups of control circuits for correcting errors in the received information digits. 9. Transmission installation according to sub-claim 8, characterized in that the deciphering device comprises separate check and information digit position change registers. 10. Transmission installation according to sub-claim 8, characterized in that said deciphering device comprises a single position change register to which the information and control digits are applied. 11. Transmission installation according to sub-claim 2, characterized by means responsive to said groups of control signals to correct the erroneous received signals, and circuits sensitive to the groups of control signals developed in intervals times to indicate correctable group errors. 12. Transmission installation according to sub-claim 2, characterized in that the first deciphering device comprises an alarm circuit.