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ES2068105B1 - Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm. - Google Patents

Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm.

Info

Publication number
ES2068105B1
ES2068105B1 ES09202433A ES9202433A ES2068105B1 ES 2068105 B1 ES2068105 B1 ES 2068105B1 ES 09202433 A ES09202433 A ES 09202433A ES 9202433 A ES9202433 A ES 9202433A ES 2068105 B1 ES2068105 B1 ES 2068105B1
Authority
ES
Spain
Prior art keywords
error
detected
detection
atm cell
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
ES09202433A
Other languages
English (en)
Other versions
ES2068105A1 (es
Inventor
Gonzalez Jose Luis Merino
Cabello Carmen Maria Lequerica
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Priority to ES09202433A priority Critical patent/ES2068105B1/es
Priority to AU50620/93A priority patent/AU669746B2/en
Priority to AT93119020T priority patent/ATE259124T1/de
Priority to EP93119020A priority patent/EP0600380B1/en
Priority to DE1993633411 priority patent/DE69333411T2/de
Priority to CA002110207A priority patent/CA2110207A1/en
Priority to US08/158,609 priority patent/US5570377A/en
Priority to JP30068393A priority patent/JP3429037B2/ja
Publication of ES2068105A1 publication Critical patent/ES2068105A1/es
Application granted granted Critical
Publication of ES2068105B1 publication Critical patent/ES2068105B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0072—Error control for data other than payload data, e.g. control data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5647—Cell loss
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Error Detection And Correction (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

METODO Y DISPOSITIVO DE DETECCION Y CORRECCION DE ERRORES EN CABECERAS DE CELULAS ATM. DEL TIPO DE LOS QUE REALIZAN UNA CONVERSION SERLE A PARALELO (2) DE LA CADENA DE DATOS EN SERIE (1), OBTENIENDOSE UN FORMATO DE DATOS EN PARALELO DE N BITIOS CUYO REGIMEN DE TRABAJO ES N VECES MENOR QUE EL ORIGINAL. A PARTIR DE LOS DATOS DE ENTRADA EN PARALELO DE LA CABECERA DE CELULAS ATM, SE REALIZA LA GENERACION DE UNA PALABRA SINDROME (3) DE ACUERDO CON UNA RELACION DETERMINADA, QUE INDICA SI NO SE HA DETECTADO NINGUN ERROR, O SI SE HA DETECTADO MAS DE UN ERROR, O EL BITIO ERRONEO A CORREGIR CUANDO SE HA DETECTADO UN SOLO ERROR. LAS CABECERAS DE CELULAS ATM SON RETARDADAS (4) HASTA QUE LA PALABRA SINDROME ESTE COMPLETADA, REALIZANDOSE DESPUES EL PROCESO DE CORRECCION DE ERRORES (5), CUANDO PROCEDA, DE ACUERDO CON LA PALABRA SINDROME GENERADA. ADEMAS SE GENERA UNA INDICACION INDIVIDUAL AL EXTERIOR (7) DEL RESULTADO DEL PROCESO DE DETECCION Y POSIBLE CORRECCION REALIZADO. EL DISPOSITIVO IMPLEMENTA EL METODO DESCRITO.
ES09202433A 1992-11-30 1992-11-30 Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm. Expired - Fee Related ES2068105B1 (es)

Priority Applications (8)

Application Number Priority Date Filing Date Title
ES09202433A ES2068105B1 (es) 1992-11-30 1992-11-30 Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm.
AU50620/93A AU669746B2 (en) 1992-11-30 1993-11-12 Method and device for detection and correction of errors in ATM cell headers
EP93119020A EP0600380B1 (en) 1992-11-30 1993-11-25 Method and device for detection and correction of errors in ATM cell headers
DE1993633411 DE69333411T2 (de) 1992-11-30 1993-11-25 Verfahren und Einrichtung zur Feststellung und Korrektur von Fehlern im Kopffeld von ATM-Zellen
AT93119020T ATE259124T1 (de) 1992-11-30 1993-11-25 Verfahren und einrichtung zur feststellung und korrektur von fehlern im kopffeld von atm-zellen
CA002110207A CA2110207A1 (en) 1992-11-30 1993-11-29 Method and device for detection and correction of errors in atm cell headers
US08/158,609 US5570377A (en) 1992-11-30 1993-11-29 Method and device for detection and correction of errors in ATM cell headers
JP30068393A JP3429037B2 (ja) 1992-11-30 1993-11-30 Ａｔｍセルヘッダにおけるエラー検出および補正方法および装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES09202433A ES2068105B1 (es) 1992-11-30 1992-11-30 Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm.

Publications (2)

Publication Number Publication Date
ES2068105A1 ES2068105A1 (es) 1995-04-01
ES2068105B1 true ES2068105B1 (es) 1995-11-01

Family

ID=8278968

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09202433A Expired - Fee Related ES2068105B1 (es) 1992-11-30 1992-11-30 Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm.

Country Status (8)

Country Link
US (1) US5570377A (es)
EP (1) EP0600380B1 (es)
JP (1) JP3429037B2 (es)
AT (1) ATE259124T1 (es)
AU (1) AU669746B2 (es)
CA (1) CA2110207A1 (es)
DE (1) DE69333411T2 (es)
ES (1) ES2068105B1 (es)

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JP3454962B2 (ja) * 1995-03-23 2003-10-06 株式会社東芝 誤り訂正符号の符号器及び復号器
FR2735889B1 (fr) * 1995-06-22 1997-09-05 Sgs Thomson Microelectronics Circuit de calcul de syndrome
DE19626455A1 (de) * 1995-07-24 1997-01-30 Ascom Tech Ag Verfahren zur Integration von Zusatzdaten in digitalen Datenpaketen
US6728921B1 (en) 1996-05-31 2004-04-27 Nortel Networks Limited Cell based data transmission method
GB2313748B (en) 1996-05-31 2000-12-20 Northern Telecom Ltd Cell based data transmission method
JPH11196006A (ja) * 1997-12-26 1999-07-21 Nec Corp 並列処理シンドロ−ム計算回路及びリ−ド・ソロモン複合化回路
US5923681A (en) * 1998-02-24 1999-07-13 Tektronix, Inc. Parallel synchronous header correction machine for ATM
DE19916631C2 (de) * 1999-04-13 2001-02-08 Siemens Ag Verfahren und Vorrichtung zum Auffinden einer regelmäßig wiederkehrenden, vordefinierten Bitfolge in einem seriellen Datenstrom
FR2805694B1 (fr) * 2000-02-25 2003-06-20 Sagem Procede de transmission de signaux entre deux reseaux locaux
US6606726B1 (en) 2000-06-13 2003-08-12 Telefonaktiebolaget L M Ericsson (Publ) Optimization of acceptance of erroneous codewords and throughput
US6700827B2 (en) 2001-02-08 2004-03-02 Integrated Device Technology, Inc. Cam circuit with error correction
US6870749B1 (en) 2003-07-15 2005-03-22 Integrated Device Technology, Inc. Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors
US7193876B1 (en) 2003-07-15 2007-03-20 Kee Park Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors
US6987684B1 (en) 2003-07-15 2006-01-17 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein
US7304875B1 (en) 2003-12-17 2007-12-04 Integrated Device Technology. Inc. Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same
US8553441B1 (en) 2010-08-31 2013-10-08 Netlogic Microsystems, Inc. Ternary content addressable memory cell having two transistor pull-down stack
US8462532B1 (en) 2010-08-31 2013-06-11 Netlogic Microsystems, Inc. Fast quaternary content addressable memory cell
US8625320B1 (en) 2010-08-31 2014-01-07 Netlogic Microsystems, Inc. Quaternary content addressable memory cell having one transistor pull-down stack
US8582338B1 (en) 2010-08-31 2013-11-12 Netlogic Microsystems, Inc. Ternary content addressable memory cell having single transistor pull-down stack
US8773880B2 (en) 2011-06-23 2014-07-08 Netlogic Microsystems, Inc. Content addressable memory array having virtual ground nodes
US8837188B1 (en) 2011-06-23 2014-09-16 Netlogic Microsystems, Inc. Content addressable memory row having virtual ground and charge sharing
JP5982869B2 (ja) * 2012-02-28 2016-08-31 富士ゼロックス株式会社 送受信システム及びプログラム

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3656107A (en) * 1970-10-23 1972-04-11 Ibm Automatic double error detection and correction apparatus
US4416010A (en) * 1980-04-14 1983-11-15 Victor Company Of Japan, Ltd. Double error correcting system in digital signal reproducing apparatus
US4777635A (en) * 1986-08-08 1988-10-11 Data Systems Technology Corp. Reed-Solomon code encoder and syndrome generator circuit
JPH0213135A (ja) * 1988-06-30 1990-01-17 Sony Corp ディジタル信号伝送装置
JPH03235441A (ja) * 1990-02-09 1991-10-21 Hitachi Ltd セル同期回路
JP2816223B2 (ja) * 1990-03-02 1998-10-27 株式会社日立製作所 セル同期回路
US5119368A (en) * 1990-04-10 1992-06-02 At&T Bell Laboratories High-speed time-division switching system
IT1240298B (it) * 1990-04-13 1993-12-07 Industrie Face Stamdard Dispositivo elettronico per la correzione parallela di stringhe dati protette col rilevamento degli errori mediante codice ciclico
JP2764865B2 (ja) * 1990-08-20 1998-06-11 富士通株式会社 Ａｔｍ交換回路構成方式
JP3241716B2 (ja) * 1990-08-31 2001-12-25 株式会社東芝 Ａｔｍ交換方法
US5285446A (en) * 1990-11-27 1994-02-08 Nec Corporation Cell flow control unit and method for asynchronous transfer mode switching networks
CA2059396C (en) * 1991-01-16 1996-10-22 Hiroshi Yamashita Compact device for checking a header error in asynchronous transfer mode cells
JP2655547B2 (ja) * 1991-03-13 1997-09-24 富士通株式会社 Ｃｒｃ演算方法及びａｔｍ交換方式におけるｈｅｃ同期装置
JPH04334234A (ja) * 1991-05-10 1992-11-20 Nec Corp 多重処理形ａｔｍセル誤り訂正回路
ES2100269T3 (es) * 1992-07-14 1997-06-16 Alcatel Bell Nv Dispositivo de deteccion y correccion de error.

Also Published As

Publication number Publication date
DE69333411T2 (de) 2005-01-13
DE69333411D1 (de) 2004-03-11
EP0600380B1 (en) 2004-02-04
AU669746B2 (en) 1996-06-20
EP0600380A2 (en) 1994-06-08
EP0600380A3 (en) 1995-03-29
JPH077492A (ja) 1995-01-10
US5570377A (en) 1996-10-29
AU5062093A (en) 1994-06-09
JP3429037B2 (ja) 2003-07-22
CA2110207A1 (en) 1994-05-31
ES2068105A1 (es) 1995-04-01
ATE259124T1 (de) 2004-02-15

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20100528