EP3235006A1

EP3235006A1 - Hemt transistor

Info

Publication number: EP3235006A1
Application number: EP15821120.1A
Authority: EP
Inventors: Frédéric MORANCHO; Saleem HAMADY; Bilal BEYDOUN
Original assignee: Centre National de la Recherche Scientifique CNRS; Universite Libanaise
Current assignee: Centre National de la Recherche Scientifique CNRS; Universite Libanaise
Priority date: 2014-12-15
Filing date: 2015-12-15
Publication date: 2017-10-25
Also published as: FR3030114A1; US20180069090A1; FR3030114B1; WO2016097576A1; US10177239B2; JP2018503252A

Abstract

Semiconductor heterojunction structure, i.e. what is also referred to as a heterostructure, especially for a high electron mobility transistor (HEMT), comprising a substrate (4) and a stack of at least three buffer layers made of the same semiconductor of wide bandgap EG1 based on a nitride of column, namely an unintentionally doped first buffer layer (6), a second buffer layer (8) and an unintentionally doped third buffer layer (10), an unintentionally doped intermediate layer (11) and a barrier layer (12) that is placed on the intermediate layer (11), said barrier layer (12) being made of a semiconductor of wide bandgap EG2 based on a nitride of column III; the second buffer layer (8) has a constant p⁺-type dopant concentration through all or some of its thickness; and the third buffer layer (10) has a first unintentionally doped region (16) right through its thickness and at least one second region (18) adjacent said first region with an n⁺ doping surrounding the first region (16).

Description

TRANSISTOR HEMT

Technical area

The present invention relates generally to the techniques for producing high electron mobility transistors (or HEMT transistor, the English "High Electron Mobility Transistor"). It relates more particularly to a hetero structure from which such a transistor can be made.

The invention finds applications, in particular in the field of power electronic components used, for example, in devices for producing, converting and / or managing renewable energies such as wind or solar energy, but also in transport with low ecological impact.

Previous Art

Renewable energy sources, such as wind and solar energy, have for some years now become viable alternatives, adapted to cope with declining fossil energy resources and global warming. In addition, the development of means of transport with low environmental impact, such as the tramway, the train or the electric car, calls for the development of suitable electronic power components and more, especially of power switches. In particular, improvements to semiconductor type components in the form of integrated circuits, such as power transistors, relate to the intrinsic characteristics of these components to increase their operating voltage and / or their maximum switching frequency. They also aim to offer total integration solutions allowing mass manufacturing to reduce production costs.

To date, only silicon-based power components (Si) such as, for example, metal oxide semiconductor (MOS) transistors or insulated gate bipolar transistor (IGBT) transistors perform this type of function. However, the physical properties inherent in the use of Si make the technological evolutions of this type of component difficult. In recent years, many research works have found alternative solutions through the use of wide bandgap materials, allowing the realization of new power components such as high electron mobility transistors, also called HEMT transistors .

Silicon Carbide (SiC) and Gallium Nitride (GaN) have emerged as two of the most promising materials thanks to a high critical electric field and a wide range of temperature functions. Despite remarkable results, however, SiC-based power components find it difficult to penetrate the mass markets due to the limited size of SiC wafers (100 to 150 mm maximum diameter at present). In addition, problems remain to date for this type of components in terms of fault control, but also the reproducibility of manufacturing processes. GaN seems to be an alternative to SiC very interesting for the design of power components. In fact, GaN is a semiconductor material that is more efficient than Si or SiC in terms of compromise pass resistance / voltage withstand. This ratio, otherwise known as the merit factor, characterizes the static performance of a power switch.

In Figure 1 is shown an example of heterojunction electronic structure used in a HEMT transistor. This heterojunction electronic structure comprises several layers based on GaN each having intrinsic characteristics under control, and stacked one above the other, with:

a substrate 1,

- Over which comes a first layer 3, called buffer layer, made of a material M1 characterized by its bandgap or "gap"Eg1; and, a second layer 5, called barrier layer, coming over the first layer 3 and composed of a material M2 characterized by its bandgap width or "gap" Eg2, where Eg1 is smaller than Eg2.

Many research studies concern the control and the improvement of a two-dimensional gas confinement of electrons at the AIGaN / GaN hetero-structure by studying different solutions. These solutions may be at the level of the deposition of the GaN layer, in order to modify certain intrinsic characteristics of the hetero-structure thus making it possible to obtain HEMT transistors with relatively high switching speeds as well as relatively low losses. They may also consist of creating new MOS-HEMT structures.

Thus, for example, a MOS-HEMT transistor structure is proposed in the IEEE publication of 2008, "Enhanced device performance of AIGaN / GaN HEMTs using thermal oxidation of electron-beam deposited aluminum for gas oxide" by C. Hongwei et al. This publication shows the improved performance of a conventional HEMT transistor structure that can be achieved by adding an oxidation layer at the gate electrode. The MOS-HEMT structure thus obtained has lower leakage currents and a larger drain current range than a conventional HEMT structure with, however, the need to have a threshold voltage of less than zero volts to set the transistor in a blocked state.

Now, another very important research axis at the present time concerns the rest state of this type of structure, that is to say the state of the transistor when no voltage is applied to the electrode. gate of the HEMT transistor. Indeed, in many power applications, the transistor used as a switch must be in the open state by default (also called "normally OFF" function). Indeed, this state is essential for reasons of safety and energy saving, as for example in automotive or rail transport applications.

Several GaN-based structures have recently been proposed in order to satisfy the "normally OFF" functionality of a HEMT transistor. Works from the team of C. Hongwei et al, showed the possibility of modifying the threshold voltage to obtain a "normally OFF" HEMT transistor by using a Fluoride ion treatment in a publication called "Self-aligned enhancement-mode AIGaN / GaN HEMTs Using 25keV Fluorite Ion Implantation "published in 2010 in the journal IEEE. To do this, a Fluorine doped zone is inserted into the barrier layer of the HEMT transistor structure AIGaN / GaN and this latter is placed below the gate electrode, the Fluor ion doses being determined to have an sufficient offset of the voltage Vgs of the transistor. Patent Application US2007 / 0278518 entitled "Enhancement Mode III-

N Devices and Circuits' further proposes a further development of the method of manufacturing a HEMT transistor structure. According to this evolution, a Fluorine plasma treatment method is used on the barrier layer of the hetero-structure. This method makes it possible, with a relatively simple process (use of a fluorine plasma), to modify the intrinsic characteristics of the hetero-structure in order to obtain an "normally OFF" transistor.

The evolution of design and manufacturing techniques such as those presented above makes it possible to obtain "normally OFF" HEMT transistors that can only address certain energy conversion markets because of relatively large leak currents.

The patent application US2013 / 0256685 entitled "Compound semiconductor device and method for manufacturing the same" proposes a structure based on HEMT transistor in which a two-dimensional gas of electrons is generated, and an electrode is formed on the transistor-based structure. HEMT. The structure further includes a P-type semiconductor layer below an area where the two-dimensional electron gas is generated. To control an electron density of the two-dimensional gas, the P-type semiconductor layer has a portion containing a larger amount of ionized acceptors than other portions of the P-type semiconductor layer. Summary of the Invention

The object of the invention is to overcome the disadvantages of the aforementioned prior art, and more particularly to allow the realization of an HEMT transistor with a low leakage current at the gate, a high switching speed and a higher threshold voltage. at 0 V to ensure "normally OFF" functionality.

For this purpose, a first aspect of the invention proposes a heterojunction structure, in particular for a high electron mobility transistor (HEMT) comprising: a planar substrate,

a stack of buffer layers with at least three layers made of a same wide-band III1 wide bandgap semiconductor material of which:

^■ a first non-intentionally doped buffer layer is arranged on the substrate,

^■ a second buffer layer disposed on the first layer and having a thickness determined according to a direction orthogonal to the substrate plane,

^■ a third non-intentionally doped buffer layer disposed on the second buffer layer and having a predetermined thickness in a direction orthogonal to the substrate plane,

an unintentionally doped intermediate layer disposed on the third buffer layer made of a tubular III nitride wide bandgap semiconductor material Eg1 identical to that of the buffer layer stack,

a barrier layer disposed on the intermediate layer disposed, said barrier layer being made of a column III nitride based wide bandgap semiconductor material Eg2,

in which : the second buffer layer has substantially constant P + type doping over all or part of its thickness, and the third buffer layer comprises a first region which is unintentionally doped throughout its thickness, as well as at least one second region adjacent to said first region and which is doped with N + type doping. Thus, thanks to the presence of the two regions, the effect of the second P + doped buffer layer is attenuated on a two-dimensional electron gas.

In an exemplary embodiment, the second region adjacent to the first region of the third buffer layer has a constant doping throughout the thickness of said third buffer layer thus controlling the formation of 2DEG bidimensional gas.

In a variant, the second region adjacent to the first region of the third buffer layer has a Gaussian type doping according to the thickness of said third buffer layer.

According to embodiments of the invention, a distance in a direction orthogonal to the plane of the substrate, between the second buffer layer and the interface between the intermediate layer and the barrier layer is less than 20 nm, which makes it possible to control and to locally elevate the Fermi level and the conduction band of the heterojunction.

According to various embodiments of the invention, the nitride semiconductor material of the column III of which are formed the first buffer layer, the second buffer layer, the third buffer layer, the layer disposed on the third buffer layer and the layer barrier comprises GaN.

N + type doping may be used to dopate the region adjacent to the first region of said third buffer layer and the dopant is preferably silicon.

Advantageously, to overcome this problem but also the possible problems of dislocation, in one embodiment of the invention a transition layer is interposed between the substrate and the first buffer layer.

A second aspect of the invention relates to a HEMT type transistor made from a hetero-structure as described above. The transistor comprises a surface gate electrode determined in a first plane parallel to the plane of the substrate, a drain electrode and a source electrode disposed in a second plane above the barrier layer of the heterojunction structure. The first and second shots can be confused or staggered. In an exemplary embodiment, the first region of the third buffer layer of the heterojunctional structure is disposed beneath the gate electrode, and has a surface in a plane parallel to the plane of the substrate that is less than or equal to said surface of the gate electrode.

In embodiments, such a transistor may have an oxide-based insulating layer on the barrier layer below the gate electrode for controlling leakage currents.

For example, the insulating layer has a surface in a plane parallel to the plane of the substrate identical to the surface of the gate electrode.

According to a third aspect of the invention, there is provided a semiconductor product comprising at least one transistor according to the second aspect. This may be, for example, a power switch or any other power component such as a power voltage regulator, for example.

According to a fourth aspect, the invention relates to a method of manufacturing such a hetero-structure which comprises:

the preparation of a planar substrate,

the successive depositions on the substrate of a stack of buffer layers made of the same Ni1-based wideband forbidden semiconductor material of column III, of which: ^■ depositing a first buffer layer on the substrate, said semiconductor material which is formed said first buffer layer being not intentionally doped,

^■ depositing a second buffer layer on the first buffer layer having a thickness determined according to a direction orthogonal to the plane of the substrate and doping said second buffer layer being formed using dopant of the P + type throughout its thickness ;

^■ depositing a third buffer layer on the second buffer layer and having a thickness determined according to a direction orthogonal to the plane of the substrate, said semiconductor material which is formed said third buffer layer being not intentionally doped,

doping with N + doping elements of at least one region of the third buffer layer adjacent to a first region of said third buffer layer which is unintentionally doped throughout its thickness,

depositing an unintentionally doped intermediate layer made of a tubular III nitride wide bandgap semiconductor material Eg1 identical to that of the stack of buffer layers,

depositing a barrier layer of a nitride-based wide bandgap semiconductor material of column III on the third buffer layer.

Note that, preferably, the intermediate layer and the barrier layer cover all of the buffer layers, and therefore the electrodes of the transistor mounted above will not be in direct contact with the P + doped layer.

Advantageously, this manufacturing method is simple and requires few additional steps compared to the manufacture of a conventional hetero-structure, for example for the production of a conventional HEMT transistor.

In order to optimize the performance of the structure, it is proposed in a variant embodiment of the method that the successive deposits of the stack of layers are made without interruption of an epitaxial process.

Brief Description of Drawings

Other features and advantages of the invention will become apparent on reading the description which follows. This is purely illustrative and should be read in conjunction with the accompanying drawings in which:

- Figure 1, already analyzed, is a sectional view of a heterojunction structure according to the prior art;

- Figure 2 is a sectional view of an example of stacking layers forming a heterojunction structure according to one embodiment of the invention;

- Figures 3 to 14 are sectional views illustrating the main technological steps for the realization of the heterojunction structure of Figure 2;

FIG. 15 is a sectional view of an HEMT transistor according to one embodiment;

Figure 16 is a top view and Figures 17 and 18 are side views showing the position of the gate electrode of the transistor relative to a first unintentionally doped region of an underlying buffer layer;

FIG. 19 is a graph showing the threshold voltage and the current of the transistor of FIG. 15 as a function of its gate-source voltage;

- Figure 20 is a sectional view of an example HEMT transistor according to another embodiment. Detailed description of embodiments

As a preliminary point, it should be noted that all the figures illustrating cross-sectional views of the heterojunction structure as well as all the figures illustrating stackings of the layers but also those representing process steps of manufacturing the heterojunction structure and the transistor HEMT, are not to scale. The different thicknesses are not represented in proportion to the reality. For the sake of simplification, in the description which follows and in the figures, the elements common to all the structures bear the same references.

The invention will be more particularly described in a nonlimiting example of application to a heterojunction structure 2 for HEMT transistors. The heterojunction structure example 2 described below is based on nitrides of elements of column III of the periodic table of the elements, also called Mendeleev table. It relates more particularly to a heterojunction structure 2 based on nitrided materials to form an AIGaN / GaN type interface. Advantageously, the GaN is a semiconductor material with a forbidden bandwidth Eg1 smaller than a bandgap width Eg2 of the AIGaN material.

It is obvious, however, that the invention is not limited to these examples. For example, a heterojunction structure that uses the properties of another type of semiconductor material for creating an interface between GaAIAs-type large gap material and a GaAs-type small gap material can be used. performed.

FIG. 2 shows a first example of stack of buffer layers constituting structure 2 with heterojunction. It comprises in ascending order of stacking: a plane substrate 4,

^■ a first non-intentionally doped buffer layer 6 is arranged on the substrate 4,

^■ a second buffer layer 8 disposed on the first layer 6 and having a thickness determined according to a direction orthogonal to the substrate plane,

^■ a third 10 Non intentionally doped buffer layer disposed on the second buffer layer 8 and having a thickness determined according to a direction orthogonal to the substrate plane, an unintentionally doped intermediate layer 1 1 disposed on the third buffer layer 10 made of a wide-band semiconductor forbidden semiconductor material Eg1 of column III identical to that of the stack of buffer layers, - a barrier layer 12 arranged on the intermediate layer 11, said barrier layer 12 being made of a nitride-based broadband semiconductor material Eg2 of column III, in which:

the second buffer layer 8 has a substantially constant P + type doping over all or part of its thickness, and

the third buffer layer 10 comprises a first region 16 which is unintentionally doped throughout its thickness, and at least one second region 18 adjacent to said first region 16 and which is doped with N + type doping. It is noted that buffer layers 6, 8, 10, the intermediate layer

1 1 and the barrier layer 12 extend continuously in stacking over the entire surface of the structure; the second 8 covering continuously and entirely the first 6; the third 10 covering continuously and entirely the second 8; the intermediate layer 1 1 covering continuously and entirely the third 10, the barrier layer 12 continuously and completely covering the intermediate layer January 1.

The P + type doping mentioned herein corresponds to a density of between 10 ¹⁷ and ¹⁸ cm ^-3 , preferably between 10 ¹⁸ and ¹⁹ cm ^-3 .

The manufacturing method in an exemplary embodiment of such a hetero-structure comprises:

the preparation of a plane substrate 4,

the successive depositions on the substrate 4 of a stack of buffer layers made of the same Ni1-based wideband forbidden semiconductor material of column III of which:

Depositing a first buffer layer 6 on the substrate 4, said semiconductor material which is made of said first buffer layer being unintentionally doped, ^■ depositing a second buffer layer 8 of the first buffer layer 6 having a thickness determined according to a direction orthogonal to the plane of the substrate and doping said second buffer layer being formed with elements P type dopants on + all its thickness,

^■ depositing a third buffer layer 10 of the second buffer layer 8 and having a thickness determined according to a direction orthogonal to the plane of the substrate, said semiconductor material which is formed said third buffer layer being not intentionally doped,

doping with N + doping elements of at least one region 18 of the third buffer layer 10 adjacent to a first region 16 of said third buffer layer which is unintentionally doped throughout its thickness; deposition of an unintentionally doped intermediate layer

1 1 in a wide band gap nitride semiconductor material Eg1 of column III identical to that of the stack of buffer layers,

depositing a barrier layer 12 of a nitride-based wide bandgap semiconductor material of column III on the layer 11.

The performance of the heterojunction structure 2 having a stack of layers depends inter alia on the crystalline quality of the epitaxial material used. GaN is an epitaxial material which makes it possible to limit partial disagreements of mesh with the materials forming the hetero-structure. To do this, the GaN is obtained by crystallographic growth from the substrate 4.

Several types of materials can be used to make the substrate 4, as epitaxial substrate for GaN. In embodiments, silicon carbide (SiC) is used, for example, which gives a mesh mismatch of the order of only 3.4%, or Sapphire (AI203). Other examples of substrates, such as substrates based on GaAs, ZnO or so-called "free standing" substrates may also be used. Alternatively, silicon (Si) may also be used. Indeed, the Si is a material that is commonly used for the manufacture of electronic components in general and HEMT transistors in particular. The massive and old use of Si in electronic components makes it a material whose intrinsic characteristics are very well controlled with above all a very low cost price despite a higher mesh size than SiC.

Depending on the nature of the substrate, for example SiC or Si, or the crystalline orientation of the Si substrate, the quality of the GaN layer obtained by epitaxial growth can vary, which is likely to modify the performance of the structure 2 heterojunction. Therefore, in one exemplary embodiment, the heterojunction structure 2 can be carried out on a substrate Si of crystalline orientation determined, for example that noted (1 1 1) in the literature. It may sometimes be necessary to deposit a transition layer 14 as illustrated in FIG. 3, more commonly known as a nucleation layer, in order to overcome any dislocation problems. This transition layer 14 can also reduce the risk of tearing between the layers. These tears are generally due to the difference in mechanical stresses internal to the interface between the layers. Thus, for example and as illustrated in Figure 3, the transition layer 14 may be disposed between the substrate 4 and the first buffer layer 6 of the stack of buffer layers.

In a variant (not shown in the figures), several transition layers can be deposited between two layers.

In the case of several nucleation layers (or transition layers), these may be deposited, for example in several successive deposition operations, on another layer of nitride compounds by epitaxy. Advantageously, this makes it possible to improve and / or control the quality of the first buffer layer 6 in order to avoid, for example, tearing off or the creation of gaps that could generate uncontrolled leakage currents. It will also be noted that the substrate Si may be of crystalline orientation other than (001) or even (100), and that, if necessary, intermediate layers may be used, as previously stated, in order to obtain a film of GaN in concordance with the specifications of the application. It should be noted that the substrates described above are mentioned here only by way of example and are not limiting of the invention.

The growth of the various layers of structure 2 heterojunction can be achieved using microelectronics techniques, such as for example a technique by vapor phase epitaxy in reactors of HVPE type (English "Hybrid Vapor Phase Epitaxy "), From certain gaseous mixtures of type for example GaCl3 / NH3. This technique makes it possible, thanks to high growth rates, to obtain relatively large thicknesses and excellent qualities.

Other deposition techniques may also be used, such as, for example, the MBE ("Molecular Beam Epitaxy") method, but also the MOCVD (MetalOrganic Chemical Vapor Deposition) method. These methods are given by way of example and have no limiting character as to the techniques for designing such nitride layers that can be used for the design of HEMT transistors. In embodiments and as illustrated in FIG. 4, the growth of the first buffer layer 6 of the stack of layers can be obtained by the MOCVD method, for example by using elements of column III, in particular by routing in a reaction chamber. It may be, for example, a mixture of dihydrogen as well as a chemical precursor. The GaN is thus formed on the surface of the transition layer 14 to form the first buffer layer 6.

Advantageously, the first buffer layer 6 is unintentionally doped. For those skilled in the art, such a layer, that is to say a layer unintentionally doped GaN is also called UID-GaN (unintentionally doped), GaN-NID (from French). "GaN Not Intentionally Doped"), or i-GaN ("intrinsic GaN" or "intrinsic GaN"). Such an epitaxial process makes it possible to obtain a growth of the order of a few μιτι / h. Thus, it is possible to obtain a thickness of the order of 1 to 3 μηι for the first buffer layer 6 in only a few hours.

The second buffer layer 8 (FIG. 5) is then deposited on the first buffer layer 6. Advantageously, the second buffer layer 8 is produced without the epitaxial process being interrupted, that is to say without the substrate 4 removed from the epitaxy chamber or undergo other technological steps. Thus, the quality of the interfaces between the different layers is substantially improved. In addition, thanks to the successive deposition of the stack of layers, the process time is decreased, which substantially reduces the production costs of the structure 2 to heterojunction.

The growth process of the second buffer layer 8 by epitaxy relies substantially on the same method as that described in the preceding paragraphs for the first buffer layer 6. In order to boost the second buffer layer 8, a P-type doping element is used during the growth process of the latter. The P-type doping element preferentially belongs to the elements of column II-A such as, for example, magnesium (Mg). However, other dopants of this same column of the Mendeleev periodic table can also be used, such as for example Beryllium.

Advantageously, the doses of doping elements during the growth process of the second buffer layer 8 can be modulated to obtain a layer with a determined doping corresponding to a precise specification of the application.

The second buffer layer 8 has a minimum thickness of 400 nm in order to obtain threshold voltages shifted to positive values.

In embodiments, the heterojunction structure 2 further comprises a third GaN buffer layer 10 as illustrated in FIG. 6. The material of this third buffer layer 10 as well as the intrinsic characteristics are preferentially identical to the characteristics of the first layer. buffer 6 of the stack of layers. Preferably, the third buffer layer 10 is unintentionally doped UID-GaN. The method for obtaining this layer is identical to that presented above for producing the first buffer layer 6. The third buffer layer 10 also has a thickness of the order of 10 nm for shifting the threshold voltage of the HEMT to positive values. .

Advantageously, thanks to the manufacturing process presented above, the heterojunction structure 2 has a lower risk of tearing the films constituting the different layers. In addition, thanks to the successive deposits of the stack of layers, it is possible to control the amount of impurities in the different layers while reducing the number of technological steps. Thus, the cost of manufacturing such a heterojunction structure 2 is substantially reduced compared to the structures of the prior art. In order to control the carrier density in the two-dimensional electron gas, in a preferred embodiment it is delimited, in the third buffer layer 10, a first region 16 and at least one region adjacent to this region 16, such as adjacent regions 18 located on either side of the region 16 in the layer view of FIG. 7. It will be noted that, seen from above, the two regions 18 of FIG. 7 can be only one and even area 18 surrounding area 16.

To obtain these regions, it is firstly used as illustrated in FIG. 8, a masking or protective layer 20 which makes it possible to precisely delimit the first region 16. This mask 20 may be made for example with a photosensitive polymer allowing Using conventional photolithography techniques, to delimit the first region 16. This method of delimitation using a polymer is well known to those skilled in the art it will not be more detailed here.

Once the first region 16 is defined and the mask 20 is adapted to protect the third buffer layer 10, an ion implantation process is performed on the entire surface of the third buffer layer 10 which is not protected by the mask 20. Preferably, it is used an N-type dopant such as Si.

Localized implantation or otherwise called localized doping of a GaN layer requires relatively high dopant energies. Indeed, to penetrate the dopants in depths of a few nm in the GaN layer, it is necessary to use energies of the order of a few tens or even hundreds of keV. Such energies are necessary because of a relatively high GaN atomic density compared for example with that of silicon. Ion implantation processes are now well known, controlled and therefore will not be presented here.

In order to finalize the implantation process, an annealing is performed so that the doping species are positioned in substitutional sites (activation). Annealing is also used so that the GaN recrystallizes following the damage caused by the implantation. For example, the annealing temperature is of the order of 1000 ° C.

Advantageously, this implantation step makes it possible to cancel the influence of the presence of the second P-doped buffer layer 8 on the two-dimensional electron gas at the two regions 18. In one exemplary embodiment, the N + type doping in the third buffer layer 10 is of Gaussian form as schematically illustrated in Figure 9a.

The dimensions of the first region 16, as well as the thickness of the third buffer layer 10, play an important role in the properties of the heterostructure. Thus, it is preferable to delimit the implantation area precisely. It should be noted that materials which can be used to create the masking layer 20 have been given by way of example only as well as the doping mode of the two regions 18. Moreover, it is understood that the entirety of the various stages of the technological process such as, for example, photosensitive resin deposition phases, photolithography steps and cleaning steps required for such a process have not been cited so as not to burden the description. In a variant of the invention, the N + type doping in the third buffer layer 10 allows the latter to propagate in the P doped zone of the second buffer layer 8 as illustrated schematically in FIG. 9b. Thus, the second buffer layer 8 may have a doping profile which is not constant over its entire thickness.

With reference to FIG. 10, an unintentionally doped intermediate layer 11 is then deposited on the third buffer layer 10. The material constituting the intermediate layer 11 may be formed of a wide bandgap semiconductor material Eg1 based on nitride column III identical to that of the stack of buffer layers. Preferably, the intermediate layer 1 1 is unintentionally doped UID-GaN. The method for obtaining this layer is identical to that presented above for producing the first buffer layer 6. The intermediate layer 1 1 further has a thickness between 10 and 30 nm, preferably of the order of 10 nm to shift the voltage threshold of the HEMT to positive values.

With reference to FIG. 10, a barrier layer 12 is then deposited on the unintentionally doped intermediate layer 11. The material constituting the barrier layer 12 may be formed of a semiconductor material having a bandwidth Eg 2. In the example considered here, this layer may be composed of AIGaN, such as AIGa (1-x) N, where x is the mole fraction and is between 0 and 1, with a thickness of the barrier layer 12 less than 1 μιτι.

In one embodiment not illustrated in the figures, the barrier layer 12 may be composed of several layers with respective controlled characteristics, such as, for example, a doped layer, called a donor layer providing electrons involved in the formation of two-dimensional gas. electron.

The heterojunction structure 2 which has been presented above allows an improvement, for example, in controlling the threshold voltages of the HEMT transistors in order to obtain "normally OFF" transistors. In addition, such a structure makes it possible to obtain a transistor with improved reliability. In an alternative embodiment, the third buffer layer 10 is doped with an N-type dopant element during the growth process of the latter. The N-type doping element may be Si. To delimit the first region 16 (FIG. 11), the third buffer layer 10 is locally etched preferentially with the aid of, for example, a dry etching solution.

An unintentionally doped GaN layer 10.1 is then made in the first region 16 (Figure 12). Thus, the presence of the second P + doped layer 8 under the part 10.1 of the third buffer layer 10 will make it possible to influence the 2DEG gas. Advantageously, this method makes it possible to reduce the charge defects in the volume of the third buffer layer 10.

In another variant illustrated in FIG. 13, the third N + doped buffer layer 10 is produced by a so-called "lift" method of deposition for defining the first region 16 without etching of the third buffer layer 10. the GaN-NID layer 10.1 is performed (Figure 14).

Advantageously, the first buffer layer 6, layer 1 1 and the first region 16 may have a slight N-doping (10 ¹⁶ to 10 ¹⁷ cm ^"3) much lower than the N + doping (October ¹⁹ to October ²⁰ ^{cm" 3)} of the region 18. The slight doping N could advantageously be a little below, namely in density / concentration between 10 ¹⁵ and 10 ¹⁶ cm ^-3 .

It should be noted that the term 'unintentionally doped' actually covers cases where there is light doping, such as the slight N doping mentioned above.

In an exemplary embodiment of an HEMT transistor, it comprises as shown in FIG. 15:

a plane substrate 4,

a stack of buffer layers with at least three layers made of a same wide-band III1 wide bandgap semiconductor material of which: ^■ a first non-intentionally doped buffer layer 6 is arranged on the substrate 4,

^■ a third 10 Non intentionally doped buffer layer disposed on the second buffer layer 8 and having a thickness determined according to a direction orthogonal to the substrate plane,

an unintentionally doped intermediate layer 1 1 disposed on the third buffer layer 10 made of a tubular III nitride wide bandgap semiconductor material Eg1 identical to that of the stack of buffer layers,

a barrier layer 12 disposed on the intermediate layer 1 1, said barrier layer 12 being made of a Ni 2 semiconductor wide bandgap semiconductor material of column III,

source (S), drain (D) and gate (G) electrodes.

It should be noted that the second P + doped buffer layer 8 is not connected to any transistor electrode, neither the source, nor the drain, nor the gate, whereas this second layer preferably extends over the entire surface of the transistor. In other words, this second P + doped buffer layer 8 is floating.

In addition, it is noted that the gate electrode G is located just above the first region 16 with similar dimensions.

The manufacturing method in an embodiment of a transistor

(HEMT) using such a hetero-structure comprises:

the preparation of a plane substrate 4,

the successive deposits on the substrate 4 of a stack of buffer layers made of the same nitride-based semiconductor material of column III, of which:

^■ depositing a first buffer layer 6 on the substrate 4, said semiconductor material which is formed said first buffer layer being not intentionally doped, ^■ depositing a second buffer layer 8 of the first buffer layer 6 having a thickness determined according to a direction orthogonal to the plane of the substrate and doping said second buffer layer being formed with elements P type dopants on + all its thickness;

1 1, made of a tubular III nitride-based wide bandgap semiconductor material Eg1 identical to that of the buffer layer stack, on the third buffer layer 10,

depositing a barrier layer 12 of a nitride-based wide bandgap semiconductor material of column III on the intermediate layer 11,

the creation of the gate (G), drain (D) and source (S) electrodes using one or more layers of electrically conductive materials.

It is noted that all the intermediate steps related to such a process as the photolithography, cleaning steps, as well as for example the photosensitive resin deposition steps are not described in detail here in order not to burden the present description.

Drain D and Source S electrodes are so-called "ohmic" contacts thus making contacts metal / semiconductor low resistance and the gate electrode G is a metal contact / semiconductor said "Schottky". The method of manufacturing such electrodes being known to those skilled in the art, it will not be detailed in the description. The metals used to make these contact resumptions of the HEMT transistor described in the invention can be of different types, depending on the characteristics of the desired contacts.

The electrodes may be composed of a single layer of metal, for example Ti, Al or other metals, or even bilayer or tri-metallic layer.

These metals can be deposited by the traditional methods of depositing metals used in microelectronics such as for example by the Lift-Off method or the LIGA method (Lithography GAIvanic). Said electrodes may also be made of other materials whose electrical properties have been previously modified to suit the desired contact resistance.

As has already been presented in the foregoing, the invention makes it possible to obtain a HEMT transistor with a zero or positive threshold voltage in order to obtain a "normally OFF" HEMT transistor. To do this, in an exemplary embodiment of the method, there is created a first region 16 unintentionally doped allowing the P + doped layer placed under this region to influence the electron gas 2DEG. The first region 16 is positioned under the gate electrode (G) of the transistor and is, according to embodiments, 10 nm thick and has a width of 1 μιτι. These parameters make it possible to control the threshold voltage of the HEMT transistor.

In order not to deplete the conduction channel in a region not controlled by the gate voltage, the first region 16 is characterized by its length Lo16 and its width La16 in a plane parallel to that of the substrate is preferably smaller or equal in size to the dimensions of the gate electrode G in a plane parallel to the plane of the substrate.

Referring to Figure 16, then the following relationships:

Lo16 <LoG, (V

La16 <LaG. (2) or

Law 6 is the length of the first region 16,

La16 is the width of the first region 16,

LoG is the length of the gate electrode (G), and LaG is the width of the gate electrode (G).

These dimensions being considered in a plane parallel to the plane of the substrate.

In addition, in order not to incur blockage of the gate current, the placement of the first region 16 with respect to the gate electrode G is important. To do this, the placement of the first region 16 with respect to the gate electrode G must be (FIG. 17 and FIG. 18):

[B \ = 0; B2 = o] _{LoZCP = LoG} . _{LaZCP = LaG} , (3) where:

[Bl ≤ 0; B2≤] _{LoZCP <LoG LaZCP <LaG} . (4)

With:

B1 = p1 -p2, (5) B2 = p3-p4. (6) where:

p1 is the positioning of the gate electrode (G) on the x axis, p2 is the positioning of the first region 16 on the x axis, p3 is the positioning of the gate electrode (G) on the x axis z axis, p4 is the positioning of the first region 16 on the z axis, B1 is the distance between the gate electrode (G) and the first region 16 along the x axis

B2 is the distance between the gate electrode (G) and the first region 16 along the z axis,

Law 6 is the length of the first region 16,

La16 is the width of the first region 16,

LoG is the length of the gate electrode (G), and,

LaG is the width of the gate electrode (G).

The presence of the first unintentionally doped region 16 placed on the second P + doped buffer layer 8 makes it possible to increase the difference in the Fermi level and, as a result, the conduction band of the AIGaN / GaN heterojunction. According to another exemplary embodiment, the invention proposes to control the threshold voltage of the transistor by varying the distance between the second buffer layer 8 (P + doped) and the AIGaN / GaN interface, that is to say between the layer 1 1 and the barrier layer 12. Indeed, the reduction or increase in the distance between the second buffer layer 8 and the barrier layer 12 makes it possible to modulate the difference between the Fermi level and the conduction band and therefore to modulate the threshold voltage of the transistor.

The graph of FIG. 19 compares the threshold voltage of a transistor according to an exemplary embodiment of the invention with the threshold voltage of a conventional "normally ON" HEMT having the same physical and geometrical parameters with the exception of the first region 16. For this structure which is shown to us as an example, the parameters of the structure are:

distance between the top of the layer 8 and the interface between the layer 1 1 and the barrier layer 12 = 10 nm, - lateral opening (width) = 1 μιη

thickness of the layer 8 = 500 nm.

These results of simulations show that, unlike the conventional HEMT transistor, the threshold voltage of the HEMT transistor is positive, in particular by adjusting the distance between the second buffer layer 8 and the interface between the intermediate layer 11 and the barrier layer 12. However, the leakage currents of such a structure remain relatively high due to the presence of a Schottky contact between the gate electrode G and the barrier layer 12.

In order to overcome these drawbacks, an oxide layer is integrated in another embodiment between the gate electrode G and the Al (1 - x) GaN layer. This further comprises as shown in FIG. 20:

a plane substrate 4,

source electrodes S, drain D arranged on the barrier layer 12,

an electrically insulating layer 24 of thermal oxide type and a gate electrode G disposed on the electrically insulating layer 24.

Those skilled in the art will appreciate that techniques that can be used for deposition of the insulating layer have been described above.

The presence of this electrically insulating layer 24 thus makes it possible to obtain a MOS contact for (Metal / Oxide / Semiconductor) between the gate contact G and the barrier layer 12.

The oxide layer 24 may be obtained by thermal oxidation using, for example, a PECVD (Plasma Enhanced Chemical Vapor Deposition) type oxidation furnace which makes it possible to obtain layers of a few nanometers to a micrometer of thickness, for example.

The presence of the oxide layer and the removal of the Schottky contact make it possible to reduce the leakage current of the order, for example, by factor 20, thus making it possible to greatly improve the performance of the HEMT transistor.

The threshold voltage obtained as a function of the parameters mentioned above makes it possible to obtain a HEMT transistor with a threshold voltage, for example of 4V. This positive threshold voltage thus makes it possible to obtain, according to the different embodiments presented, a HEMT transistor which respects the "normally OFF" functionality. New fields of application are possible thanks to such a component. Indeed, this high threshold voltage makes this type of component insensitive to external disturbances such as noise on the gate voltage, including electromagnetic noise.

The above description has been given for illustrative purposes only and is not limiting of the scope of the invention. Any technically feasible variant embodiment may be preferred to the embodiments described. For example, the GaN material used in the description may be replaced by GaAs. The use of such a material therefore implies that the type of dopant and the doses that will be used as well as the dimensions and the positioning of the layer 8 will be chosen so that the overall behavior of the HEMT transistor using a GaAs material corresponds to the transistor described in the invention.

Similarly, the technological process steps described in the invention are given for illustrative purposes and are not limited to the examples given here.

Finally, it is understood that the various improvements described can be used separately or in combination, depending on the qualities and performance sought for the HEMT transistor made with this structure.

The present invention is not limited to the embodiments presented. Other variants and embodiments may be deduced and implemented by the person skilled in the art upon reading the present description and the appended figures. The reference signs can not be understood as limiting the scope of the invention or the scope of the description. In the above description, it is assumed that when an element such as a layer, region or substrate is referred to as being "above" or "on" another element, said element may be directly on the other element, or intermediate elements may be present.

It is also assumed that the terms first, second, third, etc. can be used here to describe different elements, components, regions, layers and / or sections. These elements, regions, layers and / or sections should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or section from another region, layer, or section. Thus, a first element, region, layer, or section described above could be referred to as the second element, region, layer, or section without departing from the teachings of inventive concepts. In addition, the relative positioning terms, such as "under", "below", "below", "above", "above", etc., have been used here to facilitate description and to describe positioning. of one element with respect to another element as illustrated in the figures.

It will be understood that the relative positioning terms are intended to cover different orientations of the device according to the invention during use or operation in addition to the orientation shown in the figures. For example, if the device according to the invention is returned, the elements described as "below" or "under" other elements would then be oriented "above" other elements. Thus, the term "below" may encompass both an "above" and "below" orientation. The device may also be otherwise oriented (90 degree rotation or other orientations) and the relative positioning terms used herein will be interpreted accordingly.

Claims

1. A heterojunction structure, in particular for a high electron mobility transistor (HEMT) comprising:

a substrate (4) plane,

^■ a first buffer layer (6) is not intentionally doped is disposed on the substrate (4),

A second buffer layer (8) disposed on the first layer (6) and having a thickness determined in a direction orthogonal to the plane of the substrate,

^■ a third buffer layer (10) not intentionally doped disposed on the second buffer layer (8) and having a thickness determined according to a direction orthogonal to the substrate plane,

an unintentionally doped intermediate layer (1 1) disposed on the third layer (10) made of a nitride-based wide bandgap semiconductor material Eg1 of column III identical to that of the stack of buffer layers,

a barrier layer (12) disposed on the intermediate layer (1 1), said barrier layer (12) being made of a nitride-based wide bandgap semiconductor material Eg2 of column III, in which: - the second buffer layer (8) has substantially constant P + type doping over all or part of its thickness, and

the third buffer layer (10) comprises a first region (16) which is unintentionally doped throughout its thickness, as well as at least one second region (18) adjacent to said first region (16) and which is doped with doping N + type,

The heterojunction structure according to claim 1, wherein the second region (18) adjacent to the first region (16) of the third buffer layer (10) has constant doping throughout the thickness of said third buffer layer (10).

A heterojunction structure according to claim 1, wherein the second region (18) adjacent to the first region (16) of the third buffer layer (10) has a Gaussian type doping according to the thickness of said third buffer layer ( 10).

A heterojunction structure according to any one of claims 1 to 3, wherein a distance in a direction orthogonal to the plane of the substrate, between the second buffer layer (8) and the interface between the intermediate layer (1 1) and the barrier layer (12) is less than 20 nm.

The heterojunction structure according to any one of claims 1 to 4, wherein the nitride semiconductor material of the column

III of which are made the first buffer layer (6), the second buffer layer (8), the third buffer layer (10), the intermediate layer (1 1) and the barrier layer (12) comprises GaN.

The heterojunction structure according to any one of claims 1 to 5, wherein the N + type dopant is silicon.

7. heterojunction structure according to any one of claims 1 to 6, comprising at least one transition layer (14) interposed between the substrate (4) and the first buffer layer (6).

A high electron mobility transistor (HEMT) comprising a heterojunction structure according to any one of claims 1 to 7, and comprising a gate electrode (G) of determined surface in a first plane parallel to the plane of the substrate, a drain electrode (D) and a source electrode (S) disposed in a second plane above the barrier layer (12) of the heterojunction structure (2).

A transistor according to claim 8, wherein the first region (16) of the third buffer layer (8) of the heterojunction structure is disposed beneath the gate electrode, and has a surface in a plane parallel to the plane of the substrate which is less than or equal to said surface of the gate electrode (G).

The transistor of any one of claims 8 and 9, further comprising an oxide insulating layer (24), on the barrier layer (12), below the gate electrode, the first and second second shots can be confused or staggered.

1 1. The transistor of claim 10, wherein the insulating layer (24) has a surface in a plane parallel to the plane of the substrate identical to the surface of the gate electrode (G).

12. Transistor according to any one of claims 8 to 11, wherein the second buffer layer (8) P + doped is not connected directly to one of the electrodes (V, G, S) of the transistor.

An electronic semiconductor device comprising at least one high electron mobility transistor (HEMT) according to any one of claims 8 to 12.

14. A method for manufacturing a heterojunction structure, in semiconductor material, in particular for a high electron mobility transistor (HEMT), comprising:

the preparation of a plane substrate (4),

the successive depositions on the substrate (4) of a stack of buffer layers made of the same Ni1-based wideband forbidden semiconductor material of column III of which:

^■ depositing a first buffer layer (6) on the substrate (4), said semiconductor material which is formed said first buffer layer being not intentionally doped, ^■ depositing a second buffer layer (8) on the first buffer layer (6) having a predetermined thickness in a direction orthogonal to the plane of the substrate and doping said second buffer layer being formed by means of doping elements P + type throughout its thickness;

^■ depositing a third buffer layer (10) on the second buffer layer (8) and having a thickness determined according to a direction orthogonal to the plane of the substrate, said semiconductor material which is formed said third buffer layer being not intentionally doped ,

doping with N + doping elements of at least one region (18) of the third buffer layer (10) adjacent to a first region (16) of said third buffer layer which is unintentionally doped according to all its thickness,

depositing an unintentionally doped intermediate layer (1 1) made of a column III nitride wide bandgap-free semiconductor material Eg1 identical to that of the stack of buffer layers on the third buffer layer ( 10)

depositing a second barrier layer (12) of a nitride-based wide bandgap semiconductor material of column III on the third intermediate layer (11).

15. A method of manufacturing a heterojunction structure according to claim 14, wherein the successive deposits of the stack of the buffer layers are made by an epitaxial process without interruption.