FR3053832A1 - METHOD FOR MANUFACTURING FIELD EFFECT HETEROJUNCTION TRANSISTOR AND CORRESPONDING TRANSISTOR - Google Patents

Abstract

The invention relates to a field effect heterojunction transistor, comprising: - a silicon substrate (10), on which a layer of GaN (11) is deposited, - a barrier layer (12) deposited on said GaN layer, to create a conduction channel at the interface of the barrier layer and the GaN layer, first and second ohmic electrodes (S1, S2) formed opposite one another and between which is deposited at least one control electrode (G, G1, G2) for modulating the conductance in said conduction channel between said first and second ohmic electrodes, - a layer of high thermal conductivity dielectric material (102) filling an opening (101) formed in said silicon substrate (10) and extending into a portion of the silicon substrate under the conduction channel throughout the extent of said channel.

Description

Holder (s): RENAULT S.A.S Simplified joint-stock company, COMMISSION FOR ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.

Extension request (s)

Agent (s): CABINET FEDIT LORIOT.

METHOD FOR MANUFACTURING A FIELD-EFFECT HETEROJUNCTION TRANSISTOR AND CORRESPONDING TRANSISTOR.

FR 3 053 832 - A1 (5 /) The invention relates to a heterojunction field effect transistor, comprising:

- a silicon substrate (10), on which is deposited a layer of GaN (11),

a barrier layer (12) deposited on said GaN layer, to create a conduction channel at the interface of the barrier layer and the GaN layer,

- first and second ohmic electrodes (S1, S2) formed opposite each other and between which is deposited at least one control electrode (G, G1, G2) for modulating the conductance in said channel conduction between said first and second ohmic electrodes,

- a layer of dielectric material (102) with high thermal conductivity filling an opening (101) formed in said silicon substrate (10) and extending in a portion of the silicon substrate located under the conduction channel throughout the extent of said channel.

Method for manufacturing a heterojunction field effect transistor and corresponding transistor

The invention relates to transistors with high electronic mobility based on the presence of heterojunctions, in particular, based on Gallium Nitride (GaN) on a silicon substrate and, in particular, a method of manufacturing such transistors.

The invention finds a particular application in circuits and systems for converting electrical energy used in particular in the field of electric vehicles and which require high-performance electronic power components, that is to say which generate few losses while by being able to operate at high frequencies.

The electronic power components from GaN technology on Silicon constitute one of the most promising families of components in terms of performance and cost. This technology is based on the growth by epitaxy of GaN layers on silicon substrate, the technological sector of which is particularly mature, so that we know today how to achieve GaN layers by epitaxy at the right thickness on silicon substrate and cheaper. The physical properties of GaN also make it possible to increase the efficiency of the components, in particular its low specific resistance allows high current densities (4 to 5 times that of silicon).

More specifically, HEMTs (or High Electron Mobility Transistor in the English literature) field effect transistors with high electron mobility, based on the AIGaN / GaN heterojunction, have demonstrated excellent performance and are expected to occupy a significant place in power electronics. In particular, they make it possible to obtain high switching frequencies which are particularly well suited to the needs of electric vehicle battery chargers. Indeed, the increase in frequency makes it possible to reduce the volume of the passive elements and therefore to increase the power density and therefore reduce the cost of the charger. However, the small epitaxy thickness (some 3 to 5 microns) currently limits the maximum blocking voltage of the components to 600 / 650V, while the load applications connected to the three-phase network generally require a blocking voltage of the around 1200 V.

On the other hand, in these high frequency / high power systems, a structure commonly used is the lateral structure of the HEMT type. This lateral structure makes it possible in particular to incorporate a second gate region in the transistor without specific difficulty of design or manufacture. These double grid components allow in particular the use of particularly compact matrix topologies offering very good conversion efficiency.

îo Figure 1 is a diagram illustrating a vertical section of a transistor

HEMT AIGaN / GaN lateral with double gate and common drain. This component is produced from a substrate 10 'of silicon as a support, a channel layer 11' of GaN, and a barrier layer 12 'of Aluminum Gallium Nitride AIGaN forming a heterojunction with the GaN layer. These two semiconductor layers have different forbidden bands which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional electron gas (2DEG) which constitutes the channel located at the AIGaN / GaN interface on the GaN side. The epitaxy thus obtained receives two ohmic electrodes S1 and S2 spaced laterally.

Two control electrodes, commonly called grids, G1 and G2 respectively, are arranged between the two ohmic electrodes S1 and S2. Depending on the common drain architecture chosen, current and voltage are therefore managed by a single channel, which optimizes the specific resistance and the cost of the component. In fact, the presence of two grids allows the component to cut off a voltage whatever its sign and to conduct current in both directions. This characteristic makes it possible to carry out functions for direct conversion from an alternating voltage to another alternating voltage (for example in the context of a variable speed drive from the three-phase network or of an isolated charger which supplies the isolation transformer directly from the supply network) with a significantly higher power density and efficiency than with conventional topologies.

For certain applications, in particular in order to isolate a circuit in the event of a malfunction of a control system, transistors of the normally blocked type are used, that is to say that their threshold voltage (between gate and source) switching is positive, so that the transistor remains blocked in the absence of a control signal. According to a known approach illustrated in FIG. 1 for producing a heterojunction transistor with a normally blocked type field effect, P type dopants such as Mg magnesium are implanted to form implants 110 ′ inside the layer 11. 'of GaN and each control grid G1, G2 is formed on the AIGaN layer directly above a respective implant. Once the implantation of dopant is activated, the electric field generated makes it possible to create an insulating zone vertically, at the interface between the layer of GaN and AIGaN. Thus, the conduction channel is blocked in the layer of electron gas until a positive threshold voltage is reached.

In the case of double gate heterojunction transistors as illustrated in FIG. 1, the silicon substrate must be connected to one of the two sources S1,

S2 according to the direction of the blocked electric field. To do this, an external connection via two diodes is generally used, which requires enriching the circuit and the surface of the substrate where the transistors are placed. The patent document US 2012/0217542 describes the principle of the lateral structure of the HEMT type with double grid. The P-GaN technology used makes it possible to simply insert the polarization diodes of the substrate into the component. Since the diodes are formed between the contacts of the electrodes and the substrate, their resistance to reverse voltage is linked to the thickness of the epitaxial GaN layer. Also, with a view to obtaining an improved tensile strength, one solution would be to increase the thickness of the epitaxial layer of GaN in order to maintain the field at a sufficiently low value at the interface between the layer of GaN and the silicon layer to limit the drain leakage current in the blocked state. However, increasing the thickness of the GaN layer is undesirable. Indeed, it causes significant mechanical stress on the surface, which causes mechanical deformation making the plate difficult or even impossible to use. In other words, the thickness of the GaN material is limited on the silicon, in particular for large silicon substrates (wafers with a diameter greater than or equal to 200 mm) and therefore, the voltage withstand of the component described in the aforementioned document. is itself limited.

However, today, a large part of applications are supplied from the three-phase 400V network, which requires components capable of blocking 1200V, or more.

The document “Above 2000V breakdown voltage on ultrathin barrier 5 AIN / GaN-on-Silicon transistors” (IEMN - CS Mantech conference, 2015, Arizona) announces an innovative solution to improve the high voltage withstand of components of the type having a heterostructure AIN / GaN on silicon substrate. This solution aims to eliminate the parasitic conduction phenomenon of the substrate in the context of high electric fields applied to the channel. More specifically, this solution consists in eliminating the part of the silicon substrate located under the conduction channel. In this way, a high electric field can be applied thereto, limited only by the resistance of the GaN material, by eliminating the risk of leakage current from the silicon substrate. However, the removal of the silicon substrate under the conduction channel produces an undesirable thermal barrier. In fact, the heat produced by the component can no longer be removed by thermal conduction via the silicon initially present under the channel. Consequently, as it stands, the current density is in fact greatly reduced so as not to overheat the component, which eliminates any application in power electronics.

The invention aims to solve one or more of these drawbacks.

Another object of the invention is to allow easy integration of polarization diodes of the substrate of such a double gate component for a blocking voltage greater than 600 volts.

The invention thus relates to a method for manufacturing a heterojunction field effect transistor comprising steps of:

- supply of a silicon substrate comprising an upper face and a lower face,

- formation by epitaxy of a GaN layer on the upper face of the silicon substrate,

- formation by epitaxy of a barrier layer on the GaN layer so as to create a conduction channel located at the interface of the barrier layer and the GaN layer, on the GaN side,

- formation of two opposite ohmic electrodes and at least one control electrode on the barrier layer, said control electrode being disposed between the two ohmic electrodes, to modulate the conductance in the conduction channel between the ohmic electrodes,

- Creation of an opening in the silicon substrate between the underside of the silicon substrate and the GaN layer, said opening extending in a portion of the silicon substrate located under the conduction channel throughout the extent of said channel , said method being characterized in that it comprises a step of:

filling of said opening created in said substrate with a dielectric material with high thermal conductivity.

Thanks to this arrangement, it is possible to fabricate a GaN-based heterojunction field effect transistor on silicon substrate, with a single gate or with a double gate, which has improved voltage withstand without increasing the thickness of the layer of GaN, and without affecting its cooling. In particular, the method of the invention makes it possible to produce a power transistor making it possible to block voltages up to 1200V and more.

By dielectric material with high thermal conductivity is meant a material which has excellent electrical insulation properties, better than those of silicon, while having a thermal conductivity at least equivalent, or even higher, than that of silicon. Such a material is preferably silicon oxide. An alternative consists in using, instead of silicon oxide, aluminum nitride, a composite based on diamond powders, or any other compound capable of ensuring a good compromise between dielectric strength and thermal conduction with a coefficient d thermal expansion which limits the thermomechanical stresses undergone by GaN and silicon.

Advantageously, the opening in the substrate is created by removing, by etching, material from said substrate in said portion of the substrate, until reaching said layer of GaN.

Preferably, the step of filling said opening with said dielectric material comprises:

a first filling step consisting in depositing by a CVD type deposit a first layer of said dielectric material on the surface of said layer of GaN released by said opening, so as to fill a first thickness of said opening, and

a second filling step consisting in depositing by deposition by centrifugation a second layer of said dielectric material on the surface of said first, so as to fill a residual thickness of said opening.

Advantageously, a transistor based on an AIGaN / GaN heterostructure is produced. Also, said barrier layer is a layer of AIGaN.

According to an embodiment known as a double grid, the method can comprise the formation of two control electrodes formed on the respective sides of the two ohmic electrodes, between the two ohmic electrodes, and it comprises a step of integration in said silicon substrate substrate bias diodes capable of bringing said substrate to the potential of one or the other of the two ohmic electrodes according to the direction of the electric field in said conduction channel.

Preferably, the step of integrating said polarization diodes into said substrate comprises steps of:

- supply of a P-doped silicon substrate,

implantation of an N + type doping material in a selected implantation region of said P-doped silicon substrate near each of said ohmic electrodes,

- formation of a metallization layer extending from the N + doped implantation regions towards each respective ohmic electrode nearby.

Advantageously, the N + doped implantation regions extend up to the interface between said layer of GaN and said silicon substrate.

The invention also relates to a heterojunction field effect transistor comprising a multilayer semiconductor structure, comprising:

- a silicon substrate having a lower face and an upper face,

a layer of GaN deposited on the upper face of the silicon substrate,

a barrier layer deposited on said GaN layer, so as to create a conduction channel located at the interface of the barrier layer and the GaN layer, on the GaN side,

- first and second ohmic electrodes which are formed on said multilayer semiconductor structure opposite each other and between which is deposited at least one control electrode for modulating the conductance in said conduction channel between said first and second ohmic electrodes,

a layer of dielectric material with high thermal conductivity filling an opening formed in said silicon substrate between the underside of the silicon substrate and the GaN layer and extending in a portion of the silicon substrate located under the conduction channel in the whole extent of the said canal.

According to an embodiment known as a double gate, the transistor of the invention may comprise two control electrodes formed on the respective sides of the first and second ohmic electrodes between the first and second ohmic electrodes and in that it comprises diodes of polarization integrated into said silicon substrate capable of bringing said substrate to the potential of one or the other of the two ohmic electrodes according to the direction of the electric field in said conduction channel.

The invention also relates to an integrated circuit comprising a transistor as described above.

Other characteristics and advantages of the invention will emerge clearly from the description given below, for information and in no way limitative, with reference to the appended drawings, in which:

- Figure 1 is a schematic sectional view of a heterojunction transistor with double gate field effect and common drain of normally blocked type, known from the prior art, and has already been described;

- Figure 2 is a schematic sectional view of a heterojunction field effect transistor according to a first embodiment of the invention, with a single gate formed between a source and a drain;

- Figure 3 is a schematic sectional view of a field effect heterojunction transistor according to a second embodiment of the invention, with two gates formed between two sources and with common drain;

- Figure 4 is a sectional view of the transistor of Figure 3 with two polarization diodes of the substrate integrated into said substrate.

In Figure 2 is shown a heterojunction field effect transistor

I according to an embodiment known as a single grid. It comprises a semiconductor structure in superimposed layers disposed on a silicon substrate 10, which can be of the intrinsic or doped type. The substrate 10 may for example be of the silicon type with a crystalline orientation (111). A layer 11 of GaN, generally designated by the term channel layer, is deposited on the silicon substrate 10. The layer 11 can be formed in a manner known per se by epitaxy on the substrate 10, for example by means of a deposition process by vapor phase epitaxy, which makes it possible to precisely control the thickness of the deposition of the GaN layer 11. A layer 12 is then formed, called a barrier layer, for example by vapor phase epitaxy on the layer

II of GaN, so as to form a layer of electron gas (2DEG), which constitutes a conduction channel located at the interface between the barrier layer 12 and the layer 11 of GaN, on the GaN side. A layer 12 of AIGaN is particularly suitable for a layer 11 of GaN, the formation of layer 12 by epitaxy then being simply carried out by maintaining the multilayer structure in the same machine (epitaxy reactor), and by carrying out an epitaxy by introducing in addition to aluminum compared to the epitaxy conditions of layer 11.

Then, in a manner known per se, a control electrode G, called the gate electrode, is produced on the barrier layer 12, which forms with the barrier layer 12 a Schottky junction, and a first and a second ohmic electrodes, called the source electrode S and drain electrode D, arranged on either side of the gate electrode G on the barrier layer 12. Preferably, the transistor 1 is of the naturally blocked type. Also, during the formation of layer 11, implantation of P-type dopants is carried out in layer 11 so as to form an implant 110 in layer 11. Implantation is typically carried out by ion implantation and the type of dopants for implant 110 is for example Mg. In addition, an insulating zone 13, for example made of aluminum oxide AI ₂ O3, is formed in the layer of electron gas, directly above the implant 110. The gate electrode G is formed at the plumb with the insulating zone 13 and the implant 110. The transistor thus formed is therefore of the normally blocked type, the zone 13 plumb with the gate G being insulating.

Subsequently, the portion of the substrate 10 located under the conduction channel is removed, so as to electrically isolate the zone of the channel layer where the electric field is high. To do this, from the underside 100 of the substrate 10, an opening 101 is formed in the silicon substrate 10 at the location of the portion of the silicon substrate 10 located under the conduction channel throughout the extent of this channel. The opening 101 in the silicon substrate 10 can be formed by removing by etching the material of the silicon substrate at the location of the portion of substrate located under the channel, until reaching the GaN layer 11. This localized suppression of the silicon substrate prevents leakage currents through the substrate under the conduction zone with a strong electric field, in particular under the zone extending between the gate electrode G and the drain electrode D.

In accordance with the invention, to ensure effective cooling of this zone where most of the heat produced by the component is dissipated, while guaranteeing an electrically insulating barrier, provision is made to fill the opening 101 created in the silicon substrate. under the conduction channel with a dielectric material 102 with high thermal conductivity, allowing the heat to be removed by conduction in place of the silicon initially present. For example, silicon oxide SiO _{2 is used} to fill the opening 101, which has the advantage of being a better electrical insulator than silicon while having thermal conduction properties equivalent to those of silicon. As a variant, it is possible to use aluminum nitride AIN, or any other compound in particular based on diamond powder, which is also both a very good electrical insulator and a very good thermal conductor.

Preferably, the vacuum in the opening 101 created in the silicon substrate 10 under the channel is filled in two stages. In a first filling step, a first layer of SiO ₂ is deposited on the surface of the layer of GaN liberated by a CVD (“Chemical Vapor Deposition”) deposit. the opening 101, so as to fill a first thickness of the opening 101. Then, in a second filling step, a second layer of S1O2 is deposited by centrifugation deposition (“spin coating”) on the surface of the first layer of S1O2 deposited by CVD, so as to fill the residual thickness of the opening 101. The deposition method by centrifugation is advantageously faster and less expensive to implement. Once the opening 101 is completely filled, the layer of S1O2 extends under the conduction channel between the layer of GaN and the underside 100 of the silicon substrate 10.

This principle of increasing the voltage withstand, without increasing the epitaxy thickness of the GaN layer, while guaranteeing the dissipation of the heat produced, can be transposed to a heterojunction transistor with field effect with two gates G1 , G2, as illustrated in FIG. 3, which represents a section of such a transistor 1 'according to the present invention. The same elements as those in the previous figure have the same references. This figure shows the presence of two control or gate electrodes G1, G2 formed on the respective sides of two source electrodes S1 and S2 between these two source electrodes S1 and S2. The electrical insulation and heat dissipation layer based on dielectric material 102 is integrated into the substrate 10 under the conduction channel and, in particular under the zone extending between the two gate electrodes G1 and G2, according to the same principles as set out with reference to the previous figure.

It is customary to set the silicon substrate to the potential of the source of the component, so as to limit the increase in resistance to the passing state just after conduction. In the configuration of the double gate transistor illustrated in FIG. 3, the silicon substrate 10 must be set to the potential of one of the two source electrodes S1 or S2 depending on the direction of the electric field in the conduction channel.

FIG. 4 illustrates the component of FIG. 3, in which polarization diodes have been integrated in the silicon substrate 10 making it possible to set the substrate to the potential of one or the other of the two electrodes S1 or S2 depending on the direction of the electric field in the conduction channel. Such integration of the polarization diodes in the silicon substrate makes it possible to limit the number of components and the interconnections, as well as to increase the power density.

The process of integrating the diodes into the substrate is as follows. The silicon substrate 10 is P-doped, with a resistivity between 3 and 20 ohm.cm, that is to say with a density of P-type dopants between 10 ¹⁵ and 10 ¹⁶ / cm ³ The first step consists in reaching the surface by chemical etching of the P-doped silicon substrate 10 near each of the sources S1 and S2. A very concentrated doping of the bare silicon region 103, 104 is then carried out near the source electrodes S1 and S2, with an N + type dopant, with an density of N + type dopants of the order of 10 ¹⁸ / cm ³ , for example of the arsenic type. A metallization layer 105, 106 is then formed which extends between the N + doped silicon surface of the regions 103, 104 until the metallization of the corresponding source electrode S1, S2, in order to short-circuit the cathode of the integrated diode. to substrate 10 with the source electrode.

The diodes thus integrated into the substrate only serve to polarize the latter to one or other of the sources S1 or S2, depending on the direction of the electric field in the channel, without delivering current. The volume of the N + doped region can therefore be reduced. On the other hand, the PN junction produced must be able to block the same voltage as the JFET GaN (typically 1200V). However, to maintain an electric field in the GaN layer which is less than what GaN can support (approximately 300 V / pm), the N + doped implantation region must go to the limit of GaN deposition, otherwise dit must extend to the interface between the GaN layer and the silicon substrate (starting point of the depletion zone), so as to limit the maximum electric field at the junction point of the GaN / SiO2 zones (or AIN or other) / Si (P doped).

Claims (11)

1. Method for manufacturing a heterojunction field effect transistor (1, T) comprising steps of: 5 - supply of a silicon substrate (10) comprising an upper face and a lower face (100), - formation by epitaxy of a GaN layer (11) on the upper face of the silicon substrate, - formation by epitaxy of a barrier layer (12) on the GaN layer (11) so as to create a conduction channel located at the interface of the barrier layer and the GaN layer, on the GaN side, - formation of two opposite ohmic electrodes (S1, S2, S, D) and at least one control electrode (G, G1, G2) on the barrier layer (12), said control electrode being disposed between the 15 two ohmic electrodes, to modulate the conductance in the conduction channel between the ohmic electrodes, - Creation of an opening (101) in the silicon substrate (10) between the underside (100) of the silicon substrate and the GaN layer (11), said opening extending in a portion of the silicon substrate 20 located under the conduction channel throughout the entire extent of said channel, said method being characterized in that it comprises a step of: - filling said opening (101) created in said substrate (10) with a dielectric material (102) with high thermal conductivity. 2. Method according to claim 1, characterized in that the opening 25 (101) in said substrate (10) is created by etching away material from said substrate in said portion of the substrate, until reaching said layer of GaN (11). 3. Method according to claim 1 or 2, characterized in that the step of filling said opening (101) with said dielectric material (102) 30 includes: - A first filling step consisting in depositing by a CVD type deposit a first layer of said dielectric material (102) on the surface of said GaN layer (11) released by said opening (101), so as to fill a first thickness of said opening, and - A second filling step consisting in depositing by deposition by centrifugation a second layer of said dielectric material (102) on the surface of said first layer, so as to fill a residual thickness of said opening (101). 4. Method according to any one of claims 1 to 3, characterized in that said dielectric material (102) is silicon oxide or aluminum nitride or any other dielectric compound with high thermal conduction. 5. Method according to any one of the preceding claims, characterized in that said barrier layer (12) is a layer of AIGaN. 6. Method according to any one of the preceding claims, characterized in that it comprises the formation of two control electrodes (G1, G2) formed on the respective sides of the two ohmic electrodes (S1, S2) between the two ohmic electrodes (S1, S2) and in that it comprises a step of integrating into said silicon substrate (10) polarization diodes of the substrate capable of bringing said substrate to the potential of one or the other of the two ohmic electrodes (S1, S2) according to the direction of the electric field in said conduction channel. 7. Method according to claim 6, characterized in that the step of integrating said biasing diodes into said substrate comprises steps of: - supply of a P-doped silicon substrate, - implantation of an N + type dopant in a selected implantation region (103, 104) of said P-doped silicon substrate near each of said ohmic electrodes (S1, S2), - formation of a metallization layer (105, 106) extending from the N + doped implantation regions (103, 104) towards each respective ohmic electrode nearby. 8. Method according to claim 7, characterized in that the N + doped implantation regions extend up to the interface between said layer of GaN and said silicon substrate. 9. Heterojunction field effect transistor (1, 1d) comprising a multilayer semiconductor structure, comprising: - a silicon substrate (10) having a lower face (100) and an upper face, - a GaN layer (11) deposited on the upper face of the silicon substrate, a barrier layer (12) deposited on said GaN layer, so as to create a conduction channel located at the interface of the barrier layer and the GaN layer, on the GaN side, - first and second ohmic electrodes (S1, S2, S, D) which are formed on said multilayer semiconductor structure opposite each other and between which is deposited at least one control electrode ( G, G1, G2) to modulate the conductance in said conduction channel between said first and second ohmic electrodes, - a layer of dielectric material (102) with high thermal conductivity filling an opening (101) formed in said silicon substrate (10) between the lower face (100) of the silicon substrate and the GaN layer and extending in a portion of the silicon substrate located under the conduction channel throughout the extent of said channel. 10. Transistor according to claim 9, characterized in that it comprises two control electrodes (G1, G2) formed on the respective sides of the first and second ohmic electrodes (S1, S2) between the first and second ohmic electrodes and in that that it comprises polarization diodes integrated into said silicon substrate (10) capable of bringing said substrate to the potential of one or the other of the two ohmic electrodes according to the direction of the electric field in said conduction channel. 11. Integrated circuit comprising a transistor according to claim 9 or 10.