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EP2304793A1 - Substrate comprising different types of surfaces and method for obtaining such substrates - Google Patents

Substrate comprising different types of surfaces and method for obtaining such substrates

Info

Publication number
EP2304793A1
EP2304793A1 EP09773960A EP09773960A EP2304793A1 EP 2304793 A1 EP2304793 A1 EP 2304793A1 EP 09773960 A EP09773960 A EP 09773960A EP 09773960 A EP09773960 A EP 09773960A EP 2304793 A1 EP2304793 A1 EP 2304793A1
Authority
EP
European Patent Office
Prior art keywords
layer
support
additional
region
superficial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09773960A
Other languages
German (de)
French (fr)
Inventor
Bich-Yen Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority claimed from PCT/US2009/044365 external-priority patent/WO2010002508A1/en
Publication of EP2304793A1 publication Critical patent/EP2304793A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

Description

SUBSTRATE COMPRISING DIFFERENT TYPES OF SURFACES AND METHOD FOR OBTAINING SUCH SUBSTRATES
FIELD OF THE INVENTION The present invention relates to substrates for semiconductor fabrication, and in particular to patterned substrates of satisfactory crystalline quality and comprising bulk areas and SOI (Silicon on Insulator) areas.
BACKGROUND OF THE INVENTION Microelectronic devices are typically manufactured on either bulk semi-conductor substrates or on SOI substrates (Silicon on Insulator). It has also been proposed to use composite substrates comprising bulk areas and SOI areas. See, e.g., US 6,955,971. The fabrication of such patterned substrates is generally difficult because it requires formation of local areas of a buried oxide next to bulk areas. In the case of wafer bonding methods, such local oxide areas can be formed either on the top wafer or the base wafer, and can give rise to so-called "dishing" problems. In the case of a SIMOX type methods (Separation by Implanted Oxygen), such local oxide areas are commonly formed in the original wafer, but the differential thermal expansion of silicon oxides versus silicon gives rise to stress, etc.
SUMMARY OF THE INVENTION
The present invention provides fabrication methods for patterned substrates of satisfactory crystalline quality and comprising bulk areas and SOI areas. The invention also provides substrates fabricated by the provided methods.
Substrates of the invention comprise an insulating layer disposed on a first region of a front face of a support, a superficial layer disposed on the insulating layer and an additional layer disposed at least on a second region of the front face of the support, the additional layer having an exposed surface over the second region.
In preferred embodiments, the invention provides a substrate comprising a support having crystalline defects of a size greater than 10 nm at a density greater than 103 /cm3 or greater than 105 /cm3, an insulating layer disposed on a first region of a front face of the support, a superficial layer disposed on the insulating layer, and an additional layer disposed at least on a second region of the front face of the support, the additional layer having an exposed surface over the second region, and has a thickness sufficient to bury crystalline defects of the support. Preferably, the substrate comprises an epitaxial layer arranged over the first region of the front face of the support, between the support and the insulation layer.
In preferred embodiments, the invention provides methods of manufacturing a semiconductor structure which includes providing a substrate comprising a support, a continuous insulating layer disposed on a front face of the support and a superficial layer disposed on the insulating layer, then forming a masking layer on a first region of the superficial layer, then removing the superficial layer and the insulating layer in a second region uncovered by the masking layer, and then forming an additional, preferably planarized, layer in the second region.
BRIEF DESCRIPTION OF THE DRAWINGS
Other features and advantages of the invention will become apparent from the following description and the appended drawings:
Figure 1 illustrates embodiments of the methods and substrates of the invention; Figure 2 illustrates further embodiments of the methods and substrates of the invention;
Figure 3 illustrates further embodiments of the methods and substrates of the invention;
Figure 4 illustrates further embodiments of the methods and substrates of the invention;
Figure 5 illustrates further embodiments of the methods and substrates of the invention;
Figure 6 illustrates further embodiments of the methods and substrates of the invention; Figure 7 illustrates further embodiments of the methods and substrates of the invention;
Figure 8 illustrates further embodiments of the methods and substrates of the invention;
Figure 9 illustrates further embodiments of the methods and substrates of the invention;
Figure 10 illustrates embodiments of the invention that include the formation electronic devices; Figure 11 illustrates further embodiments of the invention that include the formation electronic devices;
Figure 12 illustrates further embodiments of the invention that include the formation electronic devices; Figure 13 illustrates further embodiments of the invention that include the formation electronic devices;
Figure 14 illustrates further embodiments of the invention that include the formation electronic devices;
Figure 15 illustrates another embodiment of the invention that includes forming electronic devices.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The preferred embodiments and particular examples described herein should be seen as examples of the scope of the invention, but not as limiting the present invention. The scope of the present invention should be determined with reference to the claims.
Figures 1 to 3 illustrate preferred embodiments of the substrates and methods of the invention. In particular, Figure 1 illustrates a substrate comprising support 1 , continuous insulating layer 2 disposed on front face of support 1 , and superficial layer 3 disposed on insulating layer 2, so as to form, e.g., an SOI substrate (silicon on insulator). Figure 2 illustrates that masking layer 7 is formed on first region 4 of superficial layer 3. After removing superficial layer 3 and insulating layer 2 in second region 5 not covered by masking layer 7, additional layer 6 can then be formed in second region 5, preferably by epitaxy. Figure 3 illustrates that additional layer 6 is then planarized, e.g., down to the top level of masking layer 7, as shown by arrow 8. The planarization can be carried out by polishing, e.g. by chemical mechanical polishing (CMP).
Figure 4 illustrates embodiments of substrates that result from the above methods after final removal of masking layer 7. The resulting substrates comprise support 1, insulating layer 2 disposed on first region 4 of front face of support 1 , and superficial layer 3 disposed on insulating layer 2. Additional layer 6 is disposed at least on second region 5 of the front face of support 1 and has exposed surface 15 over second region 5. Since exposed surface 15 of additional layer 6 was planarized down to the top level of masking layer 7, this exposed surface will not necessarily be coplanar with exposed surface 16 after removing masking layer 7. Support 1 and superficial layer 3 can comprise different semi-conducting materials or the same semi-conducting material but with different crystalline orientations, or both. Electronic devices can then be formed in the different materials. Support 1 and superficial layer 3 preferably comprise silicon, germanium, silicon-germanium, or III-V-type semi- conducting materials such as InP, GaN, or GaAs, optionally in a strained state. For instance, germanium could be chosen for PMOS transistors, and III-V-type semi-conducting materials for NMOS transistors, whereas silicon can be used for input-output-circuits and analog circuits.
Insulating layer 2 preferably can have a thickness less than 140 nm, and more preferably between 2 nm and 25 nm or less than 25 nm. Superficial layer 3 preferably has a thickness less than 100 nm and more preferably between 5 nm and 50 nm. In particular, layer 3 preferably has a thickness between 12 nm and 20 nm for planar full depletion SOI transistors, or between 20 nm and 50 nm for vertical multiple gate transistors.
Additional layer 6 preferably has a thickness sufficient to bury some or all of the crystalline defects present in support 1. For example, additional layer 6 can have a thickness of 0.1 micron or more. It is understood that the term "burying" is used herein to describe a layer of sufficient thickness to substantially limit defects that are present at the lower surface of a burying layer from propagating to, and appearing on, the upper surface of the burying layer. Exposed surface 15 of additional layer 6 can then have a suitable crystalline quality and a suitable density of defects even if the front face of the substrate has a density of crystalline defects of a size greater than 10 nm of greater than 103 /cm3 or even greater than 105 /cm3. Since the front surface of support 1 can have a greater density of defects, it can consequently be less expensive.
Also, the thickness of additional layer 6 before planarizing is preferably greater than the combined thicknesses of superficial layer 3, insulating layer 2 and masking layer 7. The planarizing of additional layer 6 can then be stopped at the top level of masking layer 7. Additional layer 6 can comprise materials with a crystalline orientation different than the crystalline orientation of superficial layer 3, and can comprise materials different than those of superficial layer 3. Masking layer 7 preferably has a thickness between 20 nm and 100 nm, and more preferably has a thickness of 50 nm or less, and comprises an oxide material.
Figures 5 and 6 illustrate further preferred embodiments of the substrates and methods of the invention. Here, masking layer 7 in Figure 5 comprises upper layer 7a and lower layer 7b. Figure 6 illustrates that upper layer 7a is preferably removed before planarizing additional layer 6, which can then be stopped at the top level of remaining lower layer 7b.
Upper layer 7a of masking layer 7 can comprise, for instance, a nitride material with a thickness between 10 nm and 100 nm, and lower layer 7b can comprise, for instance, an oxide material with a thickness between 5 nm and 20 nm. If layer 7 comprises only a single layer oxide mask, it should be thicker, for example between 20 nm and 120 nm.
Figure 7 illustrates further preferred embodiments of the substrates and methods of the invention. Here, the substrates of the invention comprise insulator spacer 9 that is formed in order to seal laterally superficial layer 3 and insulating layer 2. After spacer 9 has been formed, additional layer 6 can be grown.
Figure 8 illustrates further preferred embodiments of the substrates and methods of the invention. Here, the substrates of the invention comprise initial epitaxial layer 10 preferably having a thickness greater than 0.1 micron and preferably arranged on the front face of the support, between support 1 and continuous insulation layer 2, or at least arranged on the first region of support, and. Epitaxial layer 10 preferably has a density of crystalline defects with a size greater than 10 nm of less than 103 /cm3. Then support 1 that can have a density of crystalline defects of a size greater than 10 nm of more than 103/cm3 or more than 105/cm3. Since the epitaxial layer buries, at least partially, defects present at the surface of the front side of support 1 , the thickness of additional layer 6 that is also used for burying defects can be less than in the case where no epitaxial layer 10 is formed.
Figure 9 illustrates further preferred embodiments of the substrates and methods of the invention. Here, the substrates further comprise electronic devices 11 in or on additional layer 6 and in or on superficial layer 3.
Figures 10 to 14 illustrate embodiments of methods of the invention for fabricating the substrates of Figure 9. In general, these methods include steps of lithography, etching, and implantation.
More specifically, Figures 10-12 illustrate embodiments of these methods that form devices in or on additional layer 6 and in or on superficial layer 3 during the course of a single device forming process (a single sequence of steps). In other words, the devices can be considered as being formed "at the same time" or "simultaneously" because their formation shares common steps. Figure 10 illustrates a first lithography step comprising projecting or forming lithographic images on selected portions of exposed surface 15 of additional layer 6 and at the same time on selected portions of exposed surface 16 of superficial layer 3. Such projecting or forming can be performed by irradiating (arrows 17) by means of image forming apparatus 12. This lithography (arrows 17 in Figure 10) can be carried out simultaneously for both exposed surfaces 15 and 16, when offset height 13 is less than the depth of focus of the image forming apparatus required for a predetermined image resolution. The smallest pattern and greatest resolution is usually determined by the gate length.
Here, exposed surfaces 15 and 16 are illustrated as being offset by offset height 13 which is preferably less than the depth of focus of a lithography exposure (along a Z-axis perpendicular to the surface of substrate) made by image forming apparatus 12 that corresponds to a predetermined resolution. The depth of focus depends on the image forming apparatus used and on the resolution required by the process applied.
In other words, images of the predetermined resolution can be formed simultaneously on both exposed surfaces 15 and 16 if the depth of focus of the selected lithography tool corresponding to the predetermined image resolution is greater than offset height 13. In cases of lower image resolution, offset height 13 of less than 100 nm can be sufficient for the offset height 13 to be less than the depth of focus corresponding to the lower resolution. In cases of higher image resolution (needed for smaller structures), the depth of focus is preferably small and the offset height 13 is preferably even smaller, e.g., 50 nm or less. Generally, offset height 13 is preferably less than 100 nm, and more preferably less than 50 nm.
Figure 11 illustrates a next step of etching (arrows 20) that can be performed at the same time from both exposed surfaces 15 and 16.
Figure 12 illustrates a further next step of implantation (arrows 14) that can be performed at the same time into exposed surfaces 15 and 16.
Figures 13 and 14 illustrate embodiments of further methods of the invention for fabricating the substrates of Figure 9. Here, devices are formed in or on additional layer 6 and in or on superficial layer 3 by performing distinct lithography steps for each exposed surface. This embodiment is advantageous when the exposed surfaces are offset by a height greater than the depth of focus (along an axis Z perpendicular to the substrate) of the image forming apparatus corresponding to a lithography exposure of the predetermined resolution.
Figure 13 illustrates a distinct lithography step for exposed surface 15. Figure 14 illustrates a separate distinct lithography step for exposed surface 16.
In these embodiments, etching and implantation steps can still be carried out simultaneously for both exposed surfaces 15 and 16. Alternatively, distinct etching steps and/or distinct implantation steps can be performed. Figure 15 illustrates further embodiments of the methods of the invention in which a single lithography step is preformed for exposed surface 15 of additional layer 6 and for exposed surface 16 of superficial layer 3 even though offset height 13 is greater than the depth of focus of the image forming apparatus corresponding to certain required precisions. In this embodiment, different types of electronic devices having different required resolutions are formed in additional layer 6 and in superficial layer 3 (and optionally in the additional superficial layer described below).
For example, small electronic devices 11a, e.g., memory devices, can be formed in superficial layer 3 (and optionally in the additional superficial layer) and large electronic devices 1 Ib, e.g., logic devices, can be formed in additional layer 6, or conversely. The centre of focus of lithography is preferably adjusted to the level where the smallest devices with the highest required image resolution are formed, e.g. to superficial layer 3. Even if the other level, e.g. exposed surface 15 of additional layer 6, is beyond depth of focus 18a corresponding to the highest resolution, one single simultaneous lithography step can be used because the image resolution on the level beyond the depth of focus corresponding to the highest resolution can be sufficient for the larger devices formed therein which need only a lower resolution.
In other words, first depth of focus 18a can be associated to the first level with a higher required image resolution, e.g. superficial layer 3, and second depth of focus 18b can be associated to the second level with a lower required resolution, e.g. exposed surface 15 of additional layer 6. Depth of focus 18b, suitable for a lower image resolution, is typically larger than, and overlaps, depth of focus 18a, suitable for a higher resolution. Thus when considering two distinct depths of focus 18a and 18b, the lithography on exposed surface 15 of additional layer 6 is in fact within larger depth of focus 18b, while at the same time the lithography on exposed surface 16 of superficial layer 3 is in fact within smaller depth of focus 18a.
This approach is not limited to the particular stacks of layers 1, 2, 3 but can also be implemented with other substrates having several different levels in which electronic devices should be formed. This is for instance the case with a bulk substrate having two or more different surface levels.
For example, a substrate (not shown in the figures) useful for the practice of the invention can comprise an additional insulating layer disposed on an additional selected region of superficial layer 3 and an additional semi-conducting superficial layer disposed on the additional insulating layer. A substrate with an additional insulating layer and additional semi-conducting superficial layer can be manufactured by Smart Cut™. Then the four following layers are removed in second region 5 of the substrate: the additional insulating layer, the additional semi-conducting superficial layer, superficial layer 3 and insulating layer 2. In the remaining regions only the additional insulating layer and the additional semiconducting superficial layer are removed except in an additional selected region where the electronic devices are formed in the additional superficial layer.
Electronic devices can then be formed simultaneously in (or on) three levels of such a substrate by the methods of the invention. When the difference in height of the three levels is less than the depth of focus of the process used, lithography, etching and implantation steps are preferably carried out simultaneously. Even when the depth of focus is smaller than the difference in height, these steps can be carried out simultaneously in certain cases, for example when the resolution required in an upper level (or in a lower level) is not as high as in the other levels.

Claims

THE CLAIMSWhat is claimed is:
1. A semiconductor structure useful for the fabrication of semiconductor devices comprising: a support having a front face and crystalline defects with a size greater than 10 nm at a density greater than 103 /cm3; an insulating layer disposed on a first region of the front face of the support; a superficial layer disposed on the insulating layer and having an exposed surface; and an additional layer disposed at least on a second region of the front face of the support, the additional layer having an exposed surface and a thickness sufficient to bury the crystalline defects of the support.
2. The structure of claim 1 wherein the additional layer has a thickness greater than 0.1 micron.
3. The structure of claim 1 further comprising an epitaxial layer arranged on at least the first region of the front face of the support and between the support and the insulating layer.
4. The structure of claim 3 wherein the epitaxial layer has a thickness greater than 0.1 micron.
5. The structure of claim 1 wherein the exposed surface of the additional layer is not coplanar with the exposed surface of the superficial layer.
6. The structure of claim 1 wherein the exposed surface of the additional layer and the exposed surface of the superficial layer are offset by less than 100 nm.
7. The structure of claim 1 wherein the additional layer has one crystalline orientation, and wherein the superficial layer has a different crystalline orientation.
8. The structure of claim 1 wherein the additional layer and the superficial layer comprise different materials.
9. A method of manufacturing a semiconductor structure useful for the fabrication of semiconductor devices comprising: providing a substrate comprising a support, a continuous insulating layer disposed on a front face of the support, and a superficial layer disposed on the insulating layer; forming a masking layer on a first region of the superficial layer; removing the superficial layer and the insulating layer in a second region not covered by the masking layer; forming an additional layer in the second region; and planarizing the additional layer.
10. The method of claim 9 wherein the thickness of the additional layer is greater than a combined thickness of the superficial layer, the insulating layer, and the masking layer.
11. The method of claim 9 wherein planarizing of the additional layer is terminated at the masking layer.
12. The method of claim 9 wherein the masking layer comprises an oxide material with a thickness between 10 nm and 50 nm.
13. The method of claim 9 further comprising, before planarizing, removing an upper layer of the masking layer so as to leave a remaining lower layer of the masking layer, and wherein the planarizing of the additional layer is terminated at the remaining lower layer.
14. The method of claim 13 wherein the upper layer comprises a nitride material and the lower layer comprises an oxide material.
15. The method of claim 9 further comprising, before forming the additional layer, forming an insulator spacer for sealing laterally the superficial layer and the insulating layer.
16. The method of claim 9 wherein the support comprises crystalline defects, and wherein the additional layer has a sufficient thickness to bury the crystalline defects present in the support.
17. The method of claim 9 further comprising forming at the same time electronic devices in the additional layer and in the superficial layer.
18. The method of claim 17 further comprising : performing a single lithographic exposure on the exposed surface of the second region and on the exposed surface of the superficial layer by use of an image forming apparatus, wherein both exposed surfaces are within a first depth of focus of the image forming apparatus corresponding to a first predetermined image resolution so that the exposures on both surfaces are within the first predetermined image resolution; performing a single etching step of both exposed surfaces; and performing a single implantation step into both exposed surfaces.
19. The method of claim 18 wherein a selected one of the exposed surface is within a second depth of focus corresponding to a second higher predetermined image resolution, and wherein the first depth of focus overlaps the second depth of focus so that the selected surface is within the second depth of focus while the other surface is within the first depth of focus.
20. The method according of claim 17 further comprising: performing a first distinct lithographic exposure on an exposed surface of the second region; performing a second distinct lithographic exposure on an exposed surface of the superficial layer; performing a single etching step of both exposed surfaces; and performing a single implantation step into both exposed surfaces.
EP09773960A 2008-06-30 2009-05-18 Substrate comprising different types of surfaces and method for obtaining such substrates Withdrawn EP2304793A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0803700A FR2933236B1 (en) 2008-06-30 2008-06-30 SUBSTRATE COMPRISING DIFFERENT TYPES OF SURFACE, AND METHOD OF MANUFACTURING THE SAME
US9392008P 2008-09-03 2008-09-03
PCT/US2009/044365 WO2010002508A1 (en) 2008-06-30 2009-05-18 Substrate comprising different types of surfaces and method for obtaining such substrates

Publications (1)

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EP2304793A1 true EP2304793A1 (en) 2011-04-06

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EP09773960A Withdrawn EP2304793A1 (en) 2008-06-30 2009-05-18 Substrate comprising different types of surfaces and method for obtaining such substrates

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Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399507A (en) * 1994-06-27 1995-03-21 Motorola, Inc. Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications
JP2647022B2 (en) * 1994-10-24 1997-08-27 日本電気株式会社 Pattern formation method
US6912330B2 (en) * 2001-05-17 2005-06-28 Sioptical Inc. Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
JP4322453B2 (en) * 2001-09-27 2009-09-02 株式会社東芝 Semiconductor device and manufacturing method thereof
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7034362B2 (en) * 2003-10-17 2006-04-25 International Business Machines Corporation Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US20080124847A1 (en) * 2006-08-04 2008-05-29 Toshiba America Electronic Components, Inc. Reducing Crystal Defects from Hybrid Orientation Technology During Semiconductor Manufacture
US7755140B2 (en) * 2006-11-03 2010-07-13 Intel Corporation Process charging and electrostatic damage protection in silicon-on-insulator technology

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2010002508A1 *

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