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EP1760798B1 - Halbleiteranordnung und deren Herstellungsverfahren - Google Patents

Halbleiteranordnung und deren Herstellungsverfahren Download PDF

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Publication number
EP1760798B1
EP1760798B1 EP06016936A EP06016936A EP1760798B1 EP 1760798 B1 EP1760798 B1 EP 1760798B1 EP 06016936 A EP06016936 A EP 06016936A EP 06016936 A EP06016936 A EP 06016936A EP 1760798 B1 EP1760798 B1 EP 1760798B1
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EP
European Patent Office
Prior art keywords
layer
semiconductor device
organic compound
oxide
insulating layer
Prior art date
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EP06016936A
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English (en)
French (fr)
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EP1760798A1 (de
Inventor
Tsuenori Suzuki
Ryoji Nomura
Mikio Yukawa
Nobuhara Ohsawa
Tamae Takano
Yoshinobu Asami
Takehisa Sato
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/50—Forming devices by joining two substrates together, e.g. lamination techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor device provided with an element which has a layer containing an organic compound over a flexible substrate, and also relates to a manufacturing method of the semiconductor device.
  • WO 2004/061906 A2 discloses TFT's comprising a substrate, a gate electrode, a dielectric, source and drain electrodes as well as an organic layer.
  • the organic layer is deposited on source and drain electrodes in such a way that it contacts the dielectric.
  • US 2004/232413 A1 discloses a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely.
  • a metal layer is provided over a substrate, an oxide layer is provided in contact with the metal layer, a layer to be peeled is formed, and the metal layer is irradiated with a laser beam to perform oxidization and form a metal oxide layer, a clear separation is possible with a physical means within the metal oxide layer or at an interface between the metal oxide layer and the oxide layer.
  • US-B1- 6,236,587 discloses memory cells comprising either an isolating material which provides high impedance or one or more inorganic or organic semiconductors, preferably with an anisotropic conducting property.
  • the semiconductor material forms diode junction at the interface to a metallic conductor in the matrix.
  • US 2005/008894 A1 discloses a laminate for forming a substrate with wires, comprising a conductive layer containing Al or an Al alloy as the major component, formed on a substrate and a capping layer containing a Ni-Mo alloy as the major component, formed on the conductive layer, a substrate with wires produced by etching the laminate to remove an unnecessary metal, and a method for producing the same.
  • plastic films have low heat resistance, it is necessary to decrease the highest temperature in a process. Therefore, the semiconductor devices using plastic films are manufactured by an evaporation method or a sputtering method using a metal mask.
  • plastic films have low heat resistance, transistors formed over plastic films cannot have as favorable electrical characteristics as transistors formed over glass substrates at present.
  • the layer 105 containing an organic compound functions as an organic semiconductor, the layer 105 is formed with a material having a carrier-transporting property.
  • the material having a carrier-transporting property does not have in general a polar substituent such as an imide group, a cyano group, or a hydroxyl group. Accordingly, the adhesion between the layer 105 containing an organic compound and the second electrode layer 106 is so low that separation occurs between the layer 105 containing an organic compound and the second electrode layer 106 in a separation step.
  • a region having low adhesion is formed over a substrate having a separation layer, and a region having high adhesion is formed so as to surround an outer edge of the region having low adhesion, when the substrate is viewed from above.
  • an inorganic compound layer is in contact with a layer containing an organic compound not having a polar substituent such as an imide group, a cyano group, or a hydroxyl group; on the other hand, in a cross section of the region having high adhesion, a plurality of inorganic compound layers are in contact with each other.
  • a region 503 having high adhesion may surround an outer edge of a region 502 having low adhesion as exemplified in FIG 13A .
  • the region 503 having high adhesion may be discontinuously formed so as to surround the outer edge of the region 502 having low adhesion.
  • the region 503 having high adhesion with a rectangular shape may be formed in accordance with each side of the region 502 having low adhesion.
  • the region having high adhesion can have various shapes such as a rectangular shape, a circular shape, an elliptical shape, a curved shape, or the like.
  • the substrate and the element-formed layer are separated from each other at the separation layer and the element-formed layer is attached to a flexible substrate.
  • the present invention provides a method for the manufacture of a semiconductor device according to claims 1 and 12 and a semiconductor device according to claims 23 and 32.
  • the adhesion between the inorganic compound layer and the conductive layer is higher than that between the layer containing an organic compound and the conductive layer; therefore, separation is difficult to occur at an interface between the inorganic compound layer and the conductive layer in a separation step.
  • separation at an interface between the conductive layer and the layer containing an organic compound can be prevented by forming a region having low adhesion and a region having high adhesion so as to surround an outer edge of the region having low adhesion when viewed from above.
  • a layer which has an element that has a layer containing an organic compound formed over a substrate typically a storage element, a light-emitting element, a photoelectric conversion element, a solar cell, or a transistor.
  • a semiconductor device in which an element which has a layer containing an organic compound is provided over a flexible substrate can be manufactured with high yield.
  • the inorganic compound layer and the conductive layer have the layer containing an organic compound and the organic insulating layer sandwiched therebetween, and moreover, have a number of regions where the inorganic compound is in contact with the conductive layer. This makes it possible to decrease regions where the layer containing an organic compound and the organic insulating layer are exposed to the air, to suppress intrusion of moisture, oxygen, and the like into these regions, and to decrease deterioration of the semiconductor device.
  • this embodiment mode will describe a method for separating, with high yield, an element which has a layer containing an organic compound between a pair of electrodes and an element-formed layer having the element.
  • a separation layer 102 is formed over a substrate 101, and an inorganic insulating layer 103 is formed over the separation layer 102.
  • a first electrode layer 104 is formed over the inorganic insulating layer 103, and a layer 105 containing an organic compound is formed over the first electrode layer 104 and the inorganic insulating layer 103.
  • a region 100 is a region where the inorganic insulating layer 103 is exposed.
  • the layer 105 containing an organic compound is formed into a pattern having an opening portion by using a metal mask so that the inorganic insulating layer 103 is partially exposed at the opening portion.
  • the layer 105 containing an organic compound is partially etched to partially expose the inorganic insulating layer 103.
  • the substrate 101 a glass substrate, a quartz substrate, a metal or stainless steel substrate with an insulating layer formed over one surface thereof, a plastic substrate having heat resistance enough to resist process temperature of the steps, or the like can be used. Since the aforementioned substrate 101 is not restricted in size and shape, for example, a rectangular substrate with a length of 1 m or more on a side can be used as the substrate 101. With such a rectangular substrate, productivity can be drastically increased. This is a superior point to a circular silicon substrate.
  • the separation layer 102 is formed in a single-layer or multilayer structure by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like with an element selected from tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and silicon (Si); an alloy material containing the element as its main component; or a compound material containing the element as its main component.
  • a crystal structure of a layer containing silicon may be amorphous, microcrystal, or polycrystal.
  • a coating method is a method by which a film is formed by discharging a solution on an object to be processed and includes a spin coating method and a droplet discharging method.
  • a droplet discharging method is a method of forming a predetermined pattern by discharging a droplet of a composition containing particulates from a small hole.
  • the separation layer 102 is preferably formed by using a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum.
  • a layer containing tungsten oxide or tungsten oxynitride, a layer containing molybdenum oxide or molybdenum oxynitride, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed.
  • a mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.
  • a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed as a first layer, and a layer containing any of the following is formed as a second layer: an oxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum; a nitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum; an oxynitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum; and a nitride oxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum.
  • the separation layer 102 has a multilayer structure of a layer containing tungsten and a layer containing tungsten oxide
  • the layer containing tungsten is formed and then an insulating layer is formed with an oxide on the layer containing tungsten, thereby forming a layer containing tungsten oxide at an interface between the layer containing tungsten and the insulating layer.
  • a surface of the layer containing tungsten may be subjected to a treatment such as a thermal oxidation treatment, an oxygen plasma treatment, or a treatment using a solution having strong oxidizability such as ozone water, thereby forming the layer containing tungsten oxide.
  • Tungsten oxide is represented by WO x , where x ranges from 2 to 3.
  • X may be 2 (WO 2 ), 2.5 (W 2 Os), 2.75 (W 4 O 11 ), 3 (WO 3 ), and so on.
  • the separation layer 102 is formed so as to be in contact with the substrate 101 in the above step, the present invention is not restricted to this step.
  • An insulating layer to be a base may be formed so as to be in contact with the substrate 101 and then the separation layer 102 may be provided so as to be in contact with the insulating layer.
  • the inorganic insulating layer 103 is formed with an inorganic compound in a single-layer or multilayer structure by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like.
  • oxidized silicon or nitrided silicon is given.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or the like is given.
  • nitrided silicon silicon nitride, silicon oxynitride, silicon nitride oxide, or the like is given.
  • the inorganic insulating layer 103 may have a multilayer structure.
  • a multilayer may be formed by using an inorganic compound.
  • the inorganic insulating layer 103 may be formed by stacking silicon oxide, silicon nitride oxide, and silicon oxynitride.
  • the first electrode layer 104 can be formed in a single-layer or multilayer structure by using a metal, alloy, compound, or the like having high conductivity by a sputtering method, a plasma CVD method, a coating method, a printing method, an electrolytic plating method, an electroless plating method, or the like.
  • a metal, alloy, conductive compound, mixture thereof, or the like having a high work function specifically 4.0 eV or higher
  • a metal, alloy, conductive compound, mixture thereof, or the like having a low work function specifically 3.8 eV or lower
  • ITO indium tin oxide
  • ZnO zinc oxide
  • a nitride of a metal material such as titanium nitride (TiN), tungsten nitride (WN), or molybdenum nitride (MoN)
  • a metal belonging to Group 1 or 2 of the periodic table of the elements i.e., an alkali metal such as lithium (Li) or cesium (Cs), an alkaline earth metal such as magnesium (Mg), calcium (Ca), or strontium (Sr); aluminum (Al); an alloy containing any of these (such as MgAg or AlLi); a rare earth metal such as europium (Er) or ytterbium (Yb); an alloy containing the rare earth metal; or the like can be used.
  • an alkali metal such as lithium (Li) or cesium (Cs)
  • an alkaline earth metal such as magnesium (Mg), calcium (Ca), or strontium (Sr)
  • Al aluminum
  • an alloy containing any of these such as MgAg or AlLi
  • a rare earth metal such as europium (Er) or ytterbium (Yb); an alloy containing the rare earth metal; or the like
  • an electrode for injecting holes to the layer containing an organic compound i.e., an anode
  • an electrode for injecting electrons to the layer containing an organic compound i.e., a cathode
  • the layer 105 containing an organic compound can be formed by an evaporation method, an electron beam evaporation method, a coating method, or the like.
  • the layer 105 containing an organic compound is formed into a pattern having the region 100 where the inorganic insulating layer 103 is partially exposed.
  • the layer 105 containing an organic compound may be selectively etched to form the region 100 where the inorganic insulating layer 103 is partially exposed.
  • the titanium film is etched into a desired shape by a photolithography method, thereby forming the first electrode layer 104.
  • the layer containing an organic compound is formed with NPB by an evaporation method.
  • the second electrode layer 106 is formed over the inorganic insulating layer 103 and the layer 105 containing an organic compound. Accordingly, a region 110 where the inorganic insulating layer 103 is in contact with the second electrode layer 106 can be formed. Moreover, by the first electrode layer 104, the layer 105 containing an organic compound, and the second electrode layer 106, an element 151 which has the layer containing an organic compound can be formed.
  • the second electrode layer 106 can be formed by an evaporation method, a sputtering method, a CVD method, a printing method, a coating method, or the like.
  • the second electrode layer 106 is preferably formed with a material having a low work function. If the first electrode layer 104 is formed with a material having a low work function, the second electrode layer 106 is preferably formed with a material having a high work function.
  • the second electrode layer 106 is formed by evaporating aluminum by an evaporation method.
  • a stack of the inorganic insulating layer 103 through the second electrode layer 106 is called an element-formed layer 152.
  • FIGS. 6A to 6E A more specific structure of the element 151 which has the layer containing an organic compound is hereinafter shown with reference to FIGS. 6A to 6E .
  • 205 in FIG 6A corresponds to 105
  • a multilayer of 205 and 201 in FIG. 6B corresponds to 105
  • a multilayer of 205 and 202 in FIG 6C corresponds to 105
  • a multilayer of 205 and 203 in FIG 6D corresponds to 105
  • a multilayer of 205, 245, and 244 corresponds to 105.
  • the element 151 which has the layer containing an organic compound functions as a storage element.
  • the layer 205 containing an organic compound may be provided in a single-layer structure or a multilayer structure by stacking a plurality of layers formed with different organic compounds.
  • the thickness of the layer 205 containing an organic compound is preferably set so that the electrical resistance of the storage element changes by applying voltage to the first electrode layer 104 and the second electrode layer 106.
  • the typical thickness of the layer 205 containing an organic compound ranges from 5 to 100 nm, preferably from 10 to 60 nm, and more preferably 10 to 30 nm.
  • the layer 205 containing an organic compound can be formed with an organic compound having a hole-transporting property or an organic compound having an electron-transporting property.
  • phthalocyanine abbreviation: H 2 Pc
  • copper phthalocyanine abbreviation: CuPc
  • VOPc vanadyl phthalocyanine
  • aromatic amine compounds typified by TDATA, MTDATA, m-MTDAB, TPD, DNTPD, BBPB, and TCTA are preferable as the organic compound because they easily generate holes.
  • the substances mentioned here mainly have a hole mobility of 10 -6 cm 2 /Vs or higher.
  • the following metal complex having a quinoline skeleton or a benzoquinoline skeleton, or the like can be used: tris(8-quinolinolato)aluminum (abbreviation: Alq 3 ); tris(4-methyl-8-quinolinolato)aluminum (abbreviation: Almq 3 ); bis(10-hydroxybenzo[ h ]-quinolinato)beryllium (abbreviation: BeBq 2 ); bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum (BAlq); and the like.
  • Alq 3 tris(8-quinolinolato)aluminum
  • Almq 3 tris(4-methyl-8-quinolinolato)aluminum
  • BeBq 2 bis(10-hydroxybenzo[ h ]-quinolinato)beryllium
  • BAlq bis(2-methyl-8-quinolinolato)-4-phenylphenol
  • the following metal complex having an oxazole-based ligand or a thiazole-based ligand, or the like can be used: bis[2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: Zn(BOX) 2 ); bis[2-(2-hydroxyphenyl)benzothiazolato]zinc (abbreviation: Zn(BTZ) 2 ); and the like.
  • 2-4-biphenylyl)-3-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD); 1,3-bis[5-( p - tert -butylphenyl)-1,3,4-oxadiazole-2-yl]benzene (abbreviation: OXD-7); 3-(4- tert -butylphenyl)-4-phenyl-5-(4-biphenylyl)-1,2,4-triazole (abbreviation: TAZ); 3-(4- tert -butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole (abbreviation: p-EtTAZ); bathophenanthroline (abbreviation: BPhen); bathocuproin (abbreviation: BCP); and the like can also be
  • an insulating layer 201 may be formed between the first electrode layer 104 and the layer 205 containing an organic compound.
  • the insulating layer 201 is a layer for injecting charges of holes or electrons from the first electrode layer or the second electrode layer to the layer containing an organic compound, by a tunnel effect.
  • the insulating layer 201 is formed to have the thickness capable of injecting charges to the layer 205 containing an organic compound by a tunnel effect at a predetermined voltage.
  • the typical thickness of the insulating layer 201 ranges from 1 to 4 nm, preferably 1 to 2 nm. Since the insulating layer 201 is as thin as 1 to 4 nm, a tunnel effect occurs in the insulating layer 201, resulting in the increase in the charge-injecting property to the layer 205 containing an organic compound.
  • the insulating layer 201 is thicker than 4 nm, the tunnel effect does not occur in the insulating layer 201 and the electron injection into the layer 205 containing an organic compound gets difficult; thus, the applying voltage at the writing in the storage element increases. Moreover, since the insulating layer 201 is as thin as 1 to 4 nm, throughput improves.
  • the insulating layer 201 is formed with an inorganic compound or an organic compound that is stable thermally and chemically.
  • the following oxides having an insulating property are given: Li 2 O, Na 2 O, K 2 O, Rb 2 O, BeO, MgO, CaO, SrO, BaO, Sc 2 O 3 , ZrO 2 , HfO 2 , RfO 2 , TaO 2 , TcO 2 , MnO 2 , Fe 2 O 3 , CoO, PdO, Ag 2 O, Al 2 O 3 , Ga 2 O 3 , Bi 2 O 3 , and the like.
  • the following fluorides having an insulating property are given: LiF, NaF, KF, CsF, BeF 2 , MgF 2 , CaF 2 , SrF 2 , BaF 2 , AlF 3 , AgF, MnF 3 , and the like.
  • chlorides having an insulating property are given: LiCI, NaCl, KCI, CsCl, BeCl 2 , CaCl 2 , BaCl 2 , AlCl 3 , SnCl 4 , AgCl, ZnCl 2 , TiCl 4 , TiCl 3 , ZrCl 4 , FeCl 3 , PdCl 2 , SbCl 3 , SbCl 2 , SrCl 2 , TlCl 3 , CuCl, CuCl 2 , MnCl 2 , RuCl 2 , and the like.
  • bromides having an insulating property are given: KBr, CsBr, AgBr, BaBr 2 , LiBr, and the like. Furthermore, the following iodides having an insulating property are given: NaI, KI, BaI 2 , TlI 3 , AgI, TiI 4 , CaI2, SiI 4 , CsI, and the like.
  • the following carbonates having an insulating property are given typically: Li 2 CO 3 , K 2 CO 3 , Na 2 CO 3 , MgCO 3 , CaCO 3 , SrCO 3 , BaCO 3 , MnCO 3 , FeCO 3 , CoCO 3 , NiCO 3 , CuCO 3 , Ag 2 CO 3 , ZnCO 3 , and the like.
  • the following sulfates having an insulating property are given typically: Li 2 SO 4 , K 2 SO 4 , Na 2 SO 4 , MgSO 4 , CaSO 4 , SrSO 4 , BaSO 4 , Ti 2 (SOa) 3 , Zr(SO 4 ) 2 , MnSO 4 , FeSO 4 , Fe 2 (SO 4 ) 3 , CoSO 4 , Co 2 (SO 4 ) 3 , NiSO 4 , CuSO 4 , Ag 2 SO 4 , ZnSO 4 , Al 2 (SO 4 ) 3 , In 2 (SO 4 ) 3 , SnSO 4 Sn(SO 4 ) 2 , Sb 2 (SO 4 ) 3 , Bi 2 (SO 4 ) 3 , and the like.
  • nitrates having an insulating property typically: LiNO 3 , KNO 3 , NaNO 3 , Mg(NO 3 ) 2 , Ca(NO 3 ) 2 , Sr(NO 3 ) 2 , Ba(NO 3 ) 2 , Ti(NO 3 ) 4 , Zr(NO 3 ) 4 , Mn(NO 3 ) 2 , Fe(NO 3 ) 2 , Fe(NO 3 ) 3 , Co(NO 3 ) 2 , Ni(NO 3 ) 2 , Cu(NO 3 ) 2 , AgNO 3 , Zn(NO 3 ) 2 , Al(NO 3h , In(NO 3 ) 3 , Sn(NO 3 ) 2 , and the like.
  • nitrides having an insulating property typified by AIN, SiN, and the like are given. The compositions of these inorganic compounds are not necessarily a strict integer ratio.
  • the thickness of the insulating layer is preferably in the range of 1 to 2 nm.
  • the voltage to be applied at the writing increases.
  • organic resins typified by polyimide, acrylic, polyamide, benzocyclobutene, polyester, a novolac resin, a melamine resin, a phenol resin, an epoxy resin, a silicon resin, a furan resin, a diallylphthalate resin, and the like are given.
  • the insulating layer 201 can be formed by an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like. Moreover, a spin coating method, a sol-gel method, a printing method, a droplet discharging method, or the like can be used.
  • an insulating layer 202 having depression and projection, which is continuous may be used.
  • the thickness of the insulating layer at the projection portion be in the range of 1 to 4 nm, preferably 2 to 4 nm, and that of the insulating layer at the depression portion be in the range of 0.1 nm to less than 2 nm, preferably 1 nm to less than 2 nm.
  • an insulating layer 203 dispersed over the first electrode layer 104, which is discontinuous may be provided.
  • the discontinuous insulating layer 203 may have an island shape, a stripe shape, a net-like shape, or the like.
  • insulating particles may be provided instead of the insulating layers 201 to 203.
  • the insulating particles at this time have a grain size of 0.1 to 4 nm, preferably 1 to 4 nm.
  • the insulating layers 201 to 203 or the insulating particles may be provided between the layer 205 containing an organic compound and the second electrode layer 106.
  • the insulating layer with a thickness of 4 nm or less, preferably 2 nm or less, is provided between the first electrode layer 104 and the layer 205 containing an organic compound, or between the layer 205 containing an organic compound and the second electrode layer 106, a tunnel current flows to the insulating layer.
  • a tunnel current flows to the insulating layer.
  • the insulating layer with a thickness of 4 nm or less, preferably 2 nm or less, is provided between the first electrode layer 104 and the layer 205 containing an organic compound, or between the layer 205 containing an organic compound and the second electrode layer 106, a charge-injecting property due to the tunnel effect increases, whereby the layer 205 containing an organic compound can be made thicker.
  • short-circuiting at an initial state can be prevented. Accordingly, the reliability of the storage device and the semiconductor device can be improved.
  • an element having a rectifying action may be provided between the first electrode layer 104 and the layer 205 having an organic compound, or between the second electrode layer 106 and the layer 205 containing an organic compound ( FIG 6E ).
  • the element having a rectifying action typically, a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode is connected to a drain electrode is given. Needless to say, a diode having another structure can also be used.
  • a PN junction diode 211 including semiconductor layers 244 and 245 is provided between the first electrode layer 104 and the layer 205 containing an organic compound.
  • One of the semiconductor layers 244 and 245 is an N-type semiconductor while the other is a P-type semiconductor.
  • the element 151 which has the layer containing an organic compound functions as the light-emitting element.
  • the layer 105 containing an organic compound is formed with an organic compound having a light-emitting property.
  • organic compound having a light-emitting property for example, the following are given: 9,10-di(2-naphthyl)anthracene (abbreviation: DNA); 2- tert -butyl-9,10-di(2-naphthyl)anthracene (abbreviation: t-BuDNA); 4,4'-bis(2,2-diphenylvinyl)biphenyl (abbreviation: DPVBi); coumarin 30; coumarin 6; coumarin 545; coumarin 545T; perylene; rubrene; periflanthene; 2,5,8,11-tetra( tert- butyl)perylene (abbreviation: TBP); 9,10-diphenylanthracene (abbreviation: DPA); 5,12-diphenyltetracene; 4-(dicyanomethylene)-2-methyl-6-[ p -(dimethylamino)styryl]-4
  • compounds capable of emitting phosphorescence such as the following can be given: bis[2-(4',6'-difluorophenyl)pyridinato- N , C 2 ](picolinato)iridium (abbreviation: FIrpic); bis ⁇ 2-[3',5'-bis(trifluoromethyl)phenyl]pydinato- N , C 2 ⁇ (picolinate)iridium (abbreviation: Ir(CF 3 ppy) 2 (pic)); tris(2-phenylpyridinato- N , C 2 )iridium (abbreviation: Ir(ppy) 3 ); (acetylacetonato)bis(2-phenylpyridinato- N ,C 2 )iridium (abbreviation: Ir(ppy) 2 (acac)); (acetylacetonato)bis[2-(2'-thienyl)pyridinato-N,C 3 ]
  • the element 151 functioning as a light-emitting element may be formed by stacking a hole-injecting layer 171 formed with a hole-injecting material, a hole-transporting layer 172 formed with a hole-transporting material, a light-emitting layer 173 formed with an organic compound having a light-emitting property, an electron-transporting layer 174 formed with an electron-transporting material, and an electron-injecting layer 175 formed with an electron-injecting material, and the second electrode layer 106 which are provided over the first electrode layer 104.
  • the hole-transporting material cited in the description of the layer 205 containing an organic compound in FIG. 6A can be used appropriately as the hole-transporting material.
  • a phthalocyanine derivative is effective as the hole-injecting material, and phthalocyanine (abbreviation: H 2 Pc), copper phthalocyanine (abbreviation: CuPc), vanadyl phthalocyanine (abbreviation: VOPc), and the like can be used.
  • a conductive high-molecular compound which has been chemically doped polyethylene dioxythiophene (abbreviation: PEDOT) doped with polystyrenesulfonate (abbreviation: PSS), polyaniline (abbreviation: PAni), or the like can be used.
  • PEDOT polyethylene dioxythiophene
  • PSS polystyrenesulfonate
  • PAni polyaniline
  • a thin film of an inorganic semiconductor such as molybdenum oxide (MoO x ), vanadium oxide (VO x ), or nickel oxide (NiO x ), or an ultrathin film of an inorganic insulator such as aluminum oxide (Al 2 O;) is also effective.
  • MoO x molybdenum oxide
  • VO x vanadium oxide
  • NiO x nickel oxide
  • Al 2 O aluminum oxide
  • aromatic amine compounds are also applicable: 4,4',4"-tris( N,N -diphenyl-amino)-triphenylamine (abbreviation: TDATA); 4,4',4"-tris[ N -(3-methylphenyl)- N -phenyl-amino]triphenylamine (abbreviation: MTDATA); N,N '-bis(3-methylphenyl)- N,N '-diphenyl-1,1'-biphenyl-4,4'-diamine (abbreviation: TPD); 4,4'-bis ⁇ N -[4-( N,N -di- m -tolylamino)phenyl]- N -phenylamino ⁇ biphenyl (abbreviation: DNTPD); and the like.
  • TDATA 4,4',4"-tris( N,N -diphenyl-amino)-triphenylamine
  • MTDATA N '-bis(
  • aromatic amine compounds may be doped with a substance having an acceptor property with respect to the aromatic amine compounds; specifically, VOPc doped with 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (abbreviation: F 4 -TCNQ) or NPB doped with MoOx, which is an acceptor, may be used.
  • F 4 -TCNQ 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane
  • NPB doped with MoOx, which is an acceptor
  • the electron-transporting material As the electron-transporting material, the electron-transporting material cited in the description of the layer 205 containing an organic compound shown in FIG 6A can be appropriately used here.
  • an ultrathin film of an insulator is often used; for example, a halide of an alkali metal such as LiF or CsF, a halide of an alkaline earth metal such as CaF 2 , or an oxide of an alkali metal such as Li 2 O.
  • an alkali metal complex such as lithium acetylacetonate (abbreviation: Li(acac)) or 8-quinolinolato-lithium (abbreviation: Liq) is also effective.
  • a material in which the aforementioned electron-transporting material and a metal having a low work function such as Mg, Li, or Cs are mixed by a co-evaporation method or the like can be used.
  • the element 151 functioning as a light-emitting element may be formed by stacking the first electrode layer 104, a hole-transporting layer 176 formed with an organic compound and an inorganic compound having an electron-accepting property with respect to the organic compound, a light-emitting layer 173, an electron-transporting layer 177 formed with an organic compound and an inorganic compound having an electron-donating property with respect to the organic compound, and the second electrode layer 106.
  • the hole-transporting layer 176 formed with an organic compound and an inorganic compound having an electron-accepting property with respect to the organic compound is formed by appropriately using the aforementioned organic compound having a hole-transporting property as the organic compound.
  • the inorganic compound any inorganic compound can be used as long as electrons are easily accepted from the organic compound, and various metal oxides or metal nitrides can be used.
  • an oxide of a transition metal belonging to any of Groups 4 to 12 of the periodic table of the elements is preferable because such an oxide is likely to have an electron-accepting property.
  • titanium oxide, zirconium oxide, vanadium oxide, molybdenum oxide, tungsten oxide, rhenium oxide, ruthenium oxide, zinc oxide, or the like is given.
  • an oxide of a transition metal belonging to any of Groups 4 to 8 of the periodic table of the elements is preferable for its high electron-accepting property.
  • vanadium oxide, molybdenum oxide, tungsten oxide, and rhenium oxide are preferable because they can be evaporated in vacuum and are easily treated.
  • the electron-transporting layer 177 formed with an organic compound and an inorganic compound having an electron-donating property with respect to the organic compound is formed by appropriately using the aforementioned organic compound having an electron-transporting property as the organic compound.
  • the inorganic compound any inorganic compound can be used as long as electrons are easily donated to the organic compound, and various metal oxides or metal nitrides can be used.
  • an alkali metal oxide, an alkaline earth metal oxide, a rare earth metal oxide, an alkali metal nitride, an alkaline earth metal nitride, and a rare earth metal nitride are preferable because such oxides and nitrides are likely to have an electron-donating property.
  • lithium oxide, strontium oxide, barium oxide, erbium oxide, lithium nitride, magnesium nitride, calcium nitride, yttrium nitride, lanthanum nitride, or the like is given.
  • lithium oxide, barium oxide, lithium nitride, magnesium nitride, and calcium nitride are preferable because they can be evaporated in vacuum and are easily treated.
  • the electron-transporting layer or the hole-transporting layer formed with the organic compound and the inorganic compound is superior in an electron-injecting/transporting property, various materials can be used to form the first electrode layer 104 and the second electrode layer 106 without much restriction by the work function, and moreover, the drive voltage may be decreased.
  • the element 151 which has the layer containing an organic compound functions as a photoelectric conversion element or a solar cell.
  • the layer 105 containing an organic compound is formed to be a stack of charge-generating layer and a charge-accepting layer, which has a PN junction.
  • a multilayer of 161 and 162 in FIG. 8A corresponds to 105
  • a multilayer of 161 and 163 in FIG 8B corresponds to 105
  • a multilayer of 162 and 164 in FIG. 8C corresponds to 105
  • a multilayer of 163 and 164 in FIG 8D corresponds to 105.
  • a photoelectric conversion element and a solar cell each have a multilayer structure in which the first electrode layer 104, the charge-generating layer 161, a charge-accepting layer 162, and the second electrode layer 106 are provided sequentially.
  • the first electrode layer 104 or the second electrode layer 106 is formed with a conductive material having a light-transmitting property.
  • the charge-generating layer 161 and the charge-accepting layer 162 may be formed by appropriately selecting the aforementioned organic compound having a hole-transporting property and organic compound having an electron-transporting property.
  • the organic compound having an electron-transporting property a perylene derivative, a naphthalene derivative, a quinone derivative, methylviologen, fullerene, an organic metal compound containing ruthenium, platinum, titanium, or the like, or the like may be used.
  • the charge-generating layer 161 is formed with a compound having a hole-transporting property
  • the charge-accepting layer 162 is formed with a compound having an electron-transporting property.
  • an electron-transporting layer 163 formed with an organic compound having an electron-transporting property and an inorganic compound having an electron-donating property with respect to the organic compound may be provided instead of the charge-accepting layer 162.
  • the electron-transporting layer 163 can be formed by appropriately selecting a compound shown as the electron-transporting layer 177 in FIG 7B , which is formed with the organic compound having an electron-transporting property and the inorganic compound having an electron-donating property with respect to the organic compound.
  • an electron-generating layer 164 formed with an organic compound having a hole-transporting property and an inorganic compound having an electron-accepting property with respect to the organic compound may be provided instead of the charge-generating layer 161.
  • the electron-generating layer 164 can be formed by appropriately selecting a compound shown as the hole-transporting layer 176 in FIG 7B , which is formed with the organic compound having an electron-transporting property and the inorganic compound having an electron-accepting property with respect to the organic compound.
  • the electron-generating layer 164 formed with an organic compound having a hole-transporting property and an inorganic compound having an electron-accepting property with respect to the organic compound, and the electron-transporting layer 163 formed with an organic compound having an electron-transporting property and an inorganic compound having an electron-donating property with respect to the organic compound, are provided instead of the charge-generating layer 161 and the charge-accepting layer 162, respectively.
  • the layer containing an organic compound When the layer containing an organic compound is formed to be a layer having the PN junction between charge-generating layer and charge-accepting layer, electrons and holes generated in the charge-generating layer can be made electron carriers and hole carriers to become photocurrent. Accordingly, a solar cell and a photoelectric conversion device capable of converting light energy into electrical energy can be manufactured.
  • the charge-generating layer or the charge-accepting layer is formed with an organic compound and an inorganic compound, electron and hole generating efficiency can be improved. Accordingly, a photoelectric conversion element and a solar cell having high energy conversion efficiency can be achieved.
  • a thin film transistor formed by using a layer containing an organic compound in an active region may be formed as the element 151 which has a layer containing an organic compound.
  • FIG 9A shows an example of applying a staggered organic semiconductor transistor.
  • the separation layer 102 and the inorganic insulating layer 103 are provided over the substrate 101, and an organic semiconductor transistor is provided over the inorganic insulating layer 103 as the element 151 which has a layer containing an organic compound.
  • a gate electrode 1402 an insulating layer 1403 functioning as a gate insulating film, a semiconductor layer 1404 overlapping with the gate electrode and the insulating layer 1403 functioning as a gate insulating film, and a wire 1405 connected to the semiconductor layer 1404.
  • the semiconductor layer 1404 is in contact with the wire 1405 and the insulating layer 1403 functioning as a gate insulating film.
  • the gate electrode 1402 can be formed by similar material and method to those of the first electrode layer 104.
  • the gate electrode 1402 can also be formed by a droplet discharging method and by drying and/or baking.
  • the gate electrode 1402 can be formed over the inorganic insulating layer 103 by printing a paste containing fine particles by a printing method and drying and/or baking the paste.
  • fine particles fine particles containing any of the following as its main component are given: gold; copper; an alloy of gold and silver; an alloy of gold and copper; an alloy of silver and copper; and an alloy of gold, silver, and copper.
  • a fine particle containing a conductive oxide such as indium tin oxide (ITO) as its main component may be used.
  • the insulating layer 1403 functioning as a gate insulating film can be formed by similar material and method to those of the inorganic insulating layer 103. Moreover, the insulating layer 1403 can be formed with an organic compound.
  • a polycyclic aromatic compound As the material for the semiconductor layer 1404 of the organic semiconductor transistor, a polycyclic aromatic compound, a conjugated-double-bond-based compound, phthalocyanine, a charge transfer complex, and the like are given.
  • anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene tetracarboxylic dianhydride), NTCDA (naphthalene tetracarboxylic dianhydride), or the like can be used.
  • a ⁇ -conjugated high molecular compound such as an organic high-molecular compound, carbon nanotube, polyvinyl pyridine, a phthalocyanine metal complex, and the like are given.
  • a ⁇ -conjugated high molecular compound of which skeleton includes a conjugated double bond such as polyacetylene, polyaniline, polypyrrole, polythienylene, a polythiophene derivative, poly(3alkylthiophene), a polyparaphenylene derivative, or a polyparaphenylenevinylene derivative is preferable.
  • a method for forming the semiconductor layer 1404 of the organic semiconductor transistor a method by which a film with uniform thickness can be formed may be used.
  • the thickness ranges from 1 to 1000 nm, preferably from 10 to 100 nm.
  • an evaporation method, an electron beam evaporation method, or the like can be used.
  • the gate electrode 1402, the insulating layer 1403 functioning as a gate insulating film, the wire 1405, and the semiconductor layer 1404 overlapping with the gate electrode and the insulating layer functioning as a gate insulating film may be formed. It is to be noted that the wire 1405 is in contact with the insulating layer functioning as a gate insulating film and the semiconductor layer 1404.
  • the insulating layer 107 is formed over the second electrode layer 106.
  • a substrate 108 is attached on the surface of the insulating layer 107.
  • the insulating layer 107 is preferably formed by applying a composition by a coating method and then drying and/or heating the composition. Since the insulating layer 107 is provided as a protecting layer working in a later separation step, the insulating layer 107 preferably has little depression and projection on the surface. Such an insulating layer can be formed by a coating method. Moreover, the insulating layer 107 may be formed by forming a film by a thin-film forming method such as a CVD method or a sputtering method and then polishing the surface of the film by a CMP method.
  • a thin-film forming method such as a CVD method or a sputtering method
  • the insulating layer 107 formed by a coating method is formed by using an organic compound such as an acrylic resin, a polyimide resin, a melamine resin, a polyester resin, a polycarbonate resin, a phenol resin, an epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), a furan resin, or a diallylphthalate resin; an inorganic siloxane polymer including a Si-O-Si bond (siloxane bond) among compounds including hydrogen, oxygen, and silicon formed by using a siloxane polymer-based material typified by silica glass as a starting material; or an organic siloxane polymer in which hydrogen bonded to silicon is substituted by an organic group such as methyl or phenyl, typified by an alkylsiloxane polymer, an alkylsilsesquioxane polymer, a silsesquioxane hydride polymer, an alkylsilsesquioxane
  • the insulating layer formed by the aforementioned thin-film forming method which is then subjected to surface polishing by a CMP method, is formed with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.
  • the substrate 108 is preferably a flexible, thin, and lightweight substrate.
  • a substrate including PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthalamide, or the like can be used.
  • paper made of a fibrous material a multilayer film including a base material film (polyester, polyamide, an inorganic evaporated film, paper, or the like) and an adhesive organic resin film (an acrylic-based organic resin, an epoxy-based organic resin, or the like), or the like can also be used.
  • a base material film polyyester, polyamide, an inorganic evaporated film, paper, or the like
  • an adhesive organic resin film an acrylic-based organic resin, an epoxy-based organic resin, or the like
  • the insulating layer 107 and the substrate 108 are attached to each other by providing an adhesive layer between the insulating layer 107 and the substrate 108.
  • a film having an adhesive layer to which a laminate process is carried out to an object to be processed by thermocompression may be used as the substrate 108.
  • the laminating film can be attached to an object to be processed in such a way that an adhesive layer provided on a surface of a base film or a layer provided at an outermost layer of a base film(not the adhesive layer) is melted by a heat treatment and then, by applying pressure thereto, the film is attached to the object to be processed.
  • the adhesive layer is not necessarily provided between the insulating layer 107 and the substrate 108.
  • the insulating layer 107 is formed using an epoxy resin in such a way that a composition is applied by a coating method and then the composition is dried and/or baked. Next, the substrate 108 is attached over the insulating layer 107 by thermocompressing the laminating film on the surface of the insulating layer 107.
  • the separation layer 102 and the inorganic insulating layer 103 are separated from each other.
  • the inorganic insulating layer 103 and the second electrode layer 106 are in contact with each other. Since the adhesiveness between the inorganic insulating layer 103 and the second electrode layer 106 is so high that separation is difficult to occur at an interface between the layer 105 containing an organic compound and the second electrode layer 106, and in consequence, it is achieved that separation is carried out at the peeling layer 102 and the inorganic insulating layer 103 in a separation step.
  • this embodiment mode uses a method for physically separating the element-formed layer, in which the separation layer and the insulating layer are formed between the substrate and the element-formed layer, the metal oxide film is provided between the separation layer and the insulating layer, and the metal oxide film is weakened by crystallization, the present invention is not restricted to this method.
  • any of the following methods can also be used appropriately: (1) a method in which an amorphous silicon film containing hydrogen is provided between the substrate and the element-formed layer, and the amorphous silicon film is irradiated with laser light so that hydrogen gas in the amorphous silicon film is released, thereby separating the substrate; (2) a method in which the separation layer and the insulating layer are formed between the substrate and the element-formed layer, the metal oxide film is provided between the separation layer and the insulating layer, the metal oxide film is weakened by crystallization, a part of the separation layer is etched away using a solution or a halogen fluoride gas such as NF 3 , BrF 3 , or ClF 3 , and separation is physically carried out at the weakened metal oxide film; (3) a method in which only the substrate of the substrate where the element-formed layer is formed is mechanically removed or is etched away using a solution or a halogen fluoride gas such as NF 3 , Br 3 , or ClF 3 ; (4)
  • a substrate 109 is attached on the surface of the inorganic insulating layer 103.
  • the substrate 109 can be made of a similar material to that of the substrate 108.
  • the substrate 109 is attached on the inorganic insulating layer 103 by thermocompression of a laminating film.
  • the element which has the layer containing an organic compound can be provided over the flexible substrate with high yield using the separation step.
  • this embodiment mode will describe a method for separating an element-formed layer, which is different from that in Embodiment Mode 1.
  • This embodiment mode is different from Embodiment Mode 1 in that an insulating layer (partition wall) is provided so as to cover an edge portion of the first electrode layer.
  • the separation layer 102 is formed over the substrate 101, similarly to Embodiment Mode 1.
  • the inorganic insulating layer 103 is formed over the separation layer 102 and the first electrode layer 104 is formed over the inorganic insulating layer 103.
  • an insulating layer (partition wall) 111 is formed covering an edge portion of the first electrode layer 104.
  • the insulating layer 111 is formed by using an inorganic insulator such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride by a thin-film forming method such as a CVD method or a sputtering method.
  • the insulating layer 111 is formed in such a way that an insulating film is formed by a thin-film forming method and then the insulating film is selectively etched so that the first electrode layer 104 is partially exposed.
  • the insulating layer 111 is preferably etched so that its cross sectional shape has a tilt angle of 30 to 75°, preferably 35 to 60°. By having such a tilt angle, the coverage for the edge portion of the cross section of the later-formed layer containing an organic compound is improved, whereby breaking due to steps can be prevented as well as yield can be improved.
  • a layer 112 containing an organic compound is formed on the exposed surface of the insulating layer 111 and the first electrode layer 104, similarly to Embodiment Mode 1.
  • the layer 112 containing an organic compound is formed so that the insulating layer 111 is partially exposed. In other words, an exposed portion 114 of the insulating layer 111 is formed.
  • a second electrode layer 113 is formed over the layer 112 containing an organic compound and the exposed portion 114 of the insulating layer 111, similarly to Embodiment Mode 1. Accordingly, a region 115 can be formed in which the insulating layer 111 is in contact with the second electrode layer 113. In the region 115 where the insulating layer 111 is in contact with the second electrode layer 113, the adhesion between the insulating layer 111 and the second electrode layer 113 is so high that separation is difficult to occur at an interface between the layer 112 containing an organic compound and the second electrode layer 113, and in consequence, it is achieved that separation is carried out at the separation layer 102 and the inorganic insulating layer 103.
  • a stack of the inorganic insulating layer 103 through the second electrode layer 113 is called an element-formed layer 153.
  • the element which has the layer containing an organic compound can be provided over the flexible substrate with high yield by using the separation step.
  • this embodiment mode will describe a method for separating an element-formed layer, which is different from that in Embodiment Mode 1.
  • This embodiment mode is different from Embodiment Mode 2 in that the insulating layer (partition wall) covering the edge portions of the first electrode layer is formed with an organic compound.
  • the separation layer 102 is formed over the substrate 101, the inorganic insulating layer 103 is formed over the separation layer 102, and the first electrode layer 104 is formed over the inorganic insulating layer 103, similarly to Embodiment Mode 1.
  • an insulating layer (partition wall) 121 covering the edge portions of the first electrode layer 104 is formed.
  • the insulating layer 121 is formed by a coating method, a printing method, or a droplet discharging method, using a nonphotosensitive organic compound such as an acrylic resin, a polyimide resin, a melamine resin, a polyester resin, a polycarbonate resin, a phenol resin, an epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), a furan resin, or a diallylphthalate resin.
  • a nonphotosensitive organic compound such as an acrylic resin, a polyimide resin, a melamine resin, a polyester resin, a polycarbonate resin, a phenol resin, an epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), a furan resin, or a diallylphthalate resin.
  • the organic compound that forms the insulating layer 121 has a polar substituent such as an imide group, a cyano group, or a hydroxyl group.
  • the insulating layer 121 is formed in such a way that an insulating film is formed by discharging a composition and drying and baking the composition and the insulating film is selectively etched away by using a resist mask formed by a photolithography step so that the first electrode layer 104 and the inorganic insulating layer 103 are partially exposed.
  • the insulating layer 121 is formed by applying a composition so as to cover the edge portions of the first electrode layer 104 and partially expose the inorganic insulating layer 103, and drying and baking the composition.
  • the insulating layer 121 is formed in such a way that an insulating film is formed by a coating method and the insulating film is partially removed by dry etching so that the first electrode layer 104 and the inorganic insulating layer 103 are partially exposed. That is, the insulating layer 121 is formed so that an exposed portion 120 of the inorganic insulating layer 103 is formed.
  • the insulating layer 121 is preferably etched so that its cross sectional shape has a tilt angle of 30 to 75°, preferably 35 to 60°, similarly to the insulating layer 111 shown in Embodiment Mode 2.
  • a layer 122 containing an organic compound is formed over the insulating layer 121 and the exposed surface of the first electrode layer 104, similarly to Embodiment Mode 1.
  • a second electrode layer 123 is formed over the layer 122 containing an organic compound, the insulating layer 121, and the exposed portion 120 of the inorganic insulating layer 103, similarly to Embodiment Mode 1. Accordingly, a region 124 can be formed where the inorganic insulating layer 103 is in contact with the second electrode layer 123.
  • the adhesion between the inorganic insulating layer 103 and the second electrode layer 123 is so high that separation is difficult to occur at an interface between the layer 122 containing an organic compound and the second electrode layer 123, and separation can be carried out at the separation layer 102 and the inorganic insulating layer 103.
  • a stack of the inorganic insulating layer 103 through the second electrode layer 123 is called an element-formed layer 154.
  • the element which has the layer containing an organic compound can be provided over the flexible substrate with high yield by using the separation step.
  • this embodiment mode will describe a method for separating an element-formed layer having a different structure from those of Embodiment Modes 1 to 3.
  • This embodiment mode is different from Embodiment Mode 3 in that the insulating layer (partition wall) covering the edge portions of the first electrode layer is formed with a photosensitive organic compound.
  • the separation layer 102 is formed over the substrate 101, the inorganic insulating layer 103 is formed over the separation layer 102, and the first electrode layer 104 is formed over the inorganic insulating layer 103, similarly to Embodiment Mode 1.
  • an insulating layer (partition wall) 131 covering the edge portions of the first electrode layer 104 is formed.
  • the insulating layer 131 is formed with a positive or negative photosensitive material such as acrylic, polyimide, styrene, vinyl chloride, a diazo resin, an azide compound, a novolac resin, or polyvinyl cinnamate. It is to be noted that a sensitizer may be added to the photosensitive material.
  • the insulating layer 131 is formed by a coating method, a printing method, or a droplet discharging method.
  • the insulating layer 131 is formed in such a way that an insulating film is formed by discharging a composition and drying and baking the composition, the insulating film is light-exposed, developed, and then partially removed so that the first electrode layer 104 and the inorganic insulating layer 103 are partially exposed, and the insulating film is baked.
  • the insulating layer 131 formed by light-exposing and developing the photosensitive organic compound has curvature at an upper edge portion thereof. Therefore, it is possible to prevent breaking of the later-formed layer containing an organic compound and to improve yield.
  • the insulating layer 131 is formed in such a way that an insulating film is formed by applying a composition containing photosensitive acrylic by a coating method and drying the composition, and then the insulating film is light-exposed and developed by a photolithography step, and baked, so that the first electrode layer 104 and the inorganic insulating layer 103 are partially exposed. That is, an exposed portion 130 of the inorganic insulating layer 103 is formed.
  • the insulating layer 131 is preferably etched so that its cross sectional shape has a tilt angle of 30 to 75°, preferably 35 to 60°, similarly to the insulating layer 111 shown in Embodiment Mode 2.
  • a layer 132 containing an organic compound is formed over the insulating layer 131 and an exposed surface of the first electrode layer 104, similarly to Embodiment Mode 1.
  • a second electrode layer 133 is formed over the layer 132 containing an organic compound, the insulating layer 131, and the exposed portion 130 of the inorganic insulating layer 103, similarly to Embodiment Mode 1. Accordingly, a region 134 can be formed where the inorganic insulating layer 103 is in contact with the second electrode layer 133.
  • the adhesion between the inorganic insulating layer 103 and the second electrode layer 133 is so high that separation is difficult to occur at an interface between the layer 132 containing an organic compound and the second electrode layer 133, and separation can be carried out at the separation layer 102 and the inorganic insulating layer 103.
  • a stack of the inorganic insulating layer 103 through the second electrode layer 133 is called an element-formed layer 155.
  • the element which has the layer containing an organic compound can be provided over the flexible substrate with high yield by using the separation step.
  • This embodiment mode will describe a method for separating an element-formed layer having a different structure from that in Embodiment Modes 1 to 4, with reference to FIGS. 5A to 5E .
  • This embodiment mode is different from Embodiment Modes 2 and 3 in that the second electrode layer is in contact with a conductive layer formed similarly to the first electrode layer.
  • the separation layer 102 is formed over the substrate 101, the inorganic insulating layer 103 is formed over the separation layer 102, and the conductive layer is formed over the inorganic insulating layer 103, similarly to Embodiment Mode 1.
  • the conductive layer is selectively etched by using a resist mask formed by a photolithography step, thereby forming the first electrode layer 104 and a conductive layer 181.
  • the insulating layer 121 covering the edge portions of the first electrode layer 104 is formed similarly to Embodiment Mode 2.
  • the layer 122 containing an organic compound is formed over the insulating layer 121 and the exposed surface of the first electrode layer 104, similarly to Embodiment Mode 1. It is to be noted that the layer 122 containing an organic compound is formed so that the conductive layer 181 is partially exposed. An exposed portion of the conductive layer 181 is denoted by 182.
  • the second electrode layer 123 is formed so as to be in contact with the layer 122 containing an organic compound and the exposed portion 182 of the first conductive layer 181, similarly to Embodiment Mode 1. Accordingly, a region 184 can be formed where the conductive layer 181 is in contact with the second electrode layer 123. In the region 184 where the conductive layer 181 is in contact with the second electrode layer 123, the adhesion between the conductive layer 181 and the second electrode layer 123 is so high that separation is difficult to occur at an interface between the layer 122 containing an organic compound and the second electrode layer 123 in a separation step, and separation can be carried out at the separation layer 102 and the inorganic insulating layer 103.
  • a stack of the inorganic insulating layer 103 through the second electrode layer 123 is called an element-formed layer 156.
  • the element which has the layer containing an organic compound can be provided over the flexible substrate with high yield by using the separation step.
  • This embodiment will describe a semiconductor device having a storage element as an element which has a layer containing an organic compound, typically a storage device.
  • FIG 10A shows a structural example of a semiconductor device which will be described in this embodiment.
  • the semiconductor device includes a memory cell array 22 in which memory cells 300 are arranged in a matrix form, decoders 23 and 24, a selector 25, and a reading/writing circuit 26.
  • decoders 23 and 24 a selector 25
  • reading/writing circuit 26 a reading/writing circuit 26.
  • the structure of a storage circuit 16 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be provided, or a writing circuit may be provided in a bit line driver circuit.
  • the decoders 23 and 24, the selector 25, the reading/writing circuit 26, an interface, and the like can be formed over a substrate by using thin film transistors similarly to a storage element. Alternatively, they may be attached externally as IC chips.
  • the memory cell 300 has a first conductive layer connected to a bit line Bx (1 s x s m), a second conductive layer connected to a word line Wy (1 ⁇ y ⁇ n), and a layer containing an organic compound, which is in contact with the first conductive layer.
  • the layer containing an organic compound is formed by one or more layers between the first conductive layer and the second conductive layer.
  • FIGS. 11A to 11C Examples of a top-surface structure and a cross-sectional structure of the memory cell array 22 are shown in FIGS. 11A to 11C.
  • FIG 11A shows a top-surface structure of the memory cell array 22, and its cross-sectional structures along a line A-B and a line C-D in FIG. 11A correspond to FIGS. 11B and 11C , respectively.
  • a region surrounded by a dotted line 314 is a region where a first organic insulating layer 306 and a second organic insulating layer 310 are formed.
  • Substrates 332 and 334, and the organic insulating layers 306, 310, and 331 are omitted.
  • bit lines 304a to 304g and second electrode layers 312a to 312g are formed.
  • Memory cells are formed at intersections of the bit lines and the word lines.
  • a storage element is formed by the first conductive layer, the layer containing an organic compound, and a second word line (a second electrode layer).
  • a memory cell 300a formed at an intersection of the bit line 304e and the second electrode layer 312d and a memory cell 300b formed at an intersection of the bit line 304d and the second electrode layer 312a are described hereinafter (see FIG 11A ).
  • the memory cell 300a has a storage element 305a (see FIG. 11B ).
  • the storage element 305a has, over the substrate 334, a first electrode layer 307 connected to the bit line 304e extending in a first direction; a layer 311 containing an organic compound, which covers the first electrode layer 307; and a second electrode layer 312d extending in a second direction perpendicular to the first direction.
  • a region 313 is formed where the insulating layer 303 is in contact with the second electrode layer 312d.
  • the layer 311 containing an organic compound keeps a distance constant between the first electrode layer 307 and the second electrode layer 312d.
  • an insulating layer functioning as a protective film may be provided so as to cover the second electrode layer 312d.
  • the memory cell 300b has a storage element 305b.
  • the storage element 305b has a first electrode layer 324 connected to a bit line extending in a first direction; the layer 311 containing an organic compound, which covers the first electrode layer 324; and the second electrode layer 312a extending in a second direction perpendicular to the first direction.
  • regions 325 and 326 are formed where the insulating layer 303 is in contact with the second electrode layer 312a.
  • the insulating layer 331 is formed over the second electrode layers 312a to 312g to reduce depression and projection of the surface, and then the substrate 332 is attached over the insulating layer 331.
  • a plastic film is used here as the substrate 332.
  • FIG 11B shows an example in which the layer 311 containing an organic compound is formed so as to overlap with a plurality of the first electrode layers
  • the layer 311 containing an organic compound may be formed selectively only in each memory cell.
  • the layer 311 containing an organic compound can be formed by an evaporation method using a metal mask. Further, usage efficiency of the material can be improved by providing the layer containing an organic compound in such a way that an organic compound is selectively discharged by a droplet discharging method or the like and the organic compound is baked.
  • the material and formation method of the bit lines 304a to 304g, the first electrode layers 307 and 324, and the second electrode layers 312a to 312g can be similar to those of the first electrode and the second electrode shown in Embodiment Mode 1.
  • the layer 311 containing an organic compound can be provided by similar material and forming method to those of the layer 105 containing an organic compound shown in Embodiment Mode 1.
  • Reduction in size, thickness, and weight of the semiconductor device can be achieved when the flexible substrate, the laminating film, the paper made of a fibrous material, or the like shown as the substrates 108 and 109 in Embodiment Mode 1 is used as the substrates 332 and 334.
  • FIGS. 12A to 12C Next, a method for manufacturing a passive matrix type semiconductor device is described with reference to FIGS. 12A to 12C .
  • FIG 12A is a cross-sectional view of a memory cell array of a passive matrix type semiconductor device. It is to be noted that peripheral circuits such as the bit line driver circuit, the word line driver circuit, and an interface are omitted.
  • a separation layer 302 is formed in 30 nm thick over a substrate 301, and the insulating layer 303 is formed over the separation layer 302.
  • a 30-nm-thick tungsten layer is formed as the separation layer 302 by a sputtering method, and a 100-nm-thick silicon oxide layer, a 50-nm-thick silicon nitride oxide layer, and a 100-nm-thick silicon oxynitride layer are formed as the insulating layer 303 by a CVD method.
  • an amorphous silicon film is formed in 66 nm thick over the insulating layer 303 by a CVD method and subjected to heat treatments at 500°C for one hour and at 550°C for four hours, so that the amorphous silicon film is crystallized to form a crystalline silicon film.
  • a metal oxide here a tungsten oxide layer, is formed at an interface between the separation layer 302 and the insulating layer 303. It is to be noted that separation can be carried out easily in a later separation step when the metal oxide is formed at the interface between the separation layer 302 and the insulating layer 303.
  • the bit lines 304e to 304g are formed.
  • the bit lines 304e to 304g are formed in such a way that a 60-nm-thick titanium layer, a 40-nm-thick titanium nitride layer, a 300-nm-thick aluminum layer, a 60-nm-thick titanium layer, and a 40-nm-thick titanium nitride layer are stacked by a sputtering method and these layers are selectively etched by using a resist mask formed by a photolithography step.
  • the bit lines 304e to 304g are preferably formed with aluminum, which is a low-resistant material.
  • the first organic insulating layer 306 is formed over the bit lines 304e to 304g.
  • polyimide is applied, light-exposed, and developed and then the insulating layer 303 and the bit lines 304e to 304g are partially exposed, followed by baking at 300°C for 30 minutes; thus, the first organic insulating layer 306 is formed.
  • the first electrode layers 307 to 309 are formed over the first organic insulating layer 306 and the exposed portions of the bit lines 304e to 304g.
  • the first electrode layers 307 to 309 are formed in such a way that a 100-nm-thick titanium film is formed by a sputtering method and then the titanium film is selectively etched by using a resist mask formed by a photolithography step.
  • the second organic insulating layer 310 is formed over the first insulating layer and the first electrode layers 307 to 309.
  • the second organic insulating layer 310 is formed by using photosensitive polyimide, similarly to the first organic insulating layer. Even though depression and projection are formed on the surface of the bit lines 304e to 304g due to heating, the layer containing an organic compound can be formed over the first electrode layers 307 to 309 which are to be connected to the bit lines 304e to 304g through the second organic insulating layer 310. Even when the layer containing an organic compound is thin, involvement of depression and projection of the surface of the bit lines 304e to 304g can be suppressed; therefore, short-circuiting of the storage element prior to writing can be prevented.
  • the layer 311 containing an organic compound is formed over the first electrode layers 307 to 309 and the second organic insulating layer 310.
  • NPB is formed in 10 nm thick as the layer 311 containing an organic compound by using a metal mask.
  • the second electrode layer 312d is formed over the layer 311 containing an organic compound and the insulating layer 303.
  • the second electrode layer 312d is formed so that the region 313 is formed where the insulating layer 303 is in contact with the second electrode layer 312d.
  • the adhesion between the insulating layer 303 and the second electrode layer 312d is so high that the separation layer and the insulating layer can be separated from each other with high yield in a later separation step.
  • the substrate 332 having an adhesive layer is attached over the insulating layer 331.
  • an epoxy resin is used as the insulating layer 331.
  • the adhesive layer of the substrate 332 is plasticized by being heated at 120 to 150°C; thus, the substrate 332 is attached to the insulating layer 331.
  • the substrate 301 is provided over a flat surface, a roller (not shown) having a sticky layer is attached to the surface of the substrate 332 while applying pressure thereto, and then separation is carried out at an interface between the separation layer 302 and the insulating layer 303 as shown in FIG. 12B .
  • the substrate 334 having an adhesive layer here a plastic film
  • the substrate 334 is attached to the surface of the insulating layer 303 and heated at 120 to 150°C so that the adhesive layer of the substrate 334 is plasticized.
  • the substrate 334 is attached to the surface of the insulating layer 303.
  • the passive matrix type semiconductor device provided over a plastic film can be manufactured. Any of Embodiment Modes 1 to 5 can be applied to this embodiment.
  • the memory cell 300 is selected by the decoders 23 and 24 and the selector 25. Specifically, a predetermined voltage of V2 is applied by the decoder 24 to a word line W3 connected to the memory cell 300.
  • the bit line B3 connected to the memory cell 300 is connected to the reading/writing circuit 26 by the decoder 23 and the selector 25. Then, a writing voltage of V1 is outputted from the reading/writing circuit 26 to the bit line B3.
  • the layer containing an organic compound provided between the electrode layers can be changed physically or electrically, thereby writing data "1".
  • the electrical resistance between the first electrode layer and the second electrode layer in a data "1" state at the reading operation voltage may be changed so as to be much smaller than that in a data "0" state.
  • the voltage is controlled so that the data "1" is not written in the memory cells connected to unselected word lines and unselected bit lines.
  • the unselected word lines and the unselected bit lines may be set in a floating state.
  • the first electrode layer and the second electrode layer need to correlate with each other so as to satisfy a characteristic capable of securing selectivity such as a diode characteristic.
  • the electrical action is not applied to the memory cell 300.
  • the memory cell 300 is selected by the decoders 23 and 24 and the selector 25, similarly to the case of writing the data "1", but the output potential from the reading/writing circuit 26 to the bit line B3 is set to be similar to the potential of the selected word line W3 or the potential of the unselected word line.
  • a voltage of such a degree that the electrical characteristics of the memory cell 300 do not change may be applied between the first electrode layer and the second electrode layer that constitute a part of the memory cell 300.
  • the data reading is carried out by utilizing the fact that a memory cell having a data "0" and a memory cell having a data "1" have different electrical characteristics between the first electrode layer and the second electrode layer that constitute a part of the memory cell.
  • a method of reading by using the difference in the effective electrical resistance will be described assuming that the electrical resistance between the first conductive layer and the second conductive layer that constitute a part of the memory cell having the data "0" (hereinafter this electrical resistance is referred to as the electrical resistance of the memory cell, simply) is R0 at the reading voltage and that of the memory cell having the data "1" is R1 at the reading voltage.
  • the reading/writing circuit 26 includes a resistor element 46 and a differential amplifier 47 shown in FIG 10B as a structure of a reading portion.
  • the resistor element 46 has a resistance value Rr, and R1 ⁇ Rr ⁇ R0.
  • the resistor element 46 may be replaced by a transistor 48, and the differential amplifier may be replaced by a clocked inverter 49 ( FIG 10C ).
  • the clocked inverter 49 has a signal ⁇ or an inverted signal ⁇ inputted therein, where the signal or the inverted signal becomes "HIGH" when reading is carried out and "LOW" when reading is not carried out.
  • the circuit structure is not restricted to those shown in FIGS. 10B and 10C .
  • the memory cell 300 When data is read from the memory cell 300, first, the memory cell 300 is selected by the decoders 23 and 24 and the selector 25. Specifically, a predetermined voltage of Vy is applied to the word line Wy connected to the memory cell 300 by the decoder 24. Moreover, the bit line Bx connected to the memory cell 300 is connected to a terminal P of the reading/writing circuit 26 by the decoder 23 and the selector 25. Accordingly, the terminal P has a potential Vp, which is obtained by Vy and V0. The Vy and V0 are determined by resistance division by the resistor element 46 (resistance value Rr) and the memory cell 300 (resistance value R0 or R1).
  • the state of the electrical resistance of the layer containing an organic compound is read out by a voltage value using the difference in the resistance value and the resistance division.
  • the reading method is not restricted to this method.
  • a difference in a current value may be used for the reading. If the electrical characteristics of the memory cell are diode characteristics that the threshold voltage is different at the data "0" and the data "1", the data reading may be carried out by using a difference in the threshold voltage.
  • a resistor be connected serially to the storage element.
  • the resistor preferably has a resistance value of 5% or lower of that of the storage element. Accordingly, in the short-circuited storage element, excessive current flow can be prevented. Thus, it is possible to prevent the storage element from being broken by excessive current flow.
  • Thin film transistors may be provided over the inorganic insulating layer 103 and the memory cell 300 or the memory cell array 22 may be provided over the TFTs.
  • field effect transistors FETs
  • FETs field effect transistors
  • separation can be carried out at an interface of the separation layer instead of the layer containing an organic compound of the storage element.
  • the layer having the storage element formed over the substrate having heat resistance and to provide the layer over a flexible substrate.
  • the semiconductor device of the present invention has a storage element having a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers, the semiconductor device can be inexpensive.
  • This embodiment will describe a method for manufacturing a semiconductor device having an organic thin film transistor as an element which has a layer containing an organic compound.
  • the separation layer 302 is formed in 30 nm thick over the substrate 301 and the insulating layer 303 is formed over the separation layer 302, similarly to Embodiment 1.
  • an amorphous silicon film is formed over the insulating layer 303 and heated to form a crystalline silicon film as well as a metal oxide layer at an interface between the separation layer 302 and the insulating layer 303. Separation can be carried out easily in a later separation step by forming the metal oxide layer at the interface between the separation layer 302 and the insulating layer 303. After that, the crystalline silicon film is removed.
  • a first electrode layer 351 and a conductive layer 352 are formed over the insulating layer 303.
  • the aluminum layer is selectively etched by using a resist mask formed by a photolithography step to form the first electrode layer 351 and the conductive layer 352.
  • the first electrode layer 351 functions as a gate electrode. Further, the first electrode layer 351 and the conductive layer 352 are not connected to each other.
  • an insulating layer 353 is formed over the first electrode layer 351 and the conductive layer 352.
  • the insulating layer 353 is formed with polyimide so that the conductive layer 352 is partially exposed.
  • a reference numeral 355 denotes an exposed part of the insulating layer 353. It is to be noted that the insulating layer 353 functions as a gate insulating layer.
  • a layer 354 containing an organic compound is formed over a portion where the insulating layer 353 overlaps with the first electrode layer 351, by an evaporation method.
  • the layer 354 containing an organic compound is formed by evaporating pentacene using a metal mask.
  • a second electrode layer 356 is formed over the exposed portion 355 of the conductive layer 352, the insulating layer 353, and the layer 354 containing an organic compound.
  • the second electrode layer 356 is formed with gold by an evaporation method.
  • a region 358 is formed where the conductive layer 352 is in contact with the second electrode layer 356.
  • the adhesion between the conductive layer 352 and the second electrode layer 356 is so high that separation does not occur between the layer 354 containing an organic compound and the second electrode layer 356 in a later separation step, and separation can be carried out at the separation layer 302 and the insulating layer 303.
  • the second electrode layer 356 functions as a source electrode (source wire) and a drain electrode (drain wire). Subsequently, a protective layer 357 is formed over the insulating layer 353, the layer 354 containing an organic compound, and the second electrode layer 356.
  • any of Embodiment Modes 1 to 5 can be applied.
  • This embodiment will describe a method for manufacturing a semiconductor device having an organic solar cell as an element which has a layer containing an organic compound.
  • the separation layer 302 is formed in 30 nm thick over the substrate 301 and the insulating layer 303 is formed over the separation layer 302, similarly to Embodiment 1.
  • an amorphous silicon film is formed over the insulating layer 303 and heated to form a crystalline silicon film as well as a metal oxide layer is formed at an interface between the separation layer 302 and the insulating layer 303. After that, the crystalline silicon film is removed. Then, a first electrode layer 341 is formed over the insulating layer 303.
  • the ITO film is selectively etched by using a resist mask formed by a photolithography step to form the first electrode layer 341.
  • an insulating layer 342 is formed over the first electrode layer 341.
  • the insulating layer 342 is formed with polyimide.
  • the insulating layer 342 is formed so as to partially expose the electrode layer 341.
  • a reference numeral 344 denotes an exposed portion of the insulating layer 303.
  • a layer 343 containing an organic compound is formed over a part of the insulating layer 342 and the first electrode layer 341 by an evaporation method using a metal mask.
  • the layer 343 containing an organic compound is formed by stacking a first layer containing an inorganic compound and an organic compound having a hole-transporting property and a second layer containing an organic compound having an electron-transporting property.
  • the first layer containing an inorganic compound and an organic compound having a hole-transporting property is formed by co-evaporating molybdenum trioxide (MoO 3 ) and NPB, which is aromatic amine, with a molar ratio of 1 : 1.
  • the second layer containing an organic compound having an electron-transporting property is formed by evaporating fullerene (C60).
  • a second electrode layer 345 is formed over the exposed portion 344 of the insulating layer 303, the insulating layer 342, and the layer 343 containing an organic compound.
  • the second electrode layer 345 is formed with aluminum by an evaporation method.
  • a region 346 is formed where the insulating layer 303 is in contact with the second electrode layer 345.
  • the adhesion between the insulating layer 303 and the second electrode layer 345 is so high that separation does not occur between the layer 343 containing an organic compound and the second electrode layer 345 in a later separation step, and separation can be carried out at the separation layer 302 and the insulating layer 303.
  • any of Embodiment Modes 1 to 5 can be applied.
  • the solar cell of this embodiment can be provided as a battery for various kinds of illumination appliances, illumination apparatuses, illumination instruments for home use, outdoor lamps, street lights, unmanned public facilities, personal computers, game machines, navigation systems, mobile audio appliances, portable AV appliances, cameras such as digital cameras, film cameras, and instant cameras, calculators, wristwatches, wall clocks, and the like.
  • design quality thereof can be improved by providing the battery under a face.
  • a semiconductor device 20 of the present invention has a function to send and receive data without contact, and has a power source circuit 11, a clock generating circuit 12, a data modulating/demodulating circuit 13, a controlling circuit 14 which controls another circuit, an interface circuit 15, a storage circuit 16, a bus 17, and an antenna 18 as shown in FIG. 16A .
  • the semiconductor device 20 of the present invention has a function to send and receive data without contact, and may have a central processing unit 51, in addition to the power source circuit 11, the clock generating circuit 12, the data modulating/demodulating circuit 13, the controlling circuit 14 which controls another circuit, the interface circuit 15, the storage circuit 16, the bus 17, and the antenna 18.
  • the semiconductor device 20 of the present invention has a function to send and receive data without contact, and may have a detection portion 52 including a detection element 53 and a detection controlling circuit 54, in addition to the power source circuit 11, the clock generating circuit 12, the data modulating/demodulating circuit 13, the controlling circuit 14 which controls another circuit, the interface circuit 15, the storage circuit 16, the bus 17, the antenna 18, and the central processing unit 51.
  • the detection portion 52 including the detection element 53 and the detection controlling circuit 54 and the like are formed in addition to the power source circuit 11, the clock generating circuit 12, the data modulating/demodulating circuit 13, the controlling circuit 14 which controls another circuit, the interface circuit 15, the storage circuit 16, the bus 17, the antenna 18, and the central processing unit 51.
  • This structure makes it possible to form a compact and multi-functional semiconductor device.
  • the power source circuit 11 is a circuit generating various power sources to be supplied to each circuit in the semiconductor device 20 based on an alternating signal inputted from the antenna 18. Moreover, the power source circuit 11 may have one or more solar cells shown in any of Embodiment Modes 1 to 5.
  • the clock generating circuit 12 is a circuit generating various clock signals to be supplied to each circuit in the semiconductor device 20 based on an alternating signal inputted from the antenna 18.
  • the data modulating/demodulating circuit 13 has a function to modulate/demodulate data to be sent to or received from a reader/writer 19.
  • the controlling circuit 14 has a function to control the storage circuit 16.
  • the antenna 18 has a function to send and receive an electromagnetic wave or an electric wave.
  • the reader/writer 19 sends and receives data to and from the semiconductor device, controls the semiconductor device, and controls the process of the data sent to or received from the semiconductor device.
  • the semiconductor device is not restricted to the above structure, and for example, another element such as a limiter circuit of power source voltage or hardware only for processing codes may be added.
  • the storage circuit 16 has one or more elements selected from the storage elements shown in Embodiment Modes 1 to 5.
  • the storage element which has the layer containing an organic compound can achieve downsizing, film thinning, and capacity increasing at the same time; therefore, when the storage circuit 16 is provided by using the storage element which has the layer containing an organic compound, the reduction in size and weight of the semiconductor device can be achieved.
  • the detection portion 52 can detect temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, gas constituent, liquid constituent, and other characteristics by a physical or chemical means. Moreover, the detection portion 52 has the detection element 53 for detecting a physical quantity or a chemical quantity and the detection controlling circuit 54 for converting the physical quantity or the chemical quantity detected by the detection element 53 into an appropriate signal such as an electrical signal.
  • the detection element 53 it is possible to use a resistor element, a capacitively coupled element, an inductively coupled element, a photovoltaic element, a photoelectric conversion element, a thermo-electromotive force element, a transistor, a thermistor, a diode, or the like, and one or more elements selected from the photoelectric conversion elements shown in any of Embodiment Modes 1 to 5 can be used.
  • the number of detection portions 52 may be more than one and, in such a case, it is possible to detect a plurality of physical quantities or chemical quantities simultaneously.
  • the physical quantity described here means temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, and the like
  • the chemical quantity means a chemical substance such as a gas constituent or a constituent included in a liquid such as an ion, or the like.
  • an organic compound such as a particular biological substance included in blood, sweat, urine, or the like (for example, blood-sugar level in the blood) is also included.
  • a substance which selectively reacts with the substance to be detected is provided in advance in the detection element 53.
  • a biological substance in the case of detecting a biological substance, it is preferable to fix, in a high molecular compound or the like, an enzyme, an antibody molecule, a microbial cell, or the like which selectively reacts with the biological substance to be detected by the detection element 53.
  • a semiconductor device functioning as a wireless chip can be formed according to the present invention.
  • the wireless chip is applicable in a wide range.
  • the wireless chip can be applied to banknotes, coins, securities, bearer bonds, identification certificates (driver's license, certificate of residence, and the like, see FIG. 17A ), containers for package (package paper, bottles, and the like, see FIG 17C ), recording media (DVD software, video tapes, and the like, see FIG 17B ), vehicles (bicycles and the like, see FIG 17D ), personal belongings (bags, glasses, and the like), foods, plants, animals, human bodies, clothes, commodities, electronic appliances, baggage tags (see FIGS. 17E and 17F ), and the like.
  • the electronic appliances include a liquid crystal display device, an EL display device, a television device (also referred to as simply a TV, a TV receiving machine, or a television receiving machine), a mobile phone, and the like.
  • the semiconductor device 20 of the present invention is fixed to a product by attaching the semiconductor device 20 to the surface of the product or embedding it inside the product.
  • the semiconductor device 20 is fixed to the book by embedding it inside a paper
  • the semiconductor device 20 is fixed to the package by embedding it inside the organic resin. Since the semiconductor device 20 of the present invention can be compact, thin, and lightweight, the design quality of the product itself is not degraded even after the device is fixed to the product.
  • a certification function can be provided and the forgery can be prevented by using the certification function.
  • the semiconductor device of the present invention is provided in containers for package, recording media, personal belongings, foods, clothes, commodities, electronic appliances, and the like, systems such as an inspection system can become more efficient.
  • This embodiment will describe steps of manufacturing a semiconductor device having a light-emitting element.
  • the separation layer 302 is formed in 30 nm thick over the substrate 301 and the insulating layer 303 is formed over the separation layer 302, similarly to Embodiment 1.
  • an amorphous silicon film is formed over the insulating layer 303 and heated to form a crystalline silicon film as well as a metal oxide layer is formed at an interface between the separation layer 302 and the insulating layer 303.
  • the crystalline silicon film is removed.
  • a first electrode layer 361 is formed over the insulating layer 303.
  • the ITO film is selectively etched by using a resist mask formed by a photolithography step to form the first electrode layer 361.
  • an insulating layer 362 is formed over the first electrode layer 361.
  • the insulating layer 362 is formed with photosensitive polyimide.
  • the insulating layer 362 is formed so as to partially expose the electrode layer 361.
  • a reference numeral 364 denotes an exposed portion of the insulating layer 303.
  • a layer 363 containing an organic compound is formed over a part of the insulating layer 362 and the first electrode layer 361 by an evaporation method using a metal mask.
  • the layer 363 containing an organic compound is formed with an organic compound having a light-emitting property.
  • a pixel having a red-light-emitting property, a pixel having a blue-light-emitting property, and a pixel having a green-light-emitting property are formed by using an organic compound having a red-light-emitting property, an organic compound having a blue-light-emitting property, and an organic compound having a green-light-emitting property, respectively for the layer 363 containing an organic compound.
  • DNTPD with a thickness of 50 nm
  • NPB with a thickness of 10 nm
  • Alq 3 with a thickness of 60 nm
  • LiF with a thickness of 1 nm
  • the layer containing an organic compound having a green-light-emitting property DNTPD with a thickness of 50 nm, NPB with a thickness of 10 nm, Alq 3 doped with coumarin 545T (C545T) with a thickness of 40 nm, Alq 3 with a thickness of 60 nm, and LiF with a thickness of 1 nm are stacked.
  • the layer containing an organic compound having a blue-light-emitting property DNTPD with a thickness of 50 nm, NPB with a thickness of 10 nm, 9-[4-( N -carbazolyl)]phenyl-10-phenylanthracene (abbreviation: CzPA) doped with 2,5,8,11-tetra( tert -butyl)perylene (abbreviation: TBP) with a thickness of 30 nm, Alq 3 with a thickness of 60 nm, and LiF with a thickness of 1 nm are stacked.
  • CzPA 9-[4-( N -carbazolyl)]phenyl-10-phenylanthracene
  • TBP 2,5,8,11-tetra( tert -butyl)perylene
  • a pixel having a white-light-emitting property may be formed by using an organic compound having a white-light-emitting property. By providing a pixel having a white-light-emitting property, power consumption can be reduced.
  • a second electrode layer 365 is formed over the layer 363 containing an organic compound, the insulating layer 362, and the insulating layer 303.
  • an Al film with a thickness of 200 nm is formed by an evaporation method.
  • a region 366 is formed where the insulating layer 303 formed with an inorganic compound is in contact with the second electrode layer 365.
  • the adhesion between the insulating layer 303 and the second electrode layer 365 is so high that separation does not occur between the layer 363 containing an organic compound and the second electrode layer 365 in a later separation step, and in consequence, it is achieved that separation is carried out at the separation layer 302 and the insulating layer 303.
  • a protective layer 367 is formed over the second electrode layer 365.
  • the protective layer is to prevent the intrusion of moisture, oxygen, and the like into the light-emitting element and the insulating layer 362.
  • the protective layer 367 is preferably formed with silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, aluminum oxide, diamond-like carbon (DLC), carbon containing nitrogen (CN), and other insulating materials by a thin-film forming method such as a plasma CVD method or a sputtering method.
  • a semiconductor device having a passive matrix type light-emitting element provided over a plastic film can be manufactured.
  • any of Embodiment Modes 1 to 5 can be applied.
  • an FPC or a driver IC is mounted onto the EL display panel shown in Embodiment 5.
  • a chip-like driver circuit formed by TFTs is referred to as a driver IC.
  • a structure shown in FIG 19 is an example employing a COG method, which is preferable for a compact size with a narrowed frame (for example, 1.5 inch diagonal).
  • a driver IC 1011 is mounted on a substrate 1010, and an FPC 1019 is mounted on a terminal portion 1018 positioned at an end of the driver IC.
  • a plurality of driver ICs 1011 over a rectangular substrate with a length of 300 mm to 1000 mm on one side.
  • a plurality of circuit patterns each including a driver circuit portion and an input/output terminal as one unit are formed over a substrate and then the substrate is divided so that the driver ICs are taken out individually.
  • the driver IC may have a rectangular shape with a length of 15 to 80 mm on a long side and 1 to 6 mm on a short side in consideration of the length of one side of a pixel portion and a pixel pitch.
  • the superiority of the outside dimension of the driver IC to the IC chip lies in the length of the long side.
  • the driver IC has a long side of 15 to 80 mm, the number of chips to be mounted can be fewer than that in the case of using the IC chip, thereby increasing the yield of the production.
  • the driver IC is formed over a glass substrate, the shape of the substrate used as a base material is not limited and the productivity is not lowered. This is a great advantage in comparison with the case of taking IC chips from a circular silicon wafer.
  • a TAB method is also applicable.
  • a TAB method a plurality of tapes may be pasted and the driver ICs may be mounted on the tapes.
  • a single driver IC may be mounted on a single tape.
  • a metal chip or the like for fixing the driver IC is preferably pasted in point of the strength.
  • a connection region 1017 provided between a pixel portion 1012 and the driver IC 1011 is provided so that the second electrode layer of the light-emitting element is in contact with wires of a lower layer.
  • a sealing substrate 1014 is fixed to the substrate 1010 by a sealing material 1015 surrounding the pixel portion 1012 and a filling material surrounded by the sealing material.
  • driver IC may be replaced by an IC chip formed by Si.
  • An electronic appliance shown as the example here is a mobile phone including cases 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 20 ).
  • the panel 2701 is detachably incorporated into the housing 2702 and the housing 2702 is fitted into the printed wiring board 2703.
  • the shape and size of the housing 2702 are appropriately modified in accordance with an electronic appliance to which the panel 2701 is to be incorporated.
  • the printed wiring board 2703 has a plurality of packaged semiconductor devices mounted thereon.
  • a semiconductor device 2710 of the present invention can be used as one of the packaged semiconductor devices.
  • the plurality of semiconductor devices mounted on the printed wiring board 2703 have any function of a controller, a central processing unit (CPU), a memory, a power source circuit, an audio processing circuit, a sending/receiving circuit, and the like.
  • the panel 2701 is connected to the printed wiring board 2703 through a connection film 2708.
  • the panel 2701, the housing 2702, and the printed wiring board 2703 are included inside the cases 2700 and 2706 together with the operation buttons 2704 and the battery 2705.
  • a pixel region 2709 in the panel 2701 is provided so as to be observed from an opening window provided in the case 2700.
  • the semiconductor devices shown in Embodiments 5 and 6 can be used.
  • the semiconductor device of the present invention has advantages of its compactness, thinness, and lightness in weight. These advantages allow efficient usage of limited space in the cases 2700 and 2706 of the electronic appliance.
  • cases 2700 and 2706 are shown as one example of a mobile phone, and the electronic appliances of this embodiment can be modified variously in accordance with the function and purpose.

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Claims (40)

  1. Verfahren zum Herstellen einer Halbleitervorrichtung, das die folgenden Schritte umfasst:
    Ausbilden einer Trennschicht (102) über einem Substrat (101);
    Ausbilden einer anorganischen Verbundschicht (103) über der Trennschicht (102);
    Ausbilden einer ersten leitenden Schicht (104) über der anorganischen Verbundschicht (103);
    Ausbilden einer Schicht, die eine organische Verbindung (105; 112M; 122; 132) enthält, sowohl über der ersten leitenden Schicht (104) als auch der anorganischen Verbundschicht (103) in einem Muster, in dem die anorganische Verbundschicht (103) teilweise freiliegt;
    Ausbilden einer zweiten leitenden Schicht (106; 113; 123; 133) über der Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, um ein Element auszubilden, wobei ein Abschnitt der zweiten leitenden Schicht (106; 113; 123; 133) in den Teilen in Kontakt mit der Schicht aus einer anorganischen Verbindung (103) ist, die durch die Schicht (105; 112; 122; 132) freigelegt sind, die eine organische Verbindung enthält; und
    Trennen der ersten und der zweiten leitenden Schicht (106; 113; 123; 133) sowie der Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, von dem Substrat (101) und der Trennschicht (102).
  2. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei die Schicht (103) aus einer anorganischen Verbindung eine Isolierschicht ist.
  3. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei die Schicht (103) aus einer anorganischen Verbindung Siliziumoxid, Siliziumoxynitrid, Siliziumnitridoxid oder/und Siliziumnitrid enthält.
  4. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei die Trennschicht (102) aus einer Schicht besteht, die Wolfram, Molybdän, Wolframoxid, Molybdänoxid, Wolframoxynitrid oder/und Molybdänoxynitrid enthält.
  5. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei die zweite leitende Schicht (106; 113; 123; 133) Aluminium, eine Legierung aus Aluminium, Europium, eine Legierung aus Europium, Ytterbium oder/und eine Legierung aus Ytterbium enthält oder Indium-Zinnoxid, Indium-Zinnoxid, das Silizium enthält, Indiumoxid, das 2 bis 20 Atom% Zinkoxid enthält, Titan, Gold, Platin, Nickel, Wolfram, Chrom, Molybdän, Eisen, Kobalt, Kupfer, Palladium, Titannitrid, Wolframnitrid oder/und Molybdännitrid enthält.
  6. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Schicht ist, deren Leitfähigkeit und Form sich ändern, wenn eine Spannung an die erste leitende Schicht (104) und die zweite leitende Schicht (106; 113; 123; 133) angelegt wird.
  7. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Lichtemissionsschicht einschließt.
  8. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Schicht ist, die so konfiguriert ist, dass sie Photostrom erzeugt.
  9. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, wobei das Element ein Speicher-Element, ein Lichteemissions-Element, ein photoelektrisches Umwandlungs-Element, eine Solarzelle oder ein Transistor ist.
  10. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 1, das den folgenden weiteren Schritt umfasst:
    Ausbilden eines organischen Isolierfilms über der ersten leitenden Schicht (104), so dass er einen Randabschnitt der ersten leitenden Schicht (104) abdeckt.
  11. Verfahren zum Herstellen einer passiven Matrix-Halbleitervorrichtung, das die Schritte nach Anspruch 1 umfasst.
  12. Verfahren zum Herstellen einer Halbleitervorrichtung, das die folgenden Schritte umfasst:
    Ausbilden einer Trennschicht (102) über einem Substrat (101);
    Ausbilden einer Schicht (103) aus einer anorganischen Verbindung über der Trennschicht (102);
    Ausbilden einer ersten Elektrodenschicht (104) und einer leitenden Schicht (181) über der Schicht (103) aus einer anorganischen Verbindung;
    Ausbilden einer Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, über der ersten Elektrodenschicht (104), so dass die leitende Schicht (181) teilweise freiliegt;
    Ausbilden einer zweiten Elektrodenschicht (106; 113; 123; 133) über der Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, um ein Element auszubilden, wobei ein Abschnitt der zweiten Elektrodenschicht (106; 113; 123; 133) an den Teilen in Kontakt mit der leitenden Schicht (181) ist, die durch die Schicht (105; 112; 122; 132) freigelegt werden, die eine organische Verbindung enthält; und
    Trennen der ersten und der zweiten Elektrodenschicht (106; 113; 123; 133) und der Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, von dem Substrat (101) an der Trennschicht (102).
  13. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei die Schicht (103) aus einer anorganischen Verbindung eine Isolierschicht ist.
  14. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei die Schicht (103) aus einer anorganischen Verbindung Siliziumoxid, Siliziumoxynitrid, Siliziumnitridoxid oder/und Siliziumnitrid enthält.
  15. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei die Trennschicht (102) aus einer Schicht besteht, die Wolfram, Molybdän, Wolframoxid, Molybdänoxid, Wolframoxynitrid oder/und Molybdänoxynitrid enthält
  16. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei die erste Elektrodenschicht (106; 113; 123; 133) Aluminium, eine Legierung aus Aluminium, Europium, eine Legierung aus Europium, Ytterbium oder/und eine Legierung aus Ytterbium enthält oder Indium-Zinnoxid, Indium-Zinnoxid, das Silizium enthält, Indiumoxid, das 2 bis 20 Atom% Zinkoxid enthält, Titan, Gold, Platin, Nickel. Wolfram, Chrom, Molybdän, Eisen, Kobalt, Kupfer, Palladium, Titannitrid, Wolframnitrid oder/und Molybdännitrid enthält.
  17. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei die zweite Elektrodenschicht (106; 113; 123; 133) Aluminium, eine Legierung aus Aluminium, Europium, eine Legierung aus Europium, Ytterbium oder/und eine Legierung aus Ytterbium enthält oder Indium-Zinnoxid, Indium-Zinnoxid, das Silizium enthält, Indiumoxid, das 2 bis 20 Atom% Zinkoxid enthält, Titan, Gold, Platin, Nickel. Wolfram, Chrom, Molybdän, Eisen, Kobalt, Kupfer, Palladium, Titannitrid, Wolframnitrid oder/und Molybdännitrid enthält.
  18. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Lichtemissionsschicht einschließt.
  19. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Schicht ist, die so konfiguriert ist, dass sie Photostrom erzeugt.
  20. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, wobei das Element ein Speicher-Element, ein Lichteemissions-Element, ein photoelektrisches Umwandlungs-Element, eine Solarzelle oder ein Transistor ist.
  21. Verfahren zum Herstellen einer Halbleitervorrichtung nach Anspruch 12, das den folgenden weiteren Schritt umfasst:
    Ausbilden eines organischen Isolierfilms über der ersten leitenden Schicht (104), so dass er einen Randabschnitt der ersten Elektrodenschicht (104) abdeckt.
  22. Verfahren zum Herstellen einer passiven Matrix-Halbleitervorrichtung, das die Schritte nach Anspruch 12 umfasst.
  23. Halbleitervorrichtung, die umfasst:
    ein erstes Substrat (101), das Flexibilität aufweist;
    eine Trennschicht (102), die über dem ersten Substrat vorhanden ist;
    eine Schicht (103) aus einer anorganischen Verbindung, die über der Trennschicht (102) vorhanden ist;
    eine erste leitende Schicht (104), die über der Schicht (103) aus einer anorganischen Verbindung vorhanden ist;
    eine Schicht (105; 112; 122; 132), die eine organische Verbindung enthält und sowohl über der ersten leitenden Schicht (104) als auch der Schicht (103) aus einer anorganischen Verbindung in einem Muster vorhanden ist, in dem die Schicht (103) aus einer anorganischen Verbindung teilweise freiliegt;
    eine zweite leitende Schicht (106; 113; 123; 133), die über der Schicht vorhanden ist, die eine organische Verbindung (105; 112; 122; 132) enthält, um ein Element auszubilden; und
    ein zweites Substrat (108), das Flexibilität aufweist und über der zweiten leitenden Schicht (106; 113; 123; 133) vorhanden ist, wobei ein Abschnitt der zweiten leitenden Schicht (106; 113; 123; 133) in den Teilen in Kontakt mit der Schicht (103) aus einer anorganischen Verbindung ist, die durch die Schicht freigelegt werden, die eine organische Verbindung (105; 112; 122; 132) enthält.
  24. Halbleitervorrichtung nach Anspruch 23, wobei die Schicht (103) aus einer anorganischen Verbindung eine Isolierschicht ist.
  25. Halbleitervorrichtung nach Anspruch 23, wobei die Schicht (103) aus einer anorganischen Verbindung Siliziumoxid, Siliziumoxynitrid, Siliziumnitridoxid oder/und Siliziumnitrid enthält.
  26. Halbleitervorrichtung nach Anspruch 23, wobei die Trennschicht (102) aus einer Schicht besteht, die Wolfram, Molybdän, Wolframoxid, Molybdänoxid, Wolframoxynitrid oder/und Molybdänoxynitrid enthält.
  27. Halbleitervorrichtung nach Anspruch 23, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Schicht ist, deren Leitfähigkeit und Form sich ändern, wenn eine Spannung an die erste leitende Schicht (104) und die zweite leitende Schicht (106; 113; 123; 133) angelegt wird.
  28. Halbleitervorrichtung nach Anspruch 23, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Lichtemissionsschicht einschließt.
  29. Halbleitervorrichtung nach Anspruch 23, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Schicht ist, die so konfiguriert ist, dass sie Photostrom erzeugt.
  30. Halbleitervorrichtung nach Anspruch 23, wobei ein Randabschnitt der ersten leitenden Schicht (104) mit einer organischen isolierenden Schicht abgedeckt ist.
  31. Passive Matrix-Halbleitervorrichtung, die die Halbleitervorrichtung nach Anspruch 23 umfasst.
  32. Halbleitervorrichtung, die umfasst:
    ein erstes Substrat (101), das Flexibilität aufweist;
    eine Trennschicht (102), die über dem ersten Substrat vorhanden ist;
    eine Schicht (103) aus einer anorganischen Verbindung, die über der Trennschicht (102) vorhanden ist;
    eine erste Elektrodenschicht (104), die über der Schicht (103) aus einer anorganischen Verbindung vorhanden ist;
    eine leitende Schicht (181), die über der Schicht (103) aus einer anorganischen Verbindung vorhanden ist;
    eine Schicht (105; 112; 122; 132), die eine organische Verbindung enthält und über der ersten Elektrodenschicht (104) so vorhanden ist, dass die leitende Schicht (181) teilweise freigelegt ist; und
    eine zweite Elektrodenschicht (106; 113; 123; 133), die über der Schicht (105; 112; 122; 132) vorhanden ist, die eine organische Verbindung enthält;
    ein zweites Substrat (108), das Flexibilität aufweist und über der zweiten Elektrodenschicht (106; 113; 123; 133) vorhanden ist, wobei ein Abschnitt der zweiten Elektrodenschicht (106; 11; 123; 133) in den Teilen in Kontakt mit der leitenden Schicht ist, die durch die Schicht (105; 112; 122; 132) freigelegt werden, die eine organische Verbindung enthält.
  33. Halbleitervorrichtung nach Anspruch 32, wobei die Schicht (103) aus einer anorganischen Verbindung eine Isolierschicht ist.
  34. Halbleitervorrichtung nach Anspruch 32, wobei die Schicht (103) aus einer anorganischen Verbindung Siliziumoxid, Siliziumoxynitrid, Siliziumnitridoxid oder/und Siliziumnitrid enthält.
  35. Halbleitervorrichtung nach Anspruch 32, wobei die Trennschicht (102) aus einer Schicht besteht, die Wolfram, Molybdän, Wolframoxid, Molybdänoxid, Wolframoxynitrid oder/und Molybdänoxynitrid enthält.
  36. Halbleitervorrichtung nach Anspruch 32, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Schicht ist, deren Leitfähigkeit und Form sich ändern, wenn eine Spannung an die erste leitende Schicht (104) und die zweite leitende Schicht (106; 113; 123; 133) angelegt wird.
  37. Halbleitervorrichtung nach Anspruch 32, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Lichtemissionsschicht einschließt.
  38. Halbleitervorrichtung nach Anspruch 32, wobei die Schicht (105; 112; 122; 132), die eine organische Verbindung enthält, eine Schicht ist, die so konfiguriert ist, dass sie Photostrom erzeugt.
  39. Halbleitervorrichtung nach Anspruch 32, wobei ein Randabschnitt der ersten Elektrodenschicht (104) mit einer organischen isolierenden Schicht abgedeckt ist.
  40. Passivmatrix-Halbleitervorrichtung, die die Halbleitervorrichtung nach Anspruch 32 umfasst.
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Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834327A (en) * 1995-03-18 1998-11-10 Semiconductor Energy Laboratory Co., Ltd. Method for producing display device
US7408263B2 (en) * 2005-05-03 2008-08-05 E.I. Du Pont De Nemours And Company Anisotropic conductive coatings and electronic devices
US7968382B2 (en) * 2007-02-02 2011-06-28 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
EP1976001A3 (de) * 2007-03-26 2012-08-22 Semiconductor Energy Laboratory Co., Ltd. Herstellungsverfahren für Halbleitervorrichtung
KR101345378B1 (ko) * 2007-05-17 2013-12-24 삼성전자주식회사 ＺｎＯ 계 박막 트랜지스터 및 그 제조방법
JP5367330B2 (ja) * 2007-09-14 2013-12-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び半導体装置の作製方法
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2009260313A (ja) 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
US8182633B2 (en) * 2008-04-29 2012-05-22 Samsung Electronics Co., Ltd. Method of fabricating a flexible display device
JP2010153813A (ja) 2008-11-18 2010-07-08 Semiconductor Energy Lab Co Ltd 発光装置及びその作製方法、並びに、携帯電話機
US20100253902A1 (en) 2009-04-07 2010-10-07 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and manufacturing method thereof
GB0909721D0 (en) * 2009-06-05 2009-07-22 Plastic Logic Ltd Dielectric seed layer
US8576209B2 (en) 2009-07-07 2013-11-05 Semiconductor Energy Laboratory Co., Ltd. Display device
JP5605097B2 (ja) * 2010-09-03 2014-10-15 ソニー株式会社 電子素子の製造方法
KR20120042151A (ko) * 2010-10-22 2012-05-03 삼성모바일디스플레이주식회사 플렉서블 디스플레이 장치의 제조 방법
US8905972B2 (en) 2010-11-20 2014-12-09 Perqflo, Llc Infusion pumps
US9780242B2 (en) 2011-08-10 2017-10-03 Ascent Solar Technologies, Inc. Multilayer thin-film back contact system for flexible photovoltaic devices on polymer substrates
JP2013065824A (ja) * 2011-08-29 2013-04-11 Sony Corp トランジスタおよびその製造方法、並びに表示装置
TWI527207B (zh) * 2011-10-21 2016-03-21 友達光電股份有限公司 可撓式有機發光裝置及其製作方法
US9136402B2 (en) * 2012-02-28 2015-09-15 International Business Machines Corporation High efficiency flexible solar cells for consumer electronics
WO2014022558A1 (en) * 2012-07-31 2014-02-06 Wayne State University Method of making flexible, foldable, and stretchable devices
TWI500077B (zh) * 2012-11-29 2015-09-11 Ind Tech Res Inst 軟性元件的取出方法及基板之間的分離方法
CN103855311A (zh) * 2012-11-30 2014-06-11 海洋王照明科技股份有限公司 有机电致发光装置及其制备方法
TWI497735B (zh) * 2013-10-25 2015-08-21 Iner Aec Executive Yuan 光電元件之可撓性電極封裝結構
KR102368997B1 (ko) 2014-06-27 2022-02-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 발광 장치, 모듈, 전자 기기, 발광 장치의 제작 방법
US10159786B2 (en) 2014-09-30 2018-12-25 Perqflo, Llc Hybrid ambulatory infusion pumps
FR3027155B1 (fr) 2014-10-08 2018-01-12 Ecole Polytechnique Procede de fabrication d'un dispositif electronique, en particulier a base de nanotubes de carbone
KR101629468B1 (ko) * 2015-01-30 2016-06-10 한국과학기술원 웨어러블 박막 소자 및 이의 제조 방법
DE102015114167A1 (de) * 2015-08-26 2017-03-02 Osram Oled Gmbh Leuchtdiode und Verfahren zur Herstellung einer Leuchtdiode
WO2017079008A1 (en) * 2015-11-04 2017-05-11 Ascent Solar Technologies, Inc. Multilayer thin-film back contact system for flexible photovoltaic devices on polymer substrates
KR101730537B1 (ko) 2015-11-30 2017-04-26 엘지디스플레이 주식회사 표시장치와 그의 제조방법
US10181424B2 (en) 2016-04-12 2019-01-15 Semiconductor Energy Laboratory Co., Ltd. Peeling method and manufacturing method of flexible device
KR102388701B1 (ko) 2016-04-12 2022-04-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박리 방법 및 플렉시블 디바이스의 제작 방법
JP6835644B2 (ja) * 2017-03-27 2021-02-24 積水化学工業株式会社 太陽電池
US10586925B2 (en) * 2017-04-17 2020-03-10 Tianma Microelectronics Co., Ltd. Release film, display device manufacturing method, and device
US11220735B2 (en) * 2018-02-08 2022-01-11 Medtronic Minimed, Inc. Methods for controlling physical vapor deposition metal film adhesion to substrates and surfaces
CN108493209B (zh) * 2018-05-24 2020-06-23 京东方科技集团股份有限公司 一种显示基板、显示装置以及显示基板的制作方法
CN109087936A (zh) 2018-08-24 2018-12-25 京东方科技集团股份有限公司 一种柔性显示基板的制备方法
CN110310914B (zh) * 2019-07-04 2021-12-31 京东方科技集团股份有限公司 一种柔性器件及其制作方法、柔性装置
CN112349839B (zh) * 2020-10-26 2022-11-01 东北师范大学 一种与光刻电极相兼容的本征可拉伸有机场效应晶体管及其制备方法
US11908723B2 (en) * 2021-12-03 2024-02-20 International Business Machines Corporation Silicon handler with laser-release layers
CN114656804B (zh) * 2022-03-03 2022-12-09 江苏圣天新材料有限公司 一种覆铜板用软性复合硅微粉的制备方法

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0730012A (ja) 1993-07-09 1995-01-31 Fujitsu Ltd 半導体装置
NO973993L (no) 1997-09-01 1999-03-02 Opticom As Leseminne og leseminneinnretninger
JPH11195487A (ja) * 1997-12-27 1999-07-21 Tdk Corp 有機ｅｌ素子
JP4877675B2 (ja) * 1999-06-28 2012-02-15 株式会社半導体エネルギー研究所 電気光学装置の作製方法
US6953947B2 (en) * 1999-12-31 2005-10-11 Lg Chem, Ltd. Organic thin film transistor
US6541910B2 (en) * 2000-04-06 2003-04-01 Seiko Epson Corporation Organic el display
JP2002032037A (ja) * 2000-05-12 2002-01-31 Semiconductor Energy Lab Co Ltd 表示装置
JP2002280187A (ja) * 2001-03-16 2002-09-27 Seiko Epson Corp 有機ｅｌ素子
US6900470B2 (en) * 2001-04-20 2005-05-31 Kabushiki Kaisha Toshiba Display device and method of manufacturing the same
JP4027740B2 (ja) 2001-07-16 2007-12-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
TW564471B (en) 2001-07-16 2003-12-01 Semiconductor Energy Lab Semiconductor device and peeling off method and method of manufacturing semiconductor device
US7351300B2 (en) * 2001-08-22 2008-04-01 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
JP4493905B2 (ja) * 2001-11-09 2010-06-30 株式会社半導体エネルギー研究所 発光装置及びその作製方法
JP3951701B2 (ja) * 2001-12-18 2007-08-01 セイコーエプソン株式会社 表示装置の製造方法、電子機器の製造方法、表示装置および電子機器
US7038377B2 (en) * 2002-01-16 2006-05-02 Seiko Epson Corporation Display device with a narrow frame
EP1343206B1 (de) 2002-03-07 2016-10-26 Semiconductor Energy Laboratory Co., Ltd. Lichtemittierende Vorrichtung, elektronische Vorrichtung, Beleuchtungsvorrichtung und Herstellungsverfahren der lichtemittierenden Vorrichtung
JP2003272827A (ja) * 2002-03-13 2003-09-26 Matsushita Electric Ind Co Ltd 有機発光素子及びその製造方法
JP2004047791A (ja) 2002-07-12 2004-02-12 Pioneer Electronic Corp 有機薄膜スイッチングメモリ素子及びメモリ装置
TWI272641B (en) 2002-07-16 2007-02-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
KR20040025383A (ko) * 2002-09-19 2004-03-24 삼성에스디아이 주식회사 유기 전계 발광 표시 장치 및 그 제조방법
JP2004127627A (ja) * 2002-09-30 2004-04-22 Semiconductor Energy Lab Co Ltd 表示装置
AU2003271178A1 (en) 2002-10-17 2004-05-25 Asahi Glass Company, Limited Multilayer body, base with wiring, organic el display device, connection terminal of organic el display device, and methods for manufacturing these
WO2004040648A1 (ja) * 2002-10-30 2004-05-13 Semiconductor Energy Laboratory Co., Ltd. 半導体装置および半導体装置の作製方法
US6905908B2 (en) 2002-12-26 2005-06-14 Motorola, Inc. Method of fabricating organic field effect transistors
JP4830254B2 (ja) * 2003-01-23 2011-12-07 セイコーエプソン株式会社 有機ｅｌ装置の製造方法及び電子機器
JP2004310051A (ja) * 2003-03-24 2004-11-04 Sony Corp 超薄型電気光学表示装置の製造方法および製造装置
US7141348B2 (en) * 2003-05-23 2006-11-28 Intelleflex Corporation Lamination and delamination technique for thin film processing
JP2005085604A (ja) * 2003-09-09 2005-03-31 Seiko Epson Corp 有機金属化合物の薄膜形成方法、有機金属化合物薄膜、およびこれを備えた有機電子デバイスの製造方法、有機電子デバイス、有機エレクトロルミネッセンスの製造方法、有機エレクトロルミネッセンス、及び電子機器
JPWO2005027582A1 (ja) * 2003-09-10 2006-11-24 富士通株式会社 表示装置及びその製造方法
JP4016144B2 (ja) * 2003-09-19 2007-12-05 ソニー株式会社 有機発光素子およびその製造方法ならびに表示装置
JP4748967B2 (ja) * 2003-11-04 2011-08-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20050183769A1 (en) * 2003-11-10 2005-08-25 Hiroki Nakagawa Method of producing substrate for dye-sensitized solar cell and dye-sensitized solar cell
JP4276603B2 (ja) * 2003-12-16 2009-06-10 セイコーエプソン株式会社 有機エレクトロルミネッセンス装置および電子機器
US7166399B2 (en) * 2004-04-14 2007-01-23 Xerox Corporation Photosensitive member having anti-curl backing layer with lignin sulfonic acid doped polyaniline
JP2005317476A (ja) * 2004-04-30 2005-11-10 Toshiba Matsushita Display Technology Co Ltd 表示装置

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CN104638009B (zh) 2018-07-10
US7745252B2 (en) 2010-06-29
JP2014199929A (ja) 2014-10-23
JP2013080935A (ja) 2013-05-02
JP5521021B2 (ja) 2014-06-11
CN1925187B (zh) 2012-06-27
CN102646793A (zh) 2012-08-22
US20070048970A1 (en) 2007-03-01
CN1925187A (zh) 2007-03-07
JP5917596B2 (ja) 2016-05-18
CN104638009A (zh) 2015-05-20
CN102646793B (zh) 2015-01-14
EP1760798A1 (de) 2007-03-07

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