EP1317777A1

EP1317777A1 - Semiconductor memory cell comprising a trench capacitor and a select transistor and a method for the production thereof

Info

Publication number: EP1317777A1
Application number: EP01962672A
Authority: EP
Inventors: Wolfram Karcher; Dietmar Temmler; Martin Schrems
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2000-09-15
Filing date: 2001-08-24
Publication date: 2003-06-11
Also published as: TW518751B; JP2004509469A; US20030168690A1; WO2002023636A1; KR100523881B1; KR20030038742A; DE10045694A1; US7049647B2

Abstract

The invention relates to a semiconductor memory cell (1), which is formed in a substrate (2) and comprises a trench capacitor (3) and a select transistor (4). The trench capacitor (3) comprises a capacitor dielectric (8) and a conductive trench fill material (10). A diffusion barrier (19) is located on the conductive trench fill material (10) and an epitaxial layer (24) is formed on top of said barrier. The select transistor (4) is a planar transistor, positioned above the trench capacitor (3), whereby a drain doping region (13) of said select transistor (4) is located in the epitaxial layer (24).

Description

description

Semiconductor memory cell with trench capacitor and selection transistor and process for its production

The present invention relates to a semiconductor memory cell with a trench capacitor and a selection transistor and a method for their production.

Integrated circuits (ICs) or chips use capacitors for the purpose of charge storage, e.g. a dynamic random access memory (DRAM). The state of charge in the capacitor represents a data bit.

A DRAM chip contains a matrix of memory cells, which are arranged in the form of rows and columns and are driven by word lines and bit lines. The reading out of data from the memory cells or the writing of data into the memory cells is accomplished by activating suitable word lines and bit lines.

A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains two diffusion regions which are separated from one another by a channel which is controlled by a gate. Depending on the direction of the current flow, one diffusion region is referred to as a drain and the other as a source. The drain region is connected to the bit line, the source region to the trench capacitor and the gate to the word line.

By applying appropriate voltages to the gate, the transistor is controlled so that current flow between the drain and source regions through the channel is turned on and off.

The charge stored in the capacitor diminishes over time due to leakage currents. Before the cargo turns on has reduced an undetermined level below a threshold value, the capacitor must be refreshed. For this reason, these memory cells are referred to as dynamic RAM (DRAM). A typical configuration of a semiconductor memory with a trench capacitor and a selection transistor is specified in the patent US Pat. No. 5,867,420.

A problem with the known DRAM variants is the generation of a sufficiently large capacitance in the trench capacitor. This problem will be exacerbated in the future by the progressive miniaturization of semiconductor components. The continuous increase in the integration density means that the area available per memory cell and thus the capacitance of the trench capacitor continues to decrease. Too little capacitance in the trench capacitor can adversely affect the functionality and usability of the storage device, since too little charge is stored in the trench capacitor.

For example, sense amplifiers require a sufficient signal level for reliable reading out of the information located in the memory cell. The ratio of the storage capacity of the trench capacitor to the bit line capacitance is crucial when determining the signal level. If the storage capacity of the trench capacitor is too small, this ratio may be too small to generate a sufficient signal in the sense amplifier.

A low storage capacity also requires a higher refresh frequency, since the amount of charge stored in the trench capacitor is limited by its capacity and additionally decreases due to leakage currents. If the amount of charge in the storage capacitor falls below a minimum, it is no longer possible to read out the information stored in it with the connected sense amplifiers, the information is lost and reading errors occur. ω

finds, is manufactured. The outdiffusion of the dopant typically extends over distances between 50 and 150 nanometers (nm). It must be ensured here that the dopant does not diffuse into the channel of the selection transistor, where it can lead to increased leakage currents through the transistor, which render the memory cell in question unusable. This means that a memory cell that is theoretically possible without out-diffusion must be enlarged by the size of the out-diffusion.

It is the object of the invention to provide a semiconductor memory cell with a reduced space requirement and improved storage time, and a method for its production.

The task is solved by a semiconductor memory cell with:

A trench in which a trench capacitor is arranged;

- A selection transistor, which is designed as a planar transistor above the trench capacitor; a capacitor dielectric, which is arranged in the trench;

- A conductive trench filling, which is arranged in the trench;

- a diffusion barrier, which is arranged on the conductive trench filling;

an epitaxial layer grown epitaxially over the diffusion barrier;

- A source doping region of the selection transistor, which is arranged in the epitaxial layer.

The arrangement according to the invention initially arranges a diffusion barrier on the conductive trench filling. The purpose of the diffusion barrier is to prevent dopant in the conductive trench filling from diffusing out, which could damage the selection transistor. What is new is that the diffusion barrier is horizontal. To the space used by the memory cell as possible

lying epitaxially grown epitaxial layer. However, the inner hole in the cover layer ensures that electrical contact can be established between the conductive trench filling and the source doping region of the selection transistor arranged in the epitaxial layer. Another variant of the invention provides that a conductive contact is arranged in the inner hole. The conductive contact is designed such that it contacts the conductive trench filling and fills the inner hole of the dielectric layer. For example, the conductive trench filling comprises tungsten, tungsten nitride, titanium nitride, arsenic or phosphorus-doped poly- or amorphous silicon.

Another advantageous embodiment of the invention provides that the conductive contact connects the conductive trench filling to the source doping region of the selection transistor. This arrangement makes a conductive contact between the trench capacitor and the selection transistor.

In a further advantageous embodiment of the invention, the cross-sectional area of the inner hole in the dielectric layer is smaller than the cross-sectional area of the trench. This configuration ensures that the trench can have a large cross section, and thus the trench capacitor has a large capacitance, even if the selection transistor is made relatively small. This enables a small source doping region, since the cross-sectional area of the inner hole is made smaller than the cross-sectional area of the trench, which can thus be adapted to the size of the source doping region. The small

Source doping region additionally has the advantage that the leakage current between the channel and the source doping region is reduced.

It is also provided that the insulating cover layer is designed as a lateral edge web. The formation of the insulating cover layer as a lateral edge web comprises for example, that the insulating cover layer is produced using a spacer technique. For this purpose, an insulating layer is deposited conformally on the surface and etched back, the insulating cover layer being formed as a lateral edge web in the trench.

Another embodiment of the invention provides that the insulating cover layer has an upper edge, and the diffusion barrier is arranged completely below the upper edge. The advantage of this arrangement is an inexpensive manufacture. Another advantage is that if crystal dislocations form at the interface, they cannot slide out of the contact area due to the dielectric annular layer.

A further embodiment of the arrangement according to the invention provides that the cover layer has an upper edge and the conductive contact is arranged above the upper edge. The advantage of this arrangement is a larger contact area and thus a reduced resistance, especially if a thin dielectric barrier such as e.g. 1 nm thick silicon nitride is used.

It is further provided that the diffusion barrier is arranged on the conductive contact.

With regard to the method, the object is achieved by a method for producing a semiconductor memory cell with: forming a trench capacitor in a trench which has an upper region and a lower region and is filled with a conductive trench filling; Forming a diffusion barrier on the conductive trench fill; - Epitaxial overgrowth of the diffusion barrier with an epitaxial layer; - Subsequently forming a selection transistor as a planar transistor above the trench capacitor, a source doping region of the selection transistor being formed in the epitaxial layer.

One embodiment of the method according to the invention provides that after an epitaxial overgrowth of the diffusion barrier, a reflow process is carried out at a higher temperature than the epitaxial overgrowth. The advantage of a reflow process is that the epitaxially grown silicon can planarize a surface due to the elevated temperature, for example through a flow effect, and growth defects can be cured.

Another advantageous embodiment of the method according to the invention provides that the reflow process is carried out with the addition of hydrogen. The advantage of this process step is that improved planarization and a further reduction in growth defects are achieved.

Further advantageous refinements are the subject of the dependent claims.

The invention is explained in more detail below on the basis of exemplary embodiments and figures. The figures show:

Figure 1 shows a trench capacitor with a selection transistor;

Figure 2 shows another embodiment of a trench capacitor with a selection transistor;

FIG. 3 shows a further example of a trench capacitor with a selection transistor, the trench capacitor being connected to the selection transistor with a conductive contact; FIGS. 4 to 8 show a manufacturing method for forming the memory cell shown in FIG. 3;

FIGS. 9 to 11 show a production method for forming the memory cell shown in FIG. 2.

A memory cell 1 according to the invention is shown in FIG. The memory cell 1 is formed in a substrate 2. The substrate 2 is usually silicon, which can be lightly p- or n-doped (10 ¹⁵ - 10 ¹⁷ dopant atoms per cubic centimeter). The memory cell 1 comprises a trench capacitor 3 and a selection transistor 4. The trench capacitor 3 is formed in a trench 5, the lower region of the trench 5 being surrounded by a buried plate 6. The buried plate 6 is a conductive layer that can be formed, for example, by introducing dopant into the substrate 2. In accordance with the basic doping of the substrate 2, which may have n- or p-doping, the buried plate is doped much more strongly with up to 10 ²¹ dopants / cm ³ . The buried plate 6 is electrically contacted by a buried trough 7, which is also a doped layer, which has the same dopant type as the buried plate 6. An insulation collar 9 is arranged in an upper region of the trench 5. The insulation collar 9 is usually formed from silicon oxide, silicon nitride or a silicon oxynitride. Furthermore, a dielectric layer 8 is formed in the trench 5, the layer 8 being buried in the lower region of the trench

Plate 6 insulated and runs in the upper region of the trench 5 on the insulation collar 9. The dielectric layer 8 is formed, for example, from a silicon oxynitride. Optionally, it can also be a layer stack made of silicon oxide, silicon nitride and silicon oxynitride. The dielectric layer 8 has the task of the buried plate 6 against a conductive trench filling 10, which in the Trench 5 is arranged to isolate. The buried plate 6 represents an outer capacitor electrode, the conductive trench filling 10 an inner capacitor electrode and the dielectric layer 8 the capacitor dielectric.

An isolation trench 11, which is usually referred to as STI (shallow trench isolation), is used to isolate adjacent memory cells, which are not shown in FIG. 1. The selection transistor 4 comprises a source region 12, a drain region 13 and a gate 14, on which a word line 15 is arranged. The source region 12 is connected to a bit line 17 with a bit line contact 16. Bit line 17 is isolated from word line 15 by means of intermediate insulation 18. The drain region 13 lies above the trench 5, the drain region 13 being connected to the conductive trench filling 10 by means of a diffusion barrier 19. The conductive trench filling 10 is usually designed as highly doped and thus low-resistance silicon. In order to prevent the doping of the conductive trench filling 10 from diffusing into the drain region 13 or possibly into the channel of the selection transistor 4, a diffusion barrier 19 is arranged between the conductive trench filling 10 and the drain doping region 13. In this exemplary embodiment, the diffusion barrier 19 is arranged planar on the conductive trench filling 10. The diffusion barrier 19 extends from the dielectric layer 8 to the isolation trench 11.

FIG. 2 shows a further exemplary embodiment of a memory cell 1 according to the invention. The difference from FIG. 1 is that an insulating cover layer 20 with an inner hole 21 is arranged on the conductive trench filling 10. In this exemplary embodiment, the diffusion barrier 19 is arranged in the inner hole 21. For example, the insulating cover layer 20 is formed from silicon oxide or silicon nitride or a silicon oxynitride. The diffusion barrier 19 contacts the conductive trench filling 10 with the drain doping region 13. Since part of the cross-sectional area of the trench 5 is covered by the insulating cover layer 20 and only the region of the inner hole 21 and the diffusion barrier 19 are contacted by the drain region 13, the drain region 13 and so that the selection transistor 4 are made significantly smaller. This has the advantage that a larger proportion of the substrate surface can be used by the trench capacitor 3, and thus the capacitance of the trench capacitor 3 can be increased.

A further exemplary embodiment of a memory cell 1 according to the invention is illustrated with reference to FIG. 3. The difference from FIG. 2 is that a conductive contact 22 is formed in the inner hole 21, which is arranged in the insulating cover layer 20. The conductive contact 22 is in turn covered with a diffusion barrier 19, so that the diffusion of dopant out of the conductive trench filling 10 through the diffusion barrier 19 is prevented. The conductive contact 22 is formed in such a way that it projects beyond an upper edge 27 of the insulating cover layer 20 and thus projects into the drain doping region 13. This ensures low-resistance contact between the conductive trench filling 10 and the drain region 13.

A method for producing the memory cell 1 shown in FIG. 3 is described with reference to FIGS. 4 to 8. With reference to FIG. 4, a substrate 2, which is, for example, a p-doped silicon substrate, is provided. A mask 23 is arranged on the substrate 2 and is used to etch the trench 5. The insulation collar 9 is then formed in the upper region of the trench 5 using the usual methods. The buried plate 6 is formed in the lower region of the trench 5 by introducing dopant into the trench 5. Since the substrate 2 is weakly p-doped, a high n-doping is chosen as the doping of the buried plate 6. The buried trough 7 can, for example, be ω C * to t μ ^{> 1}

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With reference to FIG. 7, the insulation collar 9 and the insulating cover layer 20 are etched back. This can be done, for example, with a time-controlled wet etching of boron hydrofluoric acid or a reactive ion etching with CF ₄ .

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P P ti P tr F- ti rr 0 Fl P μ. • F- Φ P Ω P X CQ P. 0 Φ X Ω

P μ- P μ- P- Φ P to • Pi P CQ P F- P P Ω tr P- Φ X P rt F- P P- tr

Hi N cn o -0 F- φ P- & Ω oil φ P 3 t) P | tr Pi ro F ¹ ro PP rT P φ Φ μ- N F- ro P Φ o CD Φ P rt 13 F- Φ p ff Φ P ω t. Ω P IQ Φ P cn t ff ti CD Φ μ- 3 Φ tra 3 α td Hl tr ro S F- φ P F- φ t Ω 0 LQ LQ rr p ⁱ PP μ- α P 03 03 P

03 CQ rt μ- Ω s tΛ rr JI LQ CD CD P -3 o ro P F- i Ω Φ 3.tr Ω Φ P P Ω p 0 tr P o P Φ 03 -3 Φ P rr μ- -

F- P P- P = Hi μ- PP μ- P μ- tr Φ μ- μ- X F- Ω F ¹ P φ ω P • d F- 3 Hl Φ VD P cπ

KPPP tr Hi rr P CQ φ 03 F- rr P. ro rt tr F- Hl Ω X P- PP μ- P = HP o = ω CQ Φ c P tr Ω Ö0 X P- μ- CQ P Φ P ro X CD φ Φ P- rr tr P Φ NP ff Φ ii 01 X Φ ff φ φ Φ φ P μ- P LQ F- (t? - i 03 P Ω rt POPP 3

Φ F- P ro -3 F- μ- P F- P rr tΛ φ P- ro Pi μ ^> ro F- Ω t tr tr Φ rr Ω rr ti

P P ti P 0 φ CQ Ω i to • φ rr tr tr P CD ff cn i = d ro ro X Φ P = P

P Φ Hi μ- Ω P ff cπ P Φ tsi μ- Φ P- F- H P F- 03 -3 CD P Ω p

Φ 3 ΓT tr 01 cπ rt 3 Pi P m <3 F> cn μ- Ω P- td Pi φ P X Pi

CD P- P CQ tr μ- μ- P- F- P -3 Φ tr P φ P P = CQ μ- X ro P P- to P ro CD μ- F- rt N p rr Φ to φ P P P σ. p. rt F- P P

1 CQ P-

Substrate 2 planarized. This is achieved, for example, with an RIE sinking process or with a reflow process. The epitaxial growth of the epitaxial layer 24 can also be improved in this exemplary embodiment by one or more reflow processes carried out in the meantime, as a result of which growth defects in the epitaxial layer are reduced.

Claims

claims

1. Semiconductor memory with:

- a trench (5) in which a trench capacitor (3) is arranged;

- A selection transistor (4) which is arranged as a planar transistor above the trench capacitor (3);

- A capacitor dielectric (8) which is arranged in the trench (5); - A conductive trench filling (10) which is arranged in the trench (5);

- A diffusion barrier (19) which is arranged on the conductive trench filling (10);

- an epitaxial layer (24) grown epitaxially over the diffusion barrier (19);

- A drain doping region (13) of the selection transistor (4), which is arranged in the epitaxial layer (24).

2. Semiconductor memory according to claim 1, so that the drain doping region (13) of the selection transistor (4) is contacted from below with the diffusion barrier (19).

3. Semiconductor memory according to one of claims 1 or 2, so that the diffusion barrier (19) is arranged horizontally.

4. Arrangement according to one of claims 1 to 3, so that an insulating cover layer (20) with an inner hole (21) is arranged on the conductive trench filling (10).

5. Semiconductor memory according to claim 4, characterized in that a conductive contact (22) is arranged in the inner hole (21).

6. The semiconductor memory as claimed in claim 5, so that the conductive contact (22) connects the conductive trench filling (10) to the drain doping region (13) of the selection transistor (4).

7. Semiconductor memory according to one of claims 4 to 6, that the cross-sectional area of the inner hole (21) in the insulating cover layer (20) is smaller than the cross-sectional area of the trench (5).

8. Semiconductor memory according to one of claims 4 to 7, so that the insulating cover layer (20) is designed as a lateral edge web.

9. Semiconductor memory according to one of claims 4 to 8, so that the insulating cover layer (20) has an upper edge (27) and the diffusion barrier (19) is arranged completely below the upper edge (27).

10. The semiconductor memory as claimed in one of claims 4 to 9, that the insulating covering layer (20) has an upper edge (27) and the conductive contact (22) is arranged above the upper edge (27).

11. Semiconductor memory according to one of claims 5 to 10, that the diffusion barrier (19) is arranged on the conductive contact (22).

12. A method for producing a semiconductor memory cell comprising the steps: - Forming a trench capacitor (3) in a trench (5) which has an upper region and a lower region and is filled with a conductive trench filling (10);

- Forming a diffusion barrier (19) on the conductive trench filling (10);

- Epitaxial overgrowth of the diffusion barrier (19) with an epitaxial layer (24);

- Subsequently forming a selection transistor (4) as a planar transistor above the trench capacitor (3), a drain region (13) of the selection transistor (4) being formed in the epitaxial layer (24).

13. The method according to claim 12, so that after an epitaxial overgrowth of the diffusion barrier (19) a reflow process is carried out at a higher temperature than the epitaxial overgrowth.

14. The method of claim 13, d a d u r c h g e k e n n z e i c h n e t that the reflow process is carried out with the addition of hydrogen.

15. The method according to any one of claims 13 or 14, so that the process sequence consisting of epitaxial growth and reflow process is repeated at least once.