EP1366517A2 - Semiconductor memory location and method for the production thereof - Google Patents

Abstract

According to the invention, a trench capacitor is formed inside a trench (30) that is arranged inside a substrate (20). The trench (30) is filled with a conductive trench filling (50) that serves as an inner capacitor electrode. An epitaxial layer (75) is grown on the lateral wall of the trench (30) on the substrate (20). A buried contact (60) is arranged between the conductive trench filling (50) with the second intermediate layer (65) and the epitaxially grown layer (75). A dopant out-diffusion (80), which is formed while leading out from the buried contact (60), is arranged inside the epitaxially grown layer (75). The epitaxially grown layer (75) enables the dopant out-diffusion (80) to be further removed from a selection transistor (10) located next to the trench whereby permitting the prevention of short channel effects in the selection transistor (10).

Description

description

Semiconductor memory cell and method for its production

The present patent application relates to a semiconductor memory cell and a method for its production. The semiconductor memory cell comprises a selection transistor and a trench capacitor which is formed in a trench.

Memory components, such as DRAMs (Dynamic Random Access Memories) consist of a cell array and a control periphery, with individual memory cells being arranged in the cell array.

A DRAM chip contains a matrix of memory cells, which are arranged in the form of rows and columns and are driven by word lines and bit lines. The reading out of data from the memory cells or the writing of data into the memory cells is accomplished by activating suitable word lines and bit lines.

A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor consists, among other things, of two diffusion regions which are separated from one another by a channel which is controlled by a gate. One diffusion region is referred to as a drain region and the other diffusion region is referred to as a source region.

One of the diffusion areas is connected to a bit line, the other diffusion area to the capacitor and the gate to a word line. By applying suitable voltages to the gate, the transistor is controlled so that a current flow between the diffusion regions through the channel is switched on and off. The progressive miniaturization of memory components increases the integration density continuously. The continuous increase in the integration density means that the area available per memory cell continues to decrease. If the selection transistor is formed, for example, as a planar transistor, the lateral distance between the selection transistor and the trench capacitor consequently decreases further and further. This leads to a reduction in the blocking capability of the selection transistor, which blocks more poorly anyway as the channel length decreases due to the short channel effect. The increased leakage currents discharge the trench capacitor prematurely, as a result of which the information stored in the trench capacitor and the memory cell is lost.

The short channel effects are enhanced by the diffusion of a buried strap. The buried strap is usually arranged in the trench capacitor above the conductive trench filling and serves to electrically connect the conductive trench filling to a doping region of the transistor. In this case, a diffusion of dopant from the buried strap into the substrate and the adjacent doping region of the selection transistor is usually carried out, as a result of which the electrical contact is formed. A disadvantage of a conventional buried strap is that it increases the short-channel effects that occur.

Another problem known from the prior art is that the doping region of the selection transistor must usually be formed in single-crystal silicon in order to avoid leakage currents through the selection transistor. Since the buried strap is usually formed from polycrystalline silicon, which adjoins the monocrystalline silicon of the doping region of the selection transistor, crystal crossings occur at elevated temperatures, starting from the

Interface between polysilicon and single-crystalline silicon in order to form in the single-crystal silicon, which can lead to leakage currents through the selection transistor.

A disadvantage of an epitaxially grown buried contact is that crystal dislocations are formed at the transition between the single-crystal epitaxially grown silicon and a polycrystalline grown silicon. This defect formation leads to increased leakage currents in the selection transistor. During the further manufacturing process of the DRAM, the dislocations slide and can short-circuit the selection transistor.

Manufacturing methods for DRAM memory cells with a trench capacitor and selection transistor are described, for example, in the patents US 5,360,758, US 5,670,805 and US 5,827,765 and U. Gruening et al. "A Novel Trench DRAM Cell with a Vertical Access Transistor and Buried Strap for 4 Gb / 16Gb", IEDM, 1999.

It is the object of the invention to specify a memory with a trench capacitor and a production method therefor, which enable an improved doping profile of the buried contact and an avoidance of crystal defects in the selection transistor.

According to the invention, the object relating to the semiconductor memory is achieved by a semiconductor memory having a trench capacitor and a selection transistor, comprising:

a substrate which has a substrate surface and in which a trench is arranged which has an upper region,

an insulation collar which is arranged in the upper region on the side wall of the trench,

a conductive trench filling, which is arranged in the trench, an epitaxially grown layer extending into the trench, which is arranged on the side wall of the trench, a buried contact, which is arranged in the trench and electrically connects the epitaxially grown layer to the conductive trench filling, and a first intermediate layer, which lies between the epitaxial grown layer and the buried contact is arranged.

One advantage of the epitaxially grown layer is that the dopant diffused out of the buried strap (buried strap) has a lower diffusion length in the epitaxially grown layer than in the adjacent bulk silicon in which the selection transistor is formed. This means that the dopant diffused out of the buried strap does not diffuse into the channel of the selection transistor, thereby preventing an amplification of the short channel effect in the selection transistor. The first intermediate layer has the advantage that crystal dislocations formed in the buried strap do not grow into the single-crystal substrate in which the selection transistor is arranged. This avoids crystal defects at the doping region of the transistor, whereby an improved transistor with low leakage currents can be achieved.

It is preferably provided that the epitaxially grown layer is arranged in the direction of the substrate surface above the insulation collar on the side wall of the trench. This improves the dopant profile of the out-diffusion above the insulation collar.

A capacitor dielectric is usually arranged in the trench between the conductive trench filling and the substrate.

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It is preferably provided that the trench insulation has an insulation layer which is arranged on the buried contact and on the facet. The insulation layer arranged on the buried contact and on the facet has the advantage that, in the case of a planar selection transistor, a passing word line isolated from the trench capacitor can be arranged on the trench insulation. In the case of a memory cell with a vertical selection transistor, an active word line for driving the cell transistor runs above the trench.

A further embodiment of the invention provides that the insulation collar consists of two layers that can be selectively etched to one another.

With regard to the method, the object according to the invention is achieved by a method for producing a semiconductor memory with a trench capacitor and a selection transistor with the steps:

- Providing a substrate which has a substrate surface and in which a trench is arranged, which has an upper region, an insulation collar being arranged in the upper region on the side wall of the trench;

- Forming a conductive trench filling in the trench, the conductive trench filling is then sunk into the trench;

- Exposing the substrate on the side wall of the trench above the conductive trench filling;

- growing an epitaxial layer on the exposed side wall of the trench; - Forming a first intermediate layer on the epitaxially grown layer; >) to t P ¹ P ¹

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LΠ o Lπ o LΠ o LΠ

* τ 1

P- P-

LQ LQ

C P

Hi hi

Φ

P P> to

CO 01 tr tr Φ

Ω Ω P- Φ P- tr tr 01 P P

P- Φ X φ

Ω P 00 0 tr 01 P φ rt Ω CL Hi tr φ Hl

P- P- P P-

P Ω co P

3 "<5" CL

CL rt φ rr P

Φ H O P

3 C Hi Hj LQ

P SU 01

Ω CL tr P LQ

Hi H P Φ

SD CL Φ CL 3 tr φ P 5D =

Φ Hi 01 φ tΛ

3 01 P- φ

Φ Ω tr P

CL TjJ φ CO

Φ P- H {3 O

01 rt P- Φ

SD rt> P-

Ω x rt P Ω

HS rt Φ 01 tr

(D P- Ξ φ tr 01 N SD Hj φ Ω P tr N

P tr Hj H- ¹ Φ x rt H- ¹ o SD ω Hj H- ¹

P P P-SD Φ

CL Hl P

Φ LQ CL 01 3

P Φ P P- P-

01 € P 01 rt

SD SD LQ rt rt Ω O Φ

0 tr Φ Hi P-

HS 01 P- "* P

01 Φ P Φ

** P φ

Hi 3

Φ

P Ω

INI H {

SD P- '

FIG. 9 shows the arrangement from FIG. 8 for a memory cell with a planar selection transistor, trench isolation additionally being formed,

FIG. 10 shows the arrangement from FIG. 8 for a memory cell with a vertical selection transistor,

FIG. 11 REM image of a memory cell according to the prior art,

FIG. 12 SEM image of a memory cell according to the invention,

Figures 13 to 17 a variant of that in Figures 2 to

6 illustrated process flow,

Figures 18 to 20 a variant of that in Figures 2 to

6 illustrated process flow and

FIGS. 21 and 22 process steps for filling an annular gap between the epitaxial layer and the insulation collar.

FIG. 1 shows a memory cell 5 which comprises a selection transistor 10 and a trench capacitor 15. The selection transistor 10 and the trench capacitor 15 are formed in a substrate 20 which has a substrate surface 25. A trench 30 is arranged in the substrate 20, in which the trench capacitor 15 is formed. The trench 30 has an upper region 31.

A capacitor dielectric 35 is arranged in the trench 30. A buried plate 40 as an outer capacitor electrode is arranged around the trench 30 in the substrate 20. The buried plate 40 is contacted with a buried trough 45. Both the buried plate 40 and the buried trough 45 are doped in the substrate LO LO to to P ¹ P ¹

LΠ O LΠ o LΠ o LΠ α 01 P ta 0 3 ^ CL Φ cn

P- rt 3 Φ CL o 0 tr SD P- TJ φ 0 HS Φ X 3 P- ¹ tr P φ

H Φ HS P- CL P- Φ Φ p-

H-> Hi P- SD CL φ Ω P- Ω

Φ X P α P tr er

P- o φ co P- 01 Φ P- P Φ rt P P φ Φ SU l-i P rt Hi

Hl NP ¹ P- rt Ξ Φ N

SD = φ td o Φ P 0 Φ CL HS Φ tr P φ X H $ P- φ pr

P- rt HS P- rr co CL 01 P SD H- ¹

LQ Hi Φ CD H P- P- φ P Φ

Φ SD P- r P- P ¹ φ Ω rt P rt Ω. X P- P- HS Φ

Ω P- tr SD N Φ 01 SD P-

HS 0 Od P- X rt σ P ¹ 01

SD P P- Φ 3 P rt Φ o rt tr P P- P- H <CL P LΠ φ <; r y P-SU φ

P o CL CL P- X 01 LO SD P-

Hi P φ Φ Φ rt P o P P

P = 3 HS P- 3 co H φ

P "Ό P P- P er ≤

H- ¹ co <! Φ CL LO tr P- Φ Ω

P 0 P φ Hj LΠ 01 P P- H!

P CL r Hi rt φ 01 SD

LQ φ 01 LQ α Φ P HS P- rt tr

HS rt Hj P- P- 3 SD P • Φ

LΠ HS SD Φ P Hi rt P o P SD tr p- ¹ SD σ P- rt Φ φ co ta to P- 01

P- ö P X P- rt o φ 0

CQ 0 t φ rr rt rt o P Hi P- tr SD Ω tu

P- P- N Φ P Hj rt tr Φ 1d N P- P- 01 SD P- φ Hj P- P- P ω tr 0

P- 01 P SD rt 3 Ό co Φ P

01 rt rr 5D = 0 P- P- P

CL 0 CL rr rt X Φ H- ¹ P- P ¹

P- Hl φ Φ 01 P- P- 01 o φ Hl 3 X P 01 N 0 o

» ⁾ > O P- S P- H- ¹

01 SD φ o P rt Φ P SD SD

£ P P- 01 H (P- 3 rt P φ LQ P tr rt P- 01 P- LQ

P- Φ Φ SD SD CL φ LQ 0 φ

01 o P P ^ Φ P 0 φ HS tr CL rt φ tr Hi

CL o Φ Φ> -. P- P- P ¹ CL

SD 3 er P- ¹ • * SD 3 o P

P φ Φ rt P CL o φ

01 rt CL rt co Φ rt α Φ P- SD P- rt Hi »

TJ P- o 01 φ SD

0 01 r o P- LQ CL rt P- 01 LQ X N α rr P- φ P- Hj P- P- SD φ

1 HS Ω 0 = CL P 01 1 er 1

LO LO tt P ¹ P ¹

Lπ O LΠ o LΠ o LΠ co 01 P LO

Ω Φ P O er P CL

P- X g

Ω rt P er. P H {rt Hl CL

Φ> Φ

P P φ

Hl P- tr

P P Φ

P CL φ HS Q Φ Φ φ Hi φ P-

0 HJ rt

HS O 01 01

CL tr rt

P Φ Φ φ Hj P- rt Hl W φ

«P ^J P-

P = P H- ¹

Ω co φ er φ P-

Φ P rt

X Hl to rt P =

LΠ P- tr φ P-

CL Hi LQ

Φ Φ φ co

P »Ω

CO P "Hj

P o P tr tr

01 P- Φ rt P P

Hi St.

P CL P rt φ H- ¹

01 P

P to Ω P o ^ LQ

P

01 tr LΠ

P- φ o

P P

CL Φ

LO P-

2 o P

P LQ

01 Φ Φ

X P- Hh

Φ P P

P LQ ¹

Φ I- ¹

1 rt

If, for example, a planar transistor is arranged next to the trench capacitor in later method steps, the first recess depth 110 is formed approximately 100 nm below the substrate surface 25. If a vertical transistor is arranged in the trench capacitor, the first recess depth 110 is sunk into the trench 30, starting from the substrate surface 25, about 350 nm deep.

For the memory cell with a planar selection transistor, a passing wordline is arranged on the trench isolation (STI) and the active wordline runs next to the trench in order to drive the planar selection transistor there. This is described in more detail with reference to FIG. 9.

For a vertical selection transistor, the active wordline is arranged above the trench in order to contact and drive a gate arranged in the trench. In this case, the passing wordline is arranged next to the trench.

With reference to FIG. 3, the dielectric layer 35 is then removed. This can be accomplished, for example, by wet chemistry, using, for example, hydrofluoric acid buffered with ethylene glycol (HF / EG) to remove a dielectric layer consisting of an oxynitride.

With reference to FIG. 4, the conductive trench filling 50 is sunk into the trench 30 to a second recess depth 115. Part of the dielectric layer 35 is thereby exposed.

With reference to FIG. 5, the insulation collar 55 is then removed from the side wall of the trench 30. The insulation collar 55 remains on the side wall of the trench 30 where it passes through the dielectric layer 35 LO LO to to P> P ¹

LΠ O LΠ o LΠ o LΠ

H LQ er P- Pd tr Ω

P = Φ Φ 3 φ 0 P er Hh P P Ω

HS P Φ X tr rt tr P- P- rt <

HS 01 3 P- <P

Ξ rt rt Φ 0 P • o

Φ ~ 3 P pr 0

Hi Z. co P P

CL Φ tr td X P HS

Φ HS φ P P 3

P CL P rt 3 α

Φ Ω 3 .— »Φ

P Φ tr φ ci • d

• P- 1 HS ec 0

P Pd <01

> Φ Φ 3 P-

P Hj P 0 = rt

Ω X LQ 3 P- er H rt H- "P- 0

Φ 0 P- rt P

CL 3 HS Ω

Φ O ^ tr LQ _— _^

HS Φ • φ? 3 i-i CL HS P] td P φ a P- Ω

P rt HS tr 3 rt P Φ LQ

Ω ti Hh P φ - s er P co 3

1 N HS 0 σ πd Ξ cn Φ

HS P- 3 X P- P-

0 01 Φ P H- ¹

N Ω tr P P -j

HS er HS P P o ta Φ o

P P CL P o

X H- ¹ P- P Ω

P LΠ 01 φ CL

P o tr

P o φ 01 s. P- o P- Φ P 01

P- n P H- ¹ 01

P φ φ 01 o

P P X φ LΠ c P rt HS o w CL s: P- 01 o

<P <rt n co Hh Φ 0

CL o Φ Hh P-

P o HS M Hh P ri 0 • Ö

Ω Ω <P- P- P tr 0 rt P H- "

LQ CL HS P rt φ P LQ X CL Hj

1 ι-i φ P- Φ P

Ω 01 Φ HS er φ

1 1

LO O tt P ¹ H

LΠ o LΠ o LΠ O LΠ

-o> = ≤ ≤ CL cj P ¹ ≤ <! 01 cn s PN Hh N 01 0 s: N CO P- rt 01 rt> tr Φ co 01 tr cd

LΠ rt P- Φ φ 3 to P- P- rt o P- P P P- * CL P- Ω 01 P • d P P P- P- P Ω P- φ

N Hi HS HS LΠ Hi Φ Hi rt CL φ H- ¹ CL P- Φ HS P- er rt X P- X 01 H- ¹ P tr er P- co C CL CL CL HS P LQ P- P- ¹ φ HS 01 P- rr Φ rt Ω CL Φ 01 P- CL

TJ P Φ Ω Φ Φ rt rt φ td P rt 01 p ^J • Ω Ω Φ P- * P- tr Φ 3 rt Ω Φ C

P LQ 3 ι-S 3 P er φ tr φ P Φ H 01 3 tr er P- co 01 01 P ⁴ rt H {er P Φ

Ω s P rt φ to P- N 01 <; P- z φ X φ rt P Ω rt φ rr P- P Φ s Ω P- S P rt 3

Φ Hh tr <Hi P- W o H- ¹ PN 0 t φ er φ s- P- rt 01

HS HS 01 ≤ φ Φ Φ 01 P- CL LQ CL ≤ HS P P- P φ 01 -o P- ta P- P 0 er P->

Φ Ω 0 P HS ι- {Ό PP Φ φ P- LQ P 01 HS Ω LΠ rt P 01 P Φ ti X tr Φ Ω P o P- er tr LQ P P- 01 P rt P 3 01 φ 01 φ tr tr tr φ c P CL Φ Φ HS tr Hi rt LQ H- ^J Φ LO HS rt Φ φ CL ~ P Ω 01 P- 1 Φ P- 3 Φ Hi Hh CL Hi P Ξ

Φ Φ P- P- o P • H- ¹ P Hh LQ tr φ s: P P- Ω 0 = Hi LQ 3 LQ Hh PLP tr P = φ tr 01 X P- P- H- ¹ Φ rr P- o P- he LQ 3 Φ P- Φ £. <! P * 01 P- Ω

Φ rt ta NN φ s: rt PP ^ Φ P Φ N r X rt H- ¹ P- s; rt t. P- 0 P = - φ tr

PN Φ PPP Φ P- CL P- P- 01 P P- Hh H {P P- CQ P rt P HJ P Ω CD tr rt PPP φ P- Φ CL φ LQ Ω Ω CL Hi P- P ^ Ω Ω Ω Φ Ω CL tr: ^> P Φ

~ CL P =: P 01 H φ 3 P tr tr P CL P o er tr tr H- ¹ er Φ 0 PP φ Ω Ω φ Φ 3 HS Φ P- CL o 3 tr • Φ 01 01 01 CL LΠ CL rt

P- Z ≤ er er tr P Ω P CL p P φ 01 φ φ P- to PP = CL tr 0 P- CO 01 0 CL P ¹ Ω Φ co t ta Φ P- co φ 2! o P Φ P Φ Ω LΠ HS ^ Φ

Φ tr Hi rt rt P P- LO Hi P- s rt Hi rt rt er φ X φ P- Φ HS Ω HS

P Φ CL rt φ LΠ P 01 ≤ P CL HS P- 01 Φ P- P- P P P Φ P P er P-

, P- φ 3 P tr Ό P- rt cn P-? ^■ P- LQ P- P rt CL Φ HS CL P Ω Φ

CL P- P- X φ P- Φ P- Hi Φ LΠ φ O CL Φ Ω φ P co HS co 01 CL Φ er O td P Φ P rt rt HS PP φ CL HS tr er <HS rt Ω Ω rt LQ P- Φ P-

P- P Hi 01 P- LQ φ P CO 0 Φ P- 'rt tr Φ Φ CL P P rt

P rt f Φ cn rt a. LO co PP p ^J HS H Ω tr ι-i 0 P- tr P- LQ Φ φ P

Φ Ω P P- o Φ Φ O 5 ^> P H- "Φ co rt P- tr Φ _^ <P Ω φ Ω rsi Φ H {s; X

Φ Hi Hi PPP φ Ω P- rt 01 rt P- P- Φ tr HS tr s- P ^> P rt

HS tr PX Φ P ¹ NP P- er LQ Ω φ P- P Ω 01 CL HS CL rt 3 rt P- P = co P Ω P-

PP σ φ Hi P Ξ Ω r 01 Hh Φ er H- ¹ P tr Ό P Hh φ P- 01 er φ Ω tr co φ P ¹ Φ H {P P- HS LQ φ 0 tr N rsi P- P rt P - ta P HS CL 01 ^ 1 Ω Φ P- Φ CD Ω

P tr PXX 01 P φ P- Φ s N P- φ er P Ω LΠ tr HS rt rt rt tr rt P- 0 φ Ω σ 01 πd LQ H- ¹ P- P- P- rt er H- ¹ Φ Hj φ HS he P Φ rt P

Φ CL LO P P i-i er Φ Ω 0 Φ CL rt 01 CL HS P CO P- Φ TJ Ω Φ LQ P CL P Φ 3 P

CO Φ O Hl Hh φ P tr "P Φ P- Ω P- P ≤ P P P- tr P Φ 01 Φ 01 P

HS CL 0 HS P P- ^ CL rt LQ ¹ LQ CL CL Φ Φ rt LQ tr Ω HS PP ¹ Hi Hl

3 φ Φ 01 Φ Φ 01 φ φ Φ P- N P φ 3 P- tr P t LQ

& Φ P- 3 3 P- Ω P- CL P- CL t. P- P φ 01 co P X Hi P- P- co CL ui O Φ

01 τ_J rt Φ tr P Φ H- ¹ Φ Φ P 01 P- -3 P φ Ω Hi rr P = rt CL Ω PP 3

Ω P- Ω PN P- LQ P P- HS HS Ω LQ 0 tr P- tr HS φ tr tr CL P rt P er rt Φ HS P Ω Φ N CL Φ pr- PC P- Cd 01 HS P- rt rt 01 φ P Φ Ω

Φ P P- P co tr 01 P- <Φ P- P- φ Hh ec 3 Ω P- Ω rt CL. rt co 01 P er

P- XP tr Ω LQ rr φ P- P Φ PP Ω rt HS P- he H- ¹ tr P- ^ 1 HS LQ ω

CL rr Φ Φ er φ P Hi 3 Hj Φ "• P Φ Φ rt CL ≤ Φ ö o P Ω Φ CL Φ

Φ P- H $ P P- 01 <X CL LQ 3 rt 3 P- P P φ H {P- rt HS tr Φ P

3 01 Ω rt o rr P HS t? D N P P P P Hi P Φ P O P Φ ti Φ

Ω LQ LO er P P P P P T ι 01 P φ tr LQ Hi CL P 01 P σ tr P P

Φ tr Φ O rt £ P Hh tr Hi o s: LQ LQ φ LQ Hi Φ Φ CL td

P- φ HS rt CL P- CL φ o P- o CD 3 Φ CL Φ P X Hj P O co

PP P- LQ LQ Φ φ H CL 3 NC ω H- ¹ P- Φ CD φ € CL P CL Hh 01 <P- Ω

Φ Ω Φ φ P Hi CL P φ φ Φ P rt Hl P rt Ω Hi P φ P Φ P- "0 rt tr

Hi CO er tr Hh ^• »• P 3 ta CL HS CL P er Ω M ri P HS P = LO PP P-

Ω rt P- P = ^ Hi P ^! CD Φ P H- ¹ P- Φ er tr Ω OX Ω

X tr Φ P- "XP ö CO 0 Ω CL tr 3 tr H- ¹ Φ Hi 01 Φ Φ tr Φ tr CL P- er

0 P- rt CL P Ω P φ P P tr P- Φ 01 φ P- CL CD φ P • d Φ 3 Φ 3 φ Φ rt

P Ω Φ Φ r P Φ r P- tr rt HS φ P P- P- 01 φ rt P 01 P- P- P- P- Hj 1

1 er P rt P rt φ P 1 P P- 1 H- ¹ 1 Ω P φ φ o 1 1 1 LQ rt ι rt rt P- φ X rt P- tr PP φ LΠ Φ rt rt 1 Φ 1

LO LO to t P ¹ P ¹

LΠ O LΠ O LΠ o LΠ

Ω P ¹ P td P HS LQ SL 3 td rt H- "cn O P- tr rt <P <! Tr CL CL sΞ CL N CO CL S Hh

P * «d HPH {P Φ Φ Φ P- Φ Hi Φ 3 01 P Φ p- Φ Φ Φ φ PP P- d • dd P- 0 0 rt LΠ Hl H rt Hh LQ P rr H {rt p- P P- Φ P rt H- ¹ P- Hj HS Hi P 3 ta Ω Hh P Φ * -i rt P ti φ O P- P- Φ P- 01 3 rt P- P. tr CL 3 CO tr Hl P = P- Ω rt 3

1 P CL - - 0 P LQ P- H- ¹ P u> d 01 d Ω P tr q P-> CL CD P Ω Ω er cd P φ

O P φ P CL φ P CL P Φ P- P- P tr HS σ CL P P Φ LO P P- Φ P er tr LQ Φ X P

X LQ Hi tr 01 P tr Φ Ω N φ 01 LQ Φ φ P- Φ Hi CL rt CL O 01 φ P CL CD Φ Φ N rt

P- Φ Φ 01 P Φ CL rt tr P rt ι-s P φ HS rt Φ Φ Φ • * s: φ P- rt Hj Hh d co

CL O Φ N Ω LQ P φ Hi LQ 0 PN 01 Hi Hi PP φ φ NP = LQ H- ¹ Ω

Hi O Φ tr 01 HS 0 P HS Φ φ H φ α P- X S tr Hj cn HS ≤ Φ er P tr

P ¹ CL P- P- P- LQ P- PP tr H- ¹ Hi P 01 PP Φ CD Ω r P- H- ¹ n PP P-

J ^ P rt Ω Ω φ 0 HS LQ P Hl P φ H- "P rt rt PP rt rt tr - HS rt d X Ω cn φ P tr tr 3 tr CL Φ Hh PP Φ P & Φ CD rt CL HS φ P- CL Φ - Hi φ tr rt XP rt P = Φ P CL N 01 0 HS CL Ω φ 01 Φ P Ω £, HS rt

P-. rt Φ ta P CL * i Φ P CL tsi P- HS X P tr Ω P P tsi tr 0 α 3 CL *! Hi

01 P- rt P ¹ ö P- HS oi φ P 01 CL P er H- ¹ P ¹ tr 01 s rt tr 0 P- P- P- HS P- rt O 01 LO P- LQ P Φ LQ rr 3 rt PP Φ P- o P- P- Φ rt rt φ LQ φ P tr Ω €. o 01 φ N P- P Ω Φ <! OP rt P- Φ LΠ P- P 01 01 ^ 1 P- P- P P- φ Φ tr P- rt PPP HS HS P Ω φ HS P Φ ~ ta Φ HS et Ω LΠ Φ • d P = HS. CL

P- H {HS P P P Φ HS HS LQ Φ LQ ta N 0 tr CL HS tr φ

P tr P CL PPP P- <;P> tr Hj P <PP ¹ CL P Φ Φ X HS φ P Φ CQ P P

P P • LQ P P 01 Φ O Φ P tr 0 φ P- o P CL tr P P P P HS rt P P-

Ω H- ¹ Hh Φ Hh rt rt HS P φ tr 01 LΠ ta P- CL PP ¹ 01 CL 0 P Ω Ω

P tr LQ o O Φ rt P- P- P Φ rt 3 P o Ω α Hh H <er φ HS rt Φ r iS CL P σ P- 01 01 ü 01 P CL CL P- CL 3 tr CL o Hl φ Φ HS P

Φ CL ≤ Φ CL φ Φ X rt 0 P- P rt tr Φ P- rt φ P- φ P P- P rt 3 ti CL tr

Φ P HS P 3 <P- P H- ¹ φ PP = CL Φ HS φ rt HS Hh P Ω 01 P- P s φ φ

P> Hi Ω tr Φ Φ 01 H- ¹ φ P LQ P Φ P- cn - CL Hi Hh tr φ P> Φ PP ι ⁾ tr P rt <H Ό Φ P- rt • d φ CL 3 01 Ω N P - Φ Ξ rt cn HS 01 P P- o ii CD φ 0 = P- HS P P- P 0 P- * HS ^ H- ¹ P- CL X Φ P CD 01 01 P LO

C ^Q Φ tr HS Hh φ Φ 0 01 Hi LQ Ω P- P Φ P- P P- rr P- ^ 1 σ rt CL s φ P o

P 0 P CL LQ Hh P ⁴ H_ P oi CL Φ HS Φ tr P- N CL Φ φ 01 o 01 0 Φ P co

P φ CL P- HS Φ 01 Hj P- PPP φ rt P- φ rt rt Hh 3 er N Ω tr QP 3 Φ φ PP ≤ PP φ φ tr 01 P Φ P 3 Ω P- φ HS Hl H- ¹ d tr P-

Φ rt HS tr rt φ P o CO HS rt Φ z P- 3 HS PP P- P <rt HS H- "H- ¹

0 P- CO P φ P- CD HS H Φ • - ö P φ 01 IM 0 NP H- ¹ P rt P- φ Hi P- CL

HS 0 Ω MPP P- 01 P- CL HPP P- 0 ZXP tr CL 01 Φ P Hi P ^► *] φ φ

CL P tr 01 Ω φ Ω φ 01 P CL P r LO 01 H- ¹ P- P- P Φ Φ P t LQ P Φ ta rt

P 01 P- o tr P tr rt P Φ 3 φ O φ P 01 CL P = P 3 CL o CL HS 01 HS φ φ 01 Ω P φ 0 PP P- r Ω Ω P- P- LQ P- P P - rt PP rt Ω tr PPP P- HS LQ PS! CL N CL P- er P tr 01> Φ HS CL φ tr 01 P- CL d

_^ tr rt rt H- ¹ 0 LQ P LQ 0 Φ P- PP 0 φ P CD 0 P 0 = P- φ rt LQ P

P- P- 01 P P- CL Φ HS P 01 NPP Hh rr H- ¹ 01 cn ta Hi φ PO d <

CL Ω O rt <! σ P P O rt rt σ P 01 LQ P €. Φ Φ Hi • d φ Hi 3 φ CL

P tr LΠ PP] PO φ HS HS • d P- P ¹ Ω φ Φ rt P P- Hi P P- P LQ HS φ

01 rr 01 0 X P X CL LQ CL Φ -> CL LQ o tr Hl P- P- p- rt φ P rt LQ Hi P

Φ 01 T3 rt P φ φ P P- P P- CL φ o P- P = P 0 φ P CL P Φ Φ P

3 P> P- Ω 1 α P 3 co φ rt P Φ Φ φ Ω P rt P P- X o Φ P- tr <!

P- LO P tr <T \ P rt rt PPP P- P er H- ¹ Ω HS φ r P P- P HS φ rt o P- HS o rt Ω Φ • P Hj P • »LQ P rt rt ri P "PP Fr Hi P- rt LQ Φ φ HS

- Ω Ω φ Ω Φ HS LQ φ X P LQ P o P P 01 rt 01 P P HS P LQ

Φ P tr P φ Hi 01 P H- 'P rt P φ φ cn ≤ tr o 01 CL rt Ω X Φ 01 l-i

P- P rt rr Ω P- P er rt P- P- 3 rt 0 LΠ P- Φ P- P r rt rt ö 01 P

P Φ Φ tr P Φ <φ - 01> <; - Hi HS P 3 01 CL P σ Ω tr

Φ tr 1 P "1 Φ P Φ P rt P Φ CL CL P CL P- rt φ CL P P cn 01 tr φ

Hi Φ O O o P- HS tr 01 P- Φ P P LQ rt 0 01 CL o P- g HS P

PX o XHP Hh LO Φ N 5 ^» s; φ P- φ rt Φ H <! PHP 1 P- φ

P- P- 01 LQ P o P- P P o P rt Φ <P = Φ Ω O Hi LQ P CL rt p

CL CL P- CL O tr 3 tr Φ ι-i 0 rt P- P ¹ HS P Ω φ d rt φ 01 1 1 rr P 1 HS N 1 o P tr 1 01 φ

3 rt 1 1 1 rt 1 1

LO LO to to P ¹ P ¹ σι O LΠ o LΠ o LΠ

CL <α P H rt P tr Td tsi <01 01 cd ≤ Ω Pl co CL P 01 01 3 rt -3 01 O CD d 0

Φ P- φ P- Φ P- P- P P- H {Φ r P- d P P rt Φ 3 rt rr P- d 0 P- P- X P P r

P LQ HS φ Φ 0 01 01 0 Φ HS Φ P Ω φ 0 P LQ P Φ rt P Hj P Φ 0 CL φ

01 P Hh P Hl P - N P- 01 P CL X tr Hi <τl Hi φ P ¹ LQ rt CL Ω ^ H (

P Hj P φ P Φ 01 to Φ τ3 01 N P- d 0 -> φ tr - P- CL tr rt tr HS CL »X CL o ta <PN CL CO φ φ LQ 01 P Hi <r P- P Φ P φ LQ φ P

O to HS 01 Φ HS Φ P P P C P P- P P 'd Ω rr CL Φ Φ P P P- d P- Φ d P

H {Φ rt HS tr P 01 CL er HS P P- PP "Φ H- ¹ HS tr Φ 3 HS 3 Φ LQ rt Hh CL P- HJ tr

CL CL P Φ φ P- LQ 01 P P- P 01 X P- P Φ P = Hj Φ 01 3 Φ d φ P <!

P- φ 01 01 φ Φ Hj PPP Ω Φ NP ¹ CL rt Φ F 0 P CL P Φ P ¹ Φ L

Φ Hi 01 <co PP LQ PP LQ tr P- cn CL t P- CL Φ rt 0 H HS LQ Φ Hj P ¹ Hj Φ t-> rt P Ω N 01 Φ Hi rt Φ Φ d Ω P LQ Φ PN Ω 01 CL Hi T rt 01

Φ K P HS tr P K 01 Φ P P CL 3 tr HJ P- Φ HS d tr O P P- o CO P- P-

X 0 CL P- P- φ O rt CD P 01 P P- LQ 01 3 CO PP "Φ 01 to • d 01 X Ω rr P P- P Ω CL P- P φ P- <! Ω HS d Ω Φ rt P- LQ PP rt rd •! Φ rt P Hi

Hi CL PP tr Φ P CL PN Φ tr LQ P tr ω X P- H- ¹ φ 3 rt σ CD P- H- ¹ P

P- φ 3 rt rt Hj LQ φ P "CL P HS P- Φ CL rt rt Φ 0 = P P- P P- P- Φ 01 P- Ω Φ Φ tr

X P Φ φ P rt 3 Ω 01 Φ P- 3 X N 0 0 01 P- rt tr P- P Φ

P 01 LQ er CL tr 01 P- CL P- tr rt CL ^ 1 P P Φ P- d er P rt P Hj P- Φ P P

3 P φ LQ φ Φ HS P P φ Φ rt Φ P- Π Φ P d P Φ 01. P N Hj Φ> 01

01 rr 3 Φ P Hj P rt Cd 3 CL H- ¹ φ rt> P 3 CL Hj X c rt P- N d

0 P = 3 0 = Ω O Φ CL Φ -o. <! - d S! Φ HS Pd P3 0 d Φ Pd 01 <

LO HS ta P = rt Pl tr HS P- Φ P- P o rt φ φ 01 0 P <PP Φ Pl tr 3 H- ¹ M ≤ φ

LΠ ta P- 01 rt CL CL PP • TJ Hi CL CQ HS P- ¹ φ LQ Ω φ H- ¹ SP Hj

P tr ^ LQ 0 P- φ 0 P- P- LQ Φ Ω rt 01 HS cd Φ tr LQ Hj Ω Φ tr

Φ P- CL rr φ H CL CL 01> rt Hi Hi tr 01 PP rt Φ Hi P H- ¹ P

P HS LQ φ PP H- ¹ <P- Φ φ rt PP 0 = P Φ LQ Ό CL 01 tr H- ¹ rt LQ d rt d

P Φ P P Ξ rt HS Φ P LQ P HS Hl X ta CL P- P- Φ P φ, -, P- P = Φ Φ Hh Hi Hh

CL P- Hi P- P- CL X Hi P ≤ LQ rt φ Φ rt rt 01 P • - '<! d H- ¹ Ω CQ 3 PP Φ rt • τ | Hj 0 φ rt P- Hj> τ | <φ HS P- HS P rt d Ω P Φ P CL tr P = PPP

CL 01 to p- CL P »HS P φ P- φ HS d 01 rt P tr d CL HS rt Φ Φ 3 ta tr CQ CL

Φ »LQ • 01 P- PP LQ Hj CL P Ω cd CL LQ s ^> PP rt Φ rt P- 3 P- φ

01 LQ PX 01 X rt P tr Φ CL tr CL φ Φ d LQ Hi P- P • Φ rt CO Φ 01 P φ l_J. ii HS 0 P Φ Hi P- PP Hj Hi P 3 Φ LQ X Hj rt rt co Hh Φ Φ P 3 P LO Φ P CL P HS φ P LQ P Φ P P- PX CL P _^ -, 0 S!

Td φ CL P LQ CL P CL «φ d 01 P- Φ LQ Φ 01 H- ¹ 01 d Φ Φ P Pd Hi o φ HS O φ P <! LQ tr Φ Hj li Hh rt Ω Hi Φ 3 P- rt Φ (T Hh PP CL P Hj

P- rt Ω P ¹ P ta O Φ P- t HS P- LQ Φ tr Hh O Φ P φ HS P 01 01 rt

Ω P- tr LO HS tr 01 rt ω φ Φ H- ¹ P- HS CL CL tr σ CL rt rt er LQ NN Φ tr • rt HS 3 H- ¹ CL P CL F CL H- ¹ CO φ Φ P Φ Φ Φ Φ φ φ rt P- tr PP>PP> P- P Hh P rt Φ CL P P- Φ rt rt HS 3 Hi P- Hi H {d P-

H (~ 01 P- HS HS P - ~ J 01 h- ¹ P- Ω HS d φ 3 3 • HS • CL Φ rr

X rt 01 P = 01 <H- ¹ P tr P rt P- P- Ω CL Φ HW Hi d

P 0 Ω d tr o P cn <CL 01 α 01 LQ Φ Φ P α Ω ri P- P Φ rt P

0 tr P- P ¹ X Φ P- PP Φ d φ P φ CQ P Φ Φ tr P φ P Ω Φ • LQ rt Φ 3 LQ ω H- ¹ CL CL Hj PP 01 H- ¹ LQ N tr d σ rt s; tr X φ HS Φ rt CL Φ P 01 LQ Φ φ Φ d Φ rt 3 Φ HS Φ 0 P rr <

P tr φ ^: P ¹ P P- CL HS Φ CQ Φ X 3 d P P- P Φ Hj Hi P- Hi φ co PPP rt Φ PP φ LQ rt LQ cn P- rr P = CQ Φ P- rr X Ω rt X 0 Hi rt rt N LQ LQ Φ P φ N Φ Ω P P- ta Z HS CL Ω 0 tr CL H- ¹ P tr

LΠ er Φ CQ rt P 3 01 P 3 tr X <! Φ PX Φ er ≤ P rr Φ φ LQ Φ do HS Ό 3 CL ^h r | rt P p P- HS P tr φ 3 φ CL Φ Hj P- Φ PP

P L 01 Hi C LQ Φ co P- Φ LQ ta Ω P- P 3 01 P- φ rt N CL

Φ Ω P- P- 01 P LQ H- ¹ φ Φ tr 01 d CO rt P Ω P- ta P 2! Hi d Φ 3 Φ

P 01 tr Ω HS CL tr P P P rr rt Hh TJ HS Φ HS P CQ 0 Φ P P- P- P

P P- he CL Φ PC 01 HS rt P LQ φ P P P CL CL P HS Ω LQ LQ X

01 φ rt ^ HS 01 rt Φ Φ d Φ ~ o H- ¹ φ P- P er P rt rt er Φ rt HJ P-

0 CL O Hi PPP HS LΠ P ¹ 01 Φ P ^ Hj 0 H- ¹ rt P «O 01

Φ P CL Φ P CL P- P- CL P Hj LQ HS Φ Φ rt

P- N Φ P- P rt P ¹ P P- P- Φ P- P 1 P 3 co Φ Φ

LO LO to to P ¹ P ¹

LΠ O LΠ O LΠ o LΠ

Z LQ Ω d = PP tn Ω 01 LQ CL P = h- ¹ X LQ CL ö rt h- ¹ PPP

P- P- ¹ H! tr d P Ω HS φ Φ Φ rt P Hj φ Φ P- P- HS Φ Φ P φ

HS φ P Φ Hl Ω tr P P P 3 tsi rt P P P φ Hi P- P- HS HS

CL P- tr H <tr P- tr X d = rt P- LQ CL 01 rt CL

Ω Φ CL Hl Ω Φ r tr cn Φ 0 Φ <> τ) N Ω Hh ≤ φ φ

CL tr P CL P- 0 tr P P- Φ O P P P P P- K tr P = Φ HS HS

PN Hl Φ Φ H- ¹ rr CD φ HS Φ CD H! LQ φ P- Φ er P- CD

P Φ d = P LQ Hl P- Ω X LΠ P- d P- φ P- rt <; rt

P P- H- "N Φ LO LO Φ CL Ω HS HS LΠ P Hi rt co LQ Φ Φ Φ rt P ¹ φ ZP LΠ O Φ tr PPP Φ Φ P Ω Φ ι-i li P φ P- d P- Φ CL P ¹ HS Φ tr LQ <rt P »tr tr Φ tr

P LQ P P P- Φ tr ≤ to HS Φ Φ O Φ P- Ω P Td rt LQ LQ rt P Φ P- o φ X P P HS P »N ^ Ω HS Φ O

01 3 Φ Φ CL Hj HS P Hh X co d P- tr P CL P-

• d P- <! CQ Ξ Φ CL 01 0 d = LΠ Φ LQ rt tr P- tr ^

HS rt 0 φ cd φ Ω tl rt rt H- ¹ LΠ cn P- tr CL d Φ φ Φ CQ φ Hi P P- P- XP P- φ Φ> - • rt P P- Φ Hi LO P H- ¹ P P-

Ω CL er XP rt rr d LQ PP d CL P Φ ω P LΠ Hh Φ CL H- ¹ tr Φ P rr 01 Φ - P d P P- rt -J d = X Φ P-

Φ Hi P Φ φ Hi HS td LΠ LQ HS rt CL to] Φ rr P N

P L P P Φ CL d P- o Φ CL P- o P- Hh P Hj P-

CL Ω Φ XP P- PP ¹ PP LΠ X Φ φ LQ 0 rt d P- cd d

HS PM rr φ 3 LO 01 - o rr 01 P- ¹ 01 d HS Hi P CD 0 3 ^t fl P φ 01 P-? D P- - 'φ 01 φ P- Hi rt Φ LQ Ω CL Hh

P- tr 01 0 Φ d = N rt • P HS, ~ _^ 3 Φ X φ Φ LQ Hi tr Φ d =

LQ φ Hl Ω d rt X d = Φ P- P r tr P Φ P LΠ Φ P

P P CL P Φ X 3 Φ σ rr Ω P- rt Hi rt 01 rt o P Hh

HS Hh P- rr P = H- ¹ P- P- XP tr S. P- to φ _^ d

P = φ P- P ¹ rt cn tr φ Φ LQ Φ P- P- 01 P- rt -—. cn P = P

^ 1 H- ¹ 0 P ¹ N Ω P Hh Φ H- ¹ Hi Ω 3 tr N ^ Φ Ω Ω LQ

H- ¹ Φ P LΠ d tr ^ Hl φ P = N Hh CL tr P- rt P- P- tr tr

Hh P X 01 P d HS rt φ Φ α CQ • LQ P P- Φ CL

0 P rr X. -. LQ rt 3 Φ P ¹ N φ CL P d Φ Ω φ

HS LQ Hi HS d N P- P- P ¹ rt P- CL P- cn rt cn Hi tr P HS rt P- P P- CL rt p ^j o *> rt Φ φ Ω Φ N rt d

LQ HS 01 LQ LQ φ CL P- Φ HS tr HS P H- ¹ Hl Pl

Φ P = Ω Φ d Hj Φ Φ φ LQ d cd P- 01 H- ¹ ^ 1 φ LO LQ 01

CD Ω er P Hi HS P- LQ φ P Td LQ P- Ω Ω rt - P- LΠ Φ 0 φ X Φ Ω P Φ HS CL 0 Φ P tr tr Φ rt tr H- ¹ rt LQ 01 Φ to Hi cn Φ P P- H- ¹ 3 01 rr P- Hj Φ tr ii P

N Φ HS o P Φ HS CL P N ^ P = φ φ P α Φ P rt rt P = 3 tr - 'er P- Φ LQ ≤ 01 ta P P α P P Td CL Ω P-

• rt P 0 = φ rt CL P H P P- X d rt 01 0 Φ tr O

N rt tr CL P Φ P- d = HS H- "^ rt Hh CL P- H- ¹ Ω rr P rt Φ rt P- Hh P φ cn LQ P- P- P- P <! K ^ X • ω

HS Φ φ P ≤ H- ¹ φ P- tr N LQ Φ CL N Φ φ 01 rt X

P- 3 PP Φ P- LQ P- P- d Hl Φ d P- P- »cd ι-i ü P rt P-" PX rt 01 d HS φ 3 <rt H- ¹ Hi P

P H- ¹ S • d CL rt Φ LQ 3 d P Φ P- d = LQ

CQ PP HS P HS N Hh P ¹ P> PC P Hj HS N tr P- φ

≤. rt> LQ ≤ P- € 0 = d d = o to 01 CL P- Φ P- Φ 01 P

<P- Φ d P = 01 P ta H- ¹ oo P d Hj r

Φ HS Hi Hl LΠ tr Ω P φ φ H- ¹ H {h- ¹ NP <3 LΠ

Hi CL P- o HS tr CL HS P- d d = CL P d rt Φ Hh CL <! LΠ

Hl P LQ Φ Φ φ P P Ω φ rt HS Φ Hi d = φ 0

P Φ tr PP CL P φ LQ pr co P- Hh H- ¹ HS PP tr LQ P- CL φ HS LQ 0 <! LQ P H- ¹ d

HS CL Φ 01 CD M d = Φ Pl P 0 Φ tr d CL φ Ω

CL Φ P CL P- LQ er co 01 HS 3 HS P P- P- tr

P HS Φ P Φ Φ 0 P- P = Φ LQ Φ

HS HS ta P LΠ

to P ¹ P> o LΠ o LΠ

Ω INI co CL Φ O 01 X IM P 01 <! cn ≤> P 01 X ^ d Φ α tr s; rt φ P- tr Ω P- P P Ω 0 Ω P- d φ P- Hi P P P- P-

Φ P- Φ HS P Φ er φ HS 01 P 'HS tr n 01 LQ P Ω CL P φ

Hi 01 rt Φ HS Φ HS Ω P- N P- L CL Φ LQ Φ φ

X Ω * X 3 Φ co er φ P Ω P- HS 01 Φ rt CL ω ^

P tr rt <! P P d \ -> CL LQ tr H P = P rt φ P-

0 φ O Φ P CL CL tr P- φ 01 rt P Hh d ^ Φ 3 Pd LQ rt P Hh P HS rt Φ φ 01 Φ P ≤ d d 3 d = LΠ P P- d

Φ 01 O 01 01 φ HS rt ta «Φ P ¹ CQ 01 LΠ tr HH P Hi

P Ω H {rt 2 HS Φ P- 00 LQ P- P- H- ¹ P- CD LQ Φ tr rt ≤ P = CL ^ PPP ü 01 o Φ 0 Ω 3 tr H- ¹ 0 CO P

P P- LQ Φ HS φ P rt rt CL P- φ tr P tr P P- CL H- ¹ TJ tr Ω Φ P- X 01 Ω Φ 0 φ P Φ Φ rt P d PP to

LQ tr Hh rt rr Φ HS σ LQ φ d P P- P Φ P rt H- <o φ rr d = φ Φ H rt P- φ Φ P- P- CQ CL P Hi P CQ P- rt

01 he HS 01 rt P Hi 3 01 P ≥! P- d O CQ d

Ω -j H (Φ 0 Φ P- ¹ Hh p: o φ φ <CL P = P 01 CL PP tr o rt d H- "ta rt 3 P- 0 P er P * tr Φ 01 H CL

P- - - <01 PP ¹ P- P = Hi PP CQ Φ P- HS X cn φ φ CL r to P Ω • n 0 3 φ CL Hi o to

CL CL tr HS P- P- LΠ tr P- »d P- 3 ^ CO N Φ CL φ PP ¹

Φ P- Φ Hl Hi 0 CL φ LQ rt P- d d 01 Φ * d LQ N

P φ LQ P Hl P CL φ d P HS φ LQ tr HS rt P- φ s: N

P- tr d 01 Φ 3 to Hj tr P- P- d 01 <. rt P P- φ

Ξ N P HS 01 X HS LΠ LQ CL P HS rt Ω Φ P 01 P-

P- d P Φ P- P t φ Φ Hi Hj Hi α X LΠ Ω LQ

Hj LQ Φ P 0 P Φ P φ to 01 ≤ ~ J P P LQ 0 rt cn tr φ

CL P ¹ PP LQ Ό NP Ω P- α ~ rt tr Hi Hj P- - φ P

, φ CL Φ P- P rt P er φ P- Φ P rt 01 P

P- P- P P rt LQ H P P- Hh LQ to P tr Ω CL <

Ω 3 HS P 01 PP = φ P- φ cn H φ o CQ φ X tr Φ CL φ tr P- CL CD XP Hi 01 CL P- d 3 Φ PP Φ HS φ Hi rt LΠ rr LQ P 0 Φ -> 01 P = Hh P- Φ PP HS Hi

P- CL CL LΠ P- H- ¹ rt rt P P- P- ta P = rt PP 3 P

3 CL P P- 01 P- - H φ N o Pf Φ co P- φ tr

Φ P Φ tsi Ω Ω O P- P • n HS P * Hi Ω rt Ό HS cd HS P 01 P tr tT ≤ v σ d P- Φ 0 d = er P- φ φ φ H (φ Φ 0 P- tr LQ PPP HS P- CL rt P

HS ≤ 3 d = P P tr P- Hh p P P rr Ω Φ P 01

P er P- Ω Φ P H P- 0 HS CL P σ er HS X 01

P- 01 φ d X co Pd P- d rt Ω c! X 0 r rr Ω

Ω Ω P- tr Ω P- Pd 01 HS X to 3 Nrr er 01 P- er er er P- P tr P CL P- P- P- P- P "d 01 P- -j P- 01 Hi

Φ P LQ Φ P- LQ P Ω 0 CL φ CL Φ cn Ω Ω P- cn P- 01 P- Ω 01 co tr P ti N P- Φ cn HS tr tr rt

LΠ CL <τi O tr tr> d rt 01 Φ P φ P- o 01 N φ rt d P- P rt rt P CL d tr P- P P 01 3 rt d P P Φ

PP LQ H- ¹ P- PP 01 CL P = Φ PO 3 dd LQ d rt P ^ 1 rt Hi LQ Hi o φ Ω N HS d Hh Hh cn N

Hl ri P LΠ Hl Hi rt P tr P Hh Hh LQ Ω d

CL P ¹ CL P ¹ d 01 P- HS CQ 01 LQ Φ 01 HS tr 3

CL φ S cn P cn 01 φ φ 0 s rt <; rt H {0 d P-

Φ HS o 01 P o P- P Hj OP Φ P = d CL H- ¹ P Ω

3 CL • d CL o X Φ rt Φ HS ^ i P d P CL tr P

Φ P <! P = NP Hj P Φ P- 3 X CL HS rt rr Hl co HS HS φ rt CL ≤ 01 φ i ^> tr Hi P φ Φ Ω P- CL Hi

• d 01 LQ Hi Φ φ P- tr Ω P- LQ P- Φ P- ri CQ tr 0 φ o P = φ rt Φ tr H HS 1 H- ¹ tr Hi Φ P CL Φ Φ P HS LΠ ^J

P- φ 1 P- 0 rt CL 1 Φ P P- P = ω 1 P P X P 01 1 φ

1 1 1 P

LIST OF REFERENCE NUMBERS

5 memory cell

10 selection transistor 15 trench capacitor

20 substrate

25 substrate surface

30 trenches

31 upper region 35 capacitor dielectric or dielectric layer

40 buried plate 45 buried tub

50 conductive trench filling

55 insulation collar 60 buried contact

70 first intermediate layer

75 epitaxially grown layer

80 dopant diffusion

85 first doping region 90 second doping region

95 gate

100 trench isolation

105 bottom edge

110 first recess depth 115 second recess depth

120 third sink depth

125 facets

130 insulation layer

135 fourth recess depth 140 gate contact

145 gate oxide

150 funding area

Claims

claims Semiconductor memory (5) with a trench capacitor (15) and a selection transistor (10), comprising: - a substrate (20) which has a substrate surface (25) and in which a trench (30) is arranged which has an upper region (31) has an insulation collar (55) which is arranged in the upper region (31) on the side wall of the trench (30), - a conductive trench filling (50) which is arranged in the trench (30), an epitaxially grown layer (75) which extends into the trench (30) and is arranged on the side wall of the trench (30), - a buried contact (60) which is arranged in the trench (30) and the epitaxially grown Layer (75) electrically connects to the conductive trench filling (50), and - A first intermediate layer (70), which is arranged between the epitaxially grown layer (75) and the buried contact (60). 2. The semiconductor memory as claimed in claim 1, so that the epitaxially grown layer (75) is arranged in the direction of the substrate surface (25) above the insulation collar (55) on the side wall of the trench (30). 3. Semiconductor memory according to claim 1 or 2, so that a capacitor dielectric (35) is arranged in the trench (30) between the conductive trench filling (50) and the substrate (20). 4. Semiconductor memory according to one of claims 1 to 3, characterized in that the epitaxially grown layer (75) has a facet (125) which has an angle of approximately 45 degrees with respect to the substrate surface (25). 5. The semiconductor memory as claimed in claim 4, so that the facet (125) is located at the lower end of the epitaxially grown layer (75) above the insulation collar (55). 6. Semiconductor memory according to claim 4 or 5, characterized in that in a by the facet (125) and the upper edge of the insulation collar (55) formed annular gap (160) a barrier layer (170) is introduced, which diffuses dopants to the side wall the trench (30) prevented. 7. Semiconductor memory according to one of claims 1 to 6, that the dopant is introduced into the epitaxially grown layer (75) and the adjacent substrate (20) in order to form a conductive electrical connection to the buried contact (60). 8. The semiconductor memory as claimed in claim 7, so that the trench insulation (100) has an insulation layer (130) which is arranged on the buried contact (60) and on the epitaxially grown layer (75). 9. Semiconductor memory according to one of claims 1 to 8, characterized in that the insulation collar (55) consists of two layers which can be selectively etched to one another. 10. A method for producing a semiconductor memory (5) with a trench capacitor (15) and a selection transistor (10) with the steps: - Providing a substrate (20) which has a substrate surface (25) and in which a trench (30) is arranged which has an upper region (31), an insulation collar (55) in the upper region (31) is arranged on the side wall of the trench (30), Forming a conductive trench filling (50) in the trench (30), the conductive trench filling (50) then being sunk into the trench (30), Exposing the substrate (20) on the side wall of the trench (30) above the conductive trench filling (50), Growing an epitaxial layer (75) on the exposed side wall of the trench (30), - Forming a first intermediate layer (70) on the epitaxially grown layer (75), - Introducing dopant into the epitaxially grown layer (75) and - Forming the trench capacitor (15) and the selection transistor (10). 11. The method according to claim 10, that the substrate (20) is exposed on the side wall of the trench (30) by removing an upper part of the insulation collar (55). 12. The method according to claim 10 or 11, characterized in that after the provision of the substrate (20), a dielectric layer (35) of a capacitor dielectric is deposited on the insulation collar (55) before the conductive trench filling (50) is formed, and that Conductive trench filling (50) first sunk into the trench (30) to a first recess depth (110), then the dielectric Layer (35) above the first recess depth (110) is removed from the insulation collar (55) and then the conductive trench filling (50) is sunk into the trench (30) to a second recess depth (115) before the substrate (20) above the conductive trench filling (50) is exposed. 13. The method according to claim 10 or 11, characterized in that a substrate (20) is provided which in a lower region of the trench (30) already has a capacitor electric, which was introduced before the formation of the insulation collar (55), and that the dielectric Layer (35) is deposited on the insulation collar (55) only after the insulation collar (55) has been formed. 14. The method according to claim 13, characterized in that the conductive trench filling (50) first sunk to a first recess depth (110) in the trench (30), then the dielectric layer (35) above the first recess depth (110) from the insulation collar (55) is removed and then the conductive trench filling (50) is sunk into the trench (30) to a second recess depth (115) before the substrate (20) is exposed above the conductive trench filling (50). 15. The method according to any one of claims 10, 11 or 13, characterized in that the conductive trench filling (50) is first sunk into the trench (30) to a first recess depth (110), then the substrate (20) on the Side wall of the trench (30) is exposed and then a dielectric layer (35) is deposited directly on the exposed side wall of the trench (30), and then the conductive trench filling (50) to a second recess depth (115) in the Trench (30) sunk and the dielectric layer (35) from the side wall of the trench (30) is removed before the epitaxial layer (75) is grown. 16. The method according to any one of claims 10 to 15, that a trench isolation (100) in the substrate (20) and in the trench (30) is formed. 17. The method according to any one of claims 10 to 16, so that the epitaxially grown layer (75) is grown such that a facet (125) is formed at an angle of approximately 45 degrees with respect to the substrate surface (25). 18. The method according to claim 17, characterized in that in a by the facet (125) and the upper edge of the insulation collar (55) formed annular gap (160) at the edge of the open trench (30) has a barrier layer (170) to avoid dopant diffusions into the Sidewall of the trench (30) is introduced by depositing a material (180) impermeable to dopants isotropically into the trench (30) and then etching back anisotropically in the direction perpendicular to the substrate surface (25).