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EP1095408A1 - Vertical semiconductor element with reduced electric surface field - Google Patents

Vertical semiconductor element with reduced electric surface field

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Publication number
EP1095408A1
EP1095408A1 EP99944266A EP99944266A EP1095408A1 EP 1095408 A1 EP1095408 A1 EP 1095408A1 EP 99944266 A EP99944266 A EP 99944266A EP 99944266 A EP99944266 A EP 99944266A EP 1095408 A1 EP1095408 A1 EP 1095408A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor body
regions
vertical
semiconductor
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99944266A
Other languages
German (de)
French (fr)
Inventor
Gerald Deboy
Heinz Mitlehner
Jenö Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1095408A1 publication Critical patent/EP1095408A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a vertical semiconductor component with a semiconductor body of the one conduction type, in the surface area of which at least one zone of the opposite conduction type is embedded, the other conduction type, and to regions of the other conduction type which are in the semiconductor body in a substantially parallel to the surface of the surface area trending level are provided.
  • Such semiconductor components can in particular be n- or p-channel MOSFETs (MOS field effect transistors), IGBTs (bipolar transistors with insulated gate),
  • a Schottky diode in whose semiconductor bodies of one line type are embedded floating regions of the other line type to increase the reverse voltage, is known from US Pat. No. 4,134,123.
  • MOSFETs made of SiC with a high breakdown field strength and a low on resistance are known.
  • This object is achieved according to the invention in the case of a vertical semiconductor component of the type mentioned at the outset in that the regions are so highly doped that they are formed in the reverse direction and in the forward direction when the voltage is applied, by the semiconductor body with the zone of the other conductivity type.
  • the pn junction on charge carriers cannot be cleared.
  • the regions can be floating or partially or all can be at a fixed potential.
  • An effective reduction of the electrical surface field can be achieved by installing the non-clearable, preferably floating regions with dopants with a conductivity type opposite to the semiconductor body, for example by installing p-type regions in an n-type semiconductor body.
  • This is particularly advantageous in the case of a semiconductor body made of SiC, since with this semiconductor material, due to its very high volume breakthrough field strength (approx. 2 MV / cm compared to approx. 250 kV / cm for Si), a reduction in the surface field in the area of thermal oxides (Silicon dioxide about 8 MV / cm) is necessary in order to be able to utilize the maximum blocking capability of semiconductor components, for example transistors, produced therefrom even with small oxide thicknesses.
  • the vertical distance between the zone of the other line type and the preferably floating areas is selected such that the vertical line integral between the lower edge of this zone facing away from the surface of the zone of the other line type and that of this zone the upper edge of the preferably floating regions facing the doping remains below the specific breakdown charge (charge carrier "cm -2 ) which is dependent on the material of the semiconductor body.
  • charge carrier "cm -2 ) which is dependent on the material of the semiconductor body.
  • the line integral therefore remains below 2" 10 12 charge carriers cm -2 .
  • Other possible semiconductor materials are Ge, GaAs and - as already mentioned - especially SiC.
  • the line integral is thus formed perpendicular to the pn junction between the zone of the other conductivity type and the semiconductor body via the doping in it.
  • the preferably floating areas are formed in a point, strip or lattice shape.
  • the majority charge carrier current is influenced as little as possible, for example in the drift path of a vertical power MOSFET.
  • these regions can optionally also be connected at some points to the well of the transistor which is at source potential. This allows a significant reduction in the electrical surface field in the areas between the respective troughs to be achieved.
  • the invention enables a significant increase in the doping concentration “above” the preferred floating regions, that is to say between these and the surface of the semiconductor body. This increase in doping results in a homogeneous current distribution and a reduction in the on-resistance.
  • thermal SiO can readily be used as gate insulation as a result of the reduced surface field.
  • the semiconductor component according to the invention can be produced, for example, by implantation of the preferably floating regions and subsequent deposition of an epitaxial cover layer or by etching a trench (trench), implantation and filling with monocrystalline semiconductor material.
  • a trench trench
  • the doping is already to be defined for the semiconductor body during the manufacturing process.
  • FIG. 1 shows a sectional illustration of a robust n-channel MOSFET as an exemplary embodiment of the semiconductor component according to the invention
  • the n-channel MOSFET consists of a silicon semiconductor body with an n + -type semiconductor substrate 2 and an n-type semiconductor layer 1 thereon, a metallization 3 made of, for example, aluminum and with a drain electrode D, a p-type well 4, an n conductive source zone 5, a source metallization 6 made of, for example, aluminum, an insulating layer 7 made of, for example, silicon dioxide and a gate electrode 10 made of, for example, doped polycrystalline silicon.
  • p-type regions 8 are provided at such a vertical distance from the source zone 5 that the vertical line integral via the doping of the semiconductor layer 1 remains below approximately 2 "10 12 charge carriers cm -2 .
  • the areas 8 are point, strip or lattice-shaped and have dimensions which are approximately 1-3 ⁇ m. In some places, the areas 8 can also be connected to the tub 4. The areas 8, however, can also all be floating.
  • the doping concentration in the regions 8 is approximately 10 17 charge carriers cm "3 and is so high that these regions with the voltage applied in the reverse direction and in the forward direction of that formed between the trough 4 and the semiconductor layer 1 pn transition on charge carriers cannot be cleared.
  • the regions 8 ensure a homogeneous distribution of the current, as indicated by arrows 9, and bring about a reduction in the on-resistance.
  • the reduction in the surface field achieved by the regions 8 permits a significant increase in the doping in the semiconductor layer 2 above these regions 8, which is particularly advantageous in the case of SiC.
  • the invention is also applicable to other semiconductor materials, as explained above.
  • the semiconductor component according to the invention can be, for example, n- or p-channel MOS power transistors, IGBTs, JFETs, GTOs or diodes.
  • FIG. 2 and 3 show top views of cell structures with a grid-like (FIG. 2) or strip-like (FIG. 3) configuration of the regions 8.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thyristors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to a vertical semiconductor element comprising a semiconductor body (1, 2) of a first conductivity type, whereby at least one zone (4) of another opposite conductivity type is embedded in the surface of said semiconductor body, in addition to areas (8) of another conductivity type that are provided in the semiconductor body (1, 2) on a plane running substantially parallel to the surface of the surface area. The areas (8) are highly doped so that they cannot be cleared when voltage is applied to the charge carriers.

Description

VERTIKALES HALBLEITERBAUELEMENT MIT REDUZIERTEM ELEKTRISCHEM OBERFLÄCHENFELD VERTICAL SEMICONDUCTOR COMPONENT WITH REDUCED ELECTRICAL SURFACE AREA
Die Erfindung betrifft ein vertikales Halbleiterbauelement mit einem Halbleiterkorper des einen Leitungstyps, in dessen Oberflächenbereich wenigstens eine Zone des zum einen Leitungstyp entgegengesetzten, anderen Leitungstyps eingebettet ist, und mit Gebieten des anderen Leitungstyps, die im Halbleiterkorper in einer im wesentlichen parallel zu der Oberfläche des Oberflächenbereiches verlaufenden Ebene vorgesehen sind. Bei derartigen Halbleiterbauelementen kann es sich insbesondere um n- oder p-Kanal-MOSFETs (MOS-Feldeffekttransi- stören) , IGBTs (Bipolartransistoren mit isoliertem Gate) ,The invention relates to a vertical semiconductor component with a semiconductor body of the one conduction type, in the surface area of which at least one zone of the opposite conduction type is embedded, the other conduction type, and to regions of the other conduction type which are in the semiconductor body in a substantially parallel to the surface of the surface area trending level are provided. Such semiconductor components can in particular be n- or p-channel MOSFETs (MOS field effect transistors), IGBTs (bipolar transistors with insulated gate),
JFETs (Junction- bzw. Übergangs-Feldeffekttransistoren) , GTOs oder Dioden handeln.Act JFETs (junction or transition field effect transistors), GTOs or diodes.
Eine Schottky-Diode, in deren Halbleiterkorper des einen Lei- tungstyps zur Erhöhung der Sperrspannung floatende Gebiete des anderen Leitungstyps eingebettet sind, ist aus US 4 134 123 bekannt. Außerdem sind aus IEEE Electron Device Letters, Bd. 18, Nr. 12, Dezember 1997, Seiten 589 bis 591, MOSFETs aus SiC mit hoher Durchbruchfeidstärke und niedrigem Einschaltwiderstand bekannt.A Schottky diode, in whose semiconductor bodies of one line type are embedded floating regions of the other line type to increase the reverse voltage, is known from US Pat. No. 4,134,123. In addition, from IEEE Electron Device Letters, Vol. 18, No. 12, December 1997, pages 589 to 591, MOSFETs made of SiC with a high breakdown field strength and a low on resistance are known.
Es ist Aufgabe der vorliegenden Erfindung, ein vertikales Halbleiterbauelement zu schaffen, das sich durch eine deutliche Reduktion des elektrischen Oberflächenfeldes bei gleich- zeitiger Verbesserung der lateralen Stromverteilung und derIt is an object of the present invention to provide a vertical semiconductor component which is distinguished by a significant reduction in the electrical surface field while at the same time improving the lateral current distribution and the
Widerstands- bzw. Durchlaßcharakteristik auszeichnet.Characterized resistance or transmission characteristic.
Diese Aufgabe wird bei einem vertikalen Halbleiterbauelement der eingangs genannten Art erfindungsgemäß dadurch gelöst, daß die Gebiete so hoch dotiert sind, daß sie bei anliegender Spannung in Sperrichtung und in Durchlaßrichtung des von dem Halbleiterkorper mit der Zone des anderen Leitungstyps gebil- deten pn-Überganges an Ladungsträgern nicht ausräumbar sind. Die Gebiete können dabei floatend sein oder teilweise bzw. alle auf festem Potential liegen.This object is achieved according to the invention in the case of a vertical semiconductor component of the type mentioned at the outset in that the regions are so highly doped that they are formed in the reverse direction and in the forward direction when the voltage is applied, by the semiconductor body with the zone of the other conductivity type. The pn junction on charge carriers cannot be cleared. The regions can be floating or partially or all can be at a fixed potential.
Durch den Einbau der nicht ausräumbaren, vorzugsweise floatenden Gebiete mit Dotierstoffen mit einem zum Halbleiterkorper entgegengesetztem Leitungstyp, also beispielsweise durch den Einbau von p-leitenden Gebieten in einen n-leitenden Halbleiterkorper, läßt sich eine wirksame Reduktion des elek- trischen Oberflächenfeldes erzielen. Dies ist besonders bei einem aus SiC bestehenden Halbleiterkorper von Vorteil, da bei diesem Halbleitermaterial infolge dessen sehr hoher Volumendurchbruchsfeidstärke (ca. 2 MV/cm im Vergleich zu ca. 250 kV/cm bei Si) eine Reduktion des Oberflächenfeldes im Be- reich thermischer Oxide (Siliziumdioxid etwa 8 MV/cm) notwendig ist, um auch bei geringen Oxiddicken die maximale Blok- kierfähigkeit von hieraus hergestellten Halbleiterbauelementen, beispielsweise Transistoren, ausnutzen zu können.An effective reduction of the electrical surface field can be achieved by installing the non-clearable, preferably floating regions with dopants with a conductivity type opposite to the semiconductor body, for example by installing p-type regions in an n-type semiconductor body. This is particularly advantageous in the case of a semiconductor body made of SiC, since with this semiconductor material, due to its very high volume breakthrough field strength (approx. 2 MV / cm compared to approx. 250 kV / cm for Si), a reduction in the surface field in the area of thermal oxides (Silicon dioxide about 8 MV / cm) is necessary in order to be able to utilize the maximum blocking capability of semiconductor components, for example transistors, produced therefrom even with small oxide thicknesses.
In einer Weiterbildung der Erfindung ist vorgesehen, daß der vertikale Abstand zwischen der Zone des anderen Leitungstyps und den vorzugsweise floatenden Gebieten derart gewählt ist, daß das vertikale Linienintegral zwischen dem von der Oberfläche der Zone des anderen Leitungstyps abgewandten unteren Rand dieser Zone und dem dieser Zone zugewandten oberen Rand der vorzugsweise floatenden Gebiete über der Dotierung unterhalb der vom Material des Halbleiterkörpers abhängigen spezifischen Durchbruchsladung (Ladungsträger " cm-2) bleibt. Bei einem aus Si bestehenden Halbleiterkorper bleibt das Linien- integral also unterhalb 2 " 1012 Ladungsträgern cm-2. Andere mögliche Halbleitermaterialien sind z.B. Ge, GaAs und - wie bereits erwähnt wurde - vor allem SiC.In a further development of the invention it is provided that the vertical distance between the zone of the other line type and the preferably floating areas is selected such that the vertical line integral between the lower edge of this zone facing away from the surface of the zone of the other line type and that of this zone the upper edge of the preferably floating regions facing the doping remains below the specific breakdown charge (charge carrier "cm -2 ) which is dependent on the material of the semiconductor body. In the case of a semiconductor body consisting of Si, the line integral therefore remains below 2" 10 12 charge carriers cm -2 . Other possible semiconductor materials are Ge, GaAs and - as already mentioned - especially SiC.
Das Linienintegral wird also senkrecht zu dem pn-Übergang zwischen der Zone des anderen Leitungstyps und dem Halbleiterkorper über die Dotierung in diesem gebildet. Die Durchbruchsladung ist dabei über die 3. Maxwellsche Gleichung VE=-4πpmit der Durchbruchsfeldstärke verknüpft (E = elektrische Feldstärke; p = Ladungsdichte) .The line integral is thus formed perpendicular to the pn junction between the zone of the other conductivity type and the semiconductor body via the doping in it. The breakthrough charge is via the 3rd Maxwell equation VE = -4πp linked to the breakdown field strength (E = electrical field strength; p = charge density).
Eine andere Weiterbildung der Erfindung besteht darin, daß die vorzugsweise floatenden Gebiete punkt-, streifen- oder gitterförmig ausgebildet sind. Dadurch wird der Majoritätsladungsträgerstrom beispielsweise in der Driftstrecke eines vertikalen Leistungs-MOSFETs möglichst wenig beeinflußt. Bei einem solchen Transistor können diese Gebiete gegebenenfalls auch an einigen Stellen mit der auf Source-Potential liegenden Wanne des Transistors verbunden werden. Dadurch läßt sich eine deutliche Reduktion des elektrischen Oberflächenfeldes in den zwischen den jeweiligen Wannen liegenden Bereichen erreichen.Another development of the invention consists in that the preferably floating areas are formed in a point, strip or lattice shape. As a result, the majority charge carrier current is influenced as little as possible, for example in the drift path of a vertical power MOSFET. In the case of such a transistor, these regions can optionally also be connected at some points to the well of the transistor which is at source potential. This allows a significant reduction in the electrical surface field in the areas between the respective troughs to be achieved.
Die Erfindung ermöglicht eine deutliche Erhöhung der Dotierungskonzentration "oberhalb" der bevorzugten floatenden Gebiete, also zwischen diesen und der Oberfläche des Halbleiterkörpers. Diese Erhöhung der Dotierung bedingt eine homo- gene Stromverteilung und eine Reduktion des Einschaltwiderstandes. Bei einem aus SiC bestehenden Halbleiterkorper kann ohne weiteres thermisches Si0 als Gateisolation infolge des verringerten Oberflächenfeldes eingesetzt werden.The invention enables a significant increase in the doping concentration “above” the preferred floating regions, that is to say between these and the surface of the semiconductor body. This increase in doping results in a homogeneous current distribution and a reduction in the on-resistance. In the case of a semiconductor body consisting of SiC, thermal SiO can readily be used as gate insulation as a result of the reduced surface field.
Das erfindungsgemäße Halbleiterbauelement ist beispielsweise durch Implantation der vorzugsweise floatenden Gebiete und anschließende Abscheidung einer epitaktischen Deckschicht oder durch Ätzen eines Trenchs (Grabens) , Implantation und Auffüllung mit monokristallinem Halbleitermaterial herstell- bar. Bei dem zuerst genannten Verfahren besteht die Möglichkeit, die Dotierung in der Deckschicht oberhalb der vorzugsweise floatenden Gebiete frei einzustellen, während bei dem zweitgenannten Verfahren die Dotierung bereits während des Herstellungsprozesses für den Halbleiterkorper festzulegen ist. Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The semiconductor component according to the invention can be produced, for example, by implantation of the preferably floating regions and subsequent deposition of an epitaxial cover layer or by etching a trench (trench), implantation and filling with monocrystalline semiconductor material. In the case of the first-mentioned method, there is the possibility of freely adjusting the doping in the cover layer above the preferably floating regions, while in the case of the second-mentioned method the doping is already to be defined for the semiconductor body during the manufacturing process. The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 eine Schnittdarstellung eines robusten n-Ka- nal-MOSFET als einem Ausführungsbeispiel des erfindungsgemäßen Halbleiterbauelements, und1 shows a sectional illustration of a robust n-channel MOSFET as an exemplary embodiment of the semiconductor component according to the invention, and
Fig. 2 und 3 Draufsichten auf zwei verschiedene Zellenfelder.2 and 3 top views of two different cell fields.
Fig. 1 zeigt einen n-Kanal-MOSFET, wobei zur Vereinfachung und besseren Übersichtlichkeit nur einzelne Bereiche schraffiert sind. Der n-Kanal-MOSFET besteht aus einem Silizium- Halbleiterkörper mit einem n+-leitenden Halbleitersubstrat 2 und einer darauf n-leitenden Halbleiterschicht 1, einer Metallisierung 3 aus beispielsweise Aluminium und mit einer Drainelektrode D, einer p-leitenden Wanne 4, einer n-leitenden Sourcezone 5, einer Source-Metallisierung 6 aus beispielsweise Aluminium, einer Isolierschicht 7 aus beispiels- weise Siliziumdioxid und einer Gateelektrode 10 aus beispielsweise dotiertem polykristallinem Silizium.1 shows an n-channel MOSFET, only individual areas being hatched for simplicity and better clarity. The n-channel MOSFET consists of a silicon semiconductor body with an n + -type semiconductor substrate 2 and an n-type semiconductor layer 1 thereon, a metallization 3 made of, for example, aluminum and with a drain electrode D, a p-type well 4, an n conductive source zone 5, a source metallization 6 made of, for example, aluminum, an insulating layer 7 made of, for example, silicon dioxide and a gate electrode 10 made of, for example, doped polycrystalline silicon.
Erfindungsgemäß sind p-leitende Gebiete 8 in einem solchen vertikalen Abstand von der Sourcezone 5 vorgesehen, daß das vertikale Linienintegral über die Dotierung der Halbleiterschicht 1 unterhalb von etwa 2 " 1012 Ladungsträger cm-2 bleibt. In einem p-leitenden Halbleiterkorper sind in entsprechender Weise n-leitende Gebiete eingebettet. Die Gebiete 8 sind punkt-, streifen- oder gitterförmig und weisen Abmes- sungen auf, die etwa 1 - 3 μm betragen. An einigen Stellen können die Gebiete 8 auch mit der Wanne 4 verbunden sein. Die Gebiete 8 können aber auch alle floatend sein. Die Dotierungskonzentration in den Gebieten 8 beträgt etwa 1017 Ladungsträger cm"3 und ist so hoch, daß diese Gebiete bei an- liegender Spannung in Sperrichtung und in Durchlaßrichtung des zwischen der Wanne 4 und der Halbleiterschicht 1 gebildeten pn-Übergang an Ladungsträgern nicht ausgeräumt werden. Die Gebiete 8 sorgen für eine homogene Verteilung des Stromes, wie dies durch Pfeile 9 angedeutet ist, und bewirken eine Reduktion des Einschaltwiderstandes.According to the invention, p-type regions 8 are provided at such a vertical distance from the source zone 5 that the vertical line integral via the doping of the semiconductor layer 1 remains below approximately 2 "10 12 charge carriers cm -2 . In a p-type semiconductor body are correspondingly The areas 8 are point, strip or lattice-shaped and have dimensions which are approximately 1-3 μm. In some places, the areas 8 can also be connected to the tub 4. The areas 8, however, can also all be floating. The doping concentration in the regions 8 is approximately 10 17 charge carriers cm "3 and is so high that these regions with the voltage applied in the reverse direction and in the forward direction of that formed between the trough 4 and the semiconductor layer 1 pn transition on charge carriers cannot be cleared. The regions 8 ensure a homogeneous distribution of the current, as indicated by arrows 9, and bring about a reduction in the on-resistance.
Die durch die Gebiete 8 erzielte Reduktion des Oberflächenfeldes erlaubt eine deutliche Erhöhung der Dotierung in der Halbleiterschicht 2 oberhalb dieser Gebiete 8, was besonders bei SiC von Vorteil ist. Jedoch ist die Erfindung auch auf andere Halbleitermaterialien anwendbar, wie dies oben erläutert wurde .The reduction in the surface field achieved by the regions 8 permits a significant increase in the doping in the semiconductor layer 2 above these regions 8, which is particularly advantageous in the case of SiC. However, the invention is also applicable to other semiconductor materials, as explained above.
Bei dem erfindungsgemäßen Halbleiterbauelement kann es sich beispielsweise um n- oder p-Kanal-MOS-Leistungstransistoren, IGBTs, JFETs, GTOs oder Dioden handeln.The semiconductor component according to the invention can be, for example, n- or p-channel MOS power transistors, IGBTs, JFETs, GTOs or diodes.
Die Fig. 2 und 3 zeigen Draufsichten auf Zellenstrukturen mit einer gitterartigen (Fig. 2) bzw. streifenartigen (Fig. 3) Gestaltung der Gebiete 8. 2 and 3 show top views of cell structures with a grid-like (FIG. 2) or strip-like (FIG. 3) configuration of the regions 8.
BezugszeichenlisteReference list
1 Halbleiterschicht1 semiconductor layer
2 Halbleitersubstrat 3 Metallisierung2 semiconductor substrate 3 metallization
4 p-leitende Wanne4 p-type tub
5 Sourcezone5 source zone
6 Sourcemetallisierung6 Source Metallization
7 Isolierschicht 8 floatende Gebiete7 insulating layer 8 floating areas
9 Pfeile für Stromfluß9 arrows for current flow
10 Gateelektrode10 gate electrode
D Drainelektrode D drain electrode

Claims

Patentansprüche claims
1. Vertikales Halbleiterbauelement mit einem Halbleiterkorper (1, 2) des einen Leitungstyps, in dessen Oberflächen- bereich wenigstens eine Zone (4) des zum einen Leitungstyp entgegengesetzten anderen Leitungstyps eingebettet ist, und mit Gebieten (8) des anderen Leitungstyps, die im Halbleiterkorper (1, 2) in einer im wesentlichen parallel zu der Oberfläche des Oberflächenbereiches verlau- fenden Ebene vorgesehen sind, d a d u r c h g e k e n n z e i c h n e t , daß die Gebiete (8) so hoch dotiert sind, daß sie bei anliegender Spannung in Sperrichtung und in Durchlaßrichtung des von dem Halbleiterkorper (1, 2) mit der Zone (4) des anderen Leitungstyps gebildeten pn-Übergangs an Ladungsträgern nicht ausräumbar sind.1. Vertical semiconductor component with a semiconductor body (1, 2) of one conduction type, in the surface area of which at least one zone (4) of the opposite conduction type is embedded, and with regions (8) of the other conduction type which are in the semiconductor body (1, 2) are provided in a plane running essentially parallel to the surface of the surface area, characterized in that the regions (8) are doped so highly that when voltage is applied in the reverse direction and in the forward direction of the semiconductor body ( 1, 2) with the zone (4) of the other line type pn junction on charge carriers cannot be cleared.
2. Vertikales Halbleiterbauelement nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der vertikale Abstand zwischen der Zone (4) des anderen2. Vertical semiconductor device according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the vertical distance between the zone (4) of the other
Leitungstyps und den Gebieten (8) derart gewählt ist, daß das vertikale Linienintegral zwischen dem von der Oberfläche der Zone (4) des anderen Leitungstyps abgewandten unteren Rand dieser Gebiete (8) über der Dotierung des Halbleiterkörpers (1, 2) unterhalb der vom Material des Halbleiterkörpers (1, 2) abhängigen spezifischen Durchbruchsladung (Ladungsträger ' cm"2) bleibt.Conductivity type and the areas (8) is selected such that the vertical line integral between the lower edge of these areas (8) facing away from the surface of the zone (4) of the other conduction type above the doping of the semiconductor body (1, 2) below that of the material of the semiconductor body (1, 2) dependent specific breakdown charge (charge carrier 'cm "2 ) remains.
3. Vertikales Halbleiterbauelement nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß der Halbleiterkorper (1, 2) aus SiC, Si, Ge oder GaAs besteht.3. Vertical semiconductor component according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the semiconductor body (1, 2) consists of SiC, Si, Ge or GaAs.
4. Vertikales Halbleiterbauelement nach den Ansprüchen 2 und 3, d a d u r c h g e k e n n z e i c h n e t , daß bei einem aus Si bestehenden Halbleiterkorper (1, 2) das Linienintegral unterhalb von 2 1012 Ladungsträgern cm-2 bleibt.4. Vertical semiconductor device according to claims 2 and 3, characterized in that in the case of a semiconductor body made of Si (1, 2) Line integral below 2 10 12 charge carriers cm -2 remains.
5. Vertikales Halbleiterbauelement nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t , daß die Gebiete (8) punkt-, streifen- oder gitterförmig ausgebildet sind.5. Vertical semiconductor device according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the regions (8) are formed in a point, strip or lattice shape.
6. Vertikales Halbleiterbauelement nach einem der Ansprüche 1 bis 5, d a d u r c h g e k e n n z e i c h n e t , daß die Gebiete (8) floatend sind. 6. Vertical semiconductor component according to one of claims 1 to 5, d a d u r c h g e k e n n z e i c h n e t that the regions (8) are floating.
EP99944266A 1998-07-07 1999-07-02 Vertical semiconductor element with reduced electric surface field Withdrawn EP1095408A1 (en)

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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19840032C1 (en) 1998-09-02 1999-11-18 Siemens Ag Semiconductor device for compensation element
DE10145723A1 (en) * 2001-09-17 2003-04-10 Infineon Technologies Ag Semiconductor structure
US6649477B2 (en) * 2001-10-04 2003-11-18 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US6465304B1 (en) * 2001-10-04 2002-10-15 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6819089B2 (en) 2001-11-09 2004-11-16 Infineon Technologies Ag Power factor correction circuit with high-voltage semiconductor component
US6825514B2 (en) 2001-11-09 2004-11-30 Infineon Technologies Ag High-voltage semiconductor component
DE10214176B4 (en) * 2002-03-28 2010-09-02 Infineon Technologies Ag Semiconductor device with a buried stop zone and method for producing a stop zone in a semiconductor device
DE10243758A1 (en) 2002-09-20 2004-04-01 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Method for producing a buried stop zone in a semiconductor component and semiconductor component with a buried stop zone
EP1790013A1 (en) * 2004-08-31 2007-05-30 Freescale Semiconductor, Inc. Power semiconductor device
US7687841B2 (en) * 2005-08-02 2010-03-30 Micron Technology, Inc. Scalable high performance carbon nanotube field effect transistor
KR101614565B1 (en) 2008-09-01 2016-04-21 로무 가부시키가이샤 Semiconductor device and manufacturing method thereof
US8154078B2 (en) * 2010-02-17 2012-04-10 Vanguard International Semiconductor Corporation Semiconductor structure and fabrication method thereof
US8373449B2 (en) 2010-12-30 2013-02-12 Infineon Technologies Ag Circuit arrangement including a common source sense-FET
US9076805B2 (en) 2012-07-14 2015-07-07 Infineon Technologies Ag Current sense transistor with embedding of sense transistor cells
JP6111673B2 (en) * 2012-07-25 2017-04-12 住友電気工業株式会社 Silicon carbide semiconductor device
US9530844B2 (en) * 2012-12-28 2016-12-27 Cree, Inc. Transistor structures having reduced electrical field at the gate oxide and methods for making same
US10115815B2 (en) 2012-12-28 2018-10-30 Cree, Inc. Transistor structures having a deep recessed P+ junction and methods for making same
JP6148070B2 (en) 2013-05-27 2017-06-14 ルネサスエレクトロニクス株式会社 Vertical channel junction SiC power FET and method of manufacturing the same
EP2889915A1 (en) * 2013-12-30 2015-07-01 ABB Technology AG Power semiconductor device
US9360879B2 (en) 2014-04-28 2016-06-07 Microsemi Corp.-Analog Mixed Signal Group, Ltd. Sense current generation apparatus and method
CN107742646A (en) * 2017-09-21 2018-02-27 北京世纪金光半导体有限公司 It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends
US11489069B2 (en) 2017-12-21 2022-11-01 Wolfspeed, Inc. Vertical semiconductor device with improved ruggedness
US10615274B2 (en) 2017-12-21 2020-04-07 Cree, Inc. Vertical semiconductor device with improved ruggedness
DE102018112109A1 (en) * 2018-05-18 2019-11-21 Infineon Technologies Ag SILICON CARBIDE SEMICONDUCTOR ELEMENT
US10516372B1 (en) * 2018-07-03 2019-12-24 Nxp B.V. Low cost LF driver current sense topology
CN110224017A (en) * 2019-04-30 2019-09-10 上海功成半导体科技有限公司 Super junction device structure and preparation method thereof
KR102369048B1 (en) * 2020-07-02 2022-03-02 현대모비스 주식회사 Power semiconductor device and method of fabricating the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1558506A (en) * 1976-08-09 1980-01-03 Mullard Ltd Semiconductor devices having a rectifying metalto-semicondductor junction
JPS5368086A (en) * 1976-11-29 1978-06-17 Fujitsu Ltd Semiconductor device
JPS5737879A (en) * 1980-08-18 1982-03-02 Nec Corp Field effect transistor
US4654679A (en) * 1983-10-05 1987-03-31 Toyo Denki Seizo Kabushiki Kaisha Static induction thyristor with stepped-doping gate region
JPS63186475A (en) * 1987-01-29 1988-08-02 Nissan Motor Co Ltd Conductivity modulation type mosfet
US4821095A (en) * 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
JP2632322B2 (en) * 1987-10-02 1997-07-23 財団法人 半導体研究振興会 Power semiconductor device
GB2237930A (en) * 1989-11-01 1991-05-15 Philips Electronic Associated A semiconductor device and method of manufacturing a semiconductor device
US5218226A (en) * 1989-11-01 1993-06-08 U.S. Philips Corp. Semiconductor device having high breakdown voltage
US5608244A (en) * 1992-04-28 1997-03-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor diode with reduced recovery current
DE4309764C2 (en) * 1993-03-25 1997-01-30 Siemens Ag Power MOSFET
DE19707513A1 (en) 1997-02-25 1998-09-24 Siemens Ag Semiconductor component controllable by field effect
SE9704149D0 (en) * 1997-11-13 1997-11-13 Abb Research Ltd A semiconductor device of SiC and a transistor of SiC having an insulated gate
DE19816448C1 (en) * 1998-04-14 1999-09-30 Siemens Ag Universal semiconductor wafer for high-voltage semiconductor components, their manufacturing process and their use

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0002250A1 *

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