[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN107742646A - It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends - Google Patents

It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends Download PDF

Info

Publication number
CN107742646A
CN107742646A CN201710857440.2A CN201710857440A CN107742646A CN 107742646 A CN107742646 A CN 107742646A CN 201710857440 A CN201710857440 A CN 201710857440A CN 107742646 A CN107742646 A CN 107742646A
Authority
CN
China
Prior art keywords
areas
grid
carborundum
flat
structure cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201710857440.2A
Other languages
Chinese (zh)
Inventor
袁俊
黄兴
倪炜江
张敬伟
耿伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Century Goldray Semiconductor Co Ltd
Original Assignee
Century Goldray Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Century Goldray Semiconductor Co Ltd filed Critical Century Goldray Semiconductor Co Ltd
Priority to CN201710857440.2A priority Critical patent/CN107742646A/en
Publication of CN107742646A publication Critical patent/CN107742646A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a kind of carborundum flat-grid MOSFET component structure cell for having and burying the knot that suspends, the structure cell includes drain electrode, source electrode, grid, substrate, N drift layers, P well areas, p+ areas and n+ areas；One or more layers equally distributed discrete topology constructed by multiple burial suspension P+ areas is dispersed with the N drift layers below the p well areas.The application buries the uniform discrete topology in suspension P+ areas by being distributed a floor under the p well areas of carborundum flat-grid MOSFET component cellular, can strengthen the voltage endurance capability of device, while shielding protection effect is played to grid；On the other hand, also make it that the JFET regions design of cellular is more flexible.

Description

It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends
Technical field
The present invention relates to technical field of semiconductor device, and in particular to a kind of to have the carborundum planar gate for burying the knot that suspends MOSFET element structure cell.
Background technology
SiC is as the semiconductor material with wide forbidden band developed rapidly in recent ten years, and other semi-conducting materials, such as Si, GaN and GaAs are compared, and SiC material has the advantages that broad stopband, high heat conductance, high carrier saturation mobility, high power density. SiC can generate silica with thermal oxide so that SiC MOSFET and SBD constant power devices and circuit are implemented as possibility. Since the 1990s, SiC MOSFET and SBD constant powers device is in switching power supply, high-frequency heating, automobile electricity Son and power amplifier etc., which achieve, to be widely applied
SiC vertical powers MOSFET element mainly has double diffusion planar gate DMOSFET and vertical gate slot structure UMOSFET.Planar gate DMOSFET structures are as shown in figure 1, it includes drain electrode 1, source electrode 2, grid 3, substrate 4, drift layer 5, P- Well areas 6, p+ areas 7 and n+ areas 8；Planar gate DMOSFET structures employ planar diffusion technology, such as more using refractory material Crystal silicon grid make mask, with the Edge definition P bases and N+ source regions of polysilicon gate.DMOS title just comes from this double diffusion work Skill.Surface channel region is formed using the side diffusion difference of p-type base and n+ source regions.For high-pressure resistant silicon carbide MOSFET, based on existing carbonization silicon oxide gate dielectric process conditions limitation, planar gate structure UMOSFET often has more preferable grid can By property and yield.
However, SiC DMOSFET still have Railway Project in actual design and in making：1) SiC epitaxial layer drift region High electric field cause the electric field on gate oxide very high, so as to causing gate oxide to puncture rapidly under high drain voltage；For High pressure spike tolerance in the electrostatic effect and circuit of adverse circumstances is poor；2) increase of JFET sector widths can be reduced and led Be powered resistance, but also results in the decline of breakdown voltage simultaneously.If JFET sector widths excessively increase, adjacent P-well spacing Increase, the electric field shielding effect to JFET areas will reduce, cause the electric field of grid oxygen to be concentrated, will result under breakdown voltage Drop.3) high withstand voltage SiC MOSFET make when, the resistance to voltage devices of particularly more than 3300V, it is necessary to epitaxy layer thickness it is larger, The epitaxial layer of high quality causes high element manufacturing cost.
The content of the invention
For problems of the prior art, it is an object of the invention to provide a kind of carbonization for having and burying the knot that suspends Silicon flat-grid MOSFET component structure cell, one or more layers is dispersed with the p-well areas of the structure cell and buries suspension P+ The uniform discrete topology in area (it is one or more that single first intracellular buries the knot that suspends), the voltage endurance capability of device can be strengthened, while to grid Play shielding protection effect in pole.On the other hand, also make it that the JFET regions design of cellular is more flexible.
To achieve the above object, the present invention uses following technical scheme：
A kind of to have the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends, the structure cell includes leakage Pole, source electrode, grid, substrate, drift layer, P-well areas, p+ areas and n+ areas；Characterized in that, below the p-well areas One or more layers equally distributed discrete topology constructed by multiple burial suspension P+ areas is dispersed with the N- drift layers.
Further, the discrete topology and the vertical range in the p-well areas are 0-10um.
Further, the section in the burial suspension P+ areas be square, be circular, hexagon or annular.
The present invention has following advantageous effects：
The application by be distributed under the p-well areas of carborundum flat-grid MOSFET component cellular one or more layers by The uniform discrete topology (it is one or more that single first intracellular buries the knot that suspends) that multiple burial suspension P+ areas are formed, can strengthen device Voltage endurance capability, while grid is played shielding protection effect；On the other hand, also make it that the JFET regions design of cellular is cleverer It is living.
The resistance to intermediate pressure section that the application is deliberately constructed using the uniform discrete topology in suspension P+ areas is buried, can be with backward voltage It is pressure-resistant so as to improve that the depletion region of automatic extension both sides forms partial pressure buffer structures；Simultaneously when surge voltage is excessive, both sides Depleted region continues extension and overlapped, plays block effect, protects the gate oxide of the area of grid of inside, plays certain Peak voltage overvoltage protection effect.
Although certain conducting resistance can be increased after the burial uniform discrete topology in suspension P+ areas is introduced, enhancing is provided with The voltage endurance capability of device and shielding protection is played to grid, can also reduced to a certain extent to more than 3300V devices to high quality The requirement of epitaxy layer thickness.
Brief description of the drawings
Fig. 1 is lateral DMOS FET structure cells schematic diagram in the prior art；
Fig. 2 is the carborundum flat-grid MOSFET component structure cell schematic diagram with burial suspension knot of the present invention；
The process that the burial uniform discrete topology in suspension P+ areas is constructed by secondary epitaxy that Fig. 3 is the present invention is illustrated Figure；
Fig. 4 is the injection reticle pattern schematic diagram of the burial suspension P+ areas difference buried structure of the present invention.
Embodiment
Below, refer to the attached drawing, the present invention is more fully illustrated, shown in the drawings of the exemplary implementation of the present invention Example.However, the present invention can be presented as a variety of multi-forms, it is not construed as being confined to the exemplary implementation described here Example.And these embodiments are to provide, so that the present invention is fully and completely, and it will fully convey the scope of the invention to this The those of ordinary skill in field.
As shown in Fig. 2 the present invention provides a kind of carborundum flat-grid MOSFET component cellular knot for having and burying the knot that suspends Structure, the structure cell include drain electrode 1, source electrode 2, grid 3, substrate 4, drift layer 5 (N- drift layers), P-well areas 6, p+ areas 7 And n+ areas 8；Be dispersed with the drift layer 5 of the lower section of p-well areas 6 one or more layers constructed by multiple burial suspension P+ areas 9 it is equal The discrete topology of even distribution.The discrete topology and the vertical range in p-well areas 6 are 0-10um.Bury the section in suspension P+ areas 9 It is square, is circular, hexagon or annular.
As shown in figure 3, the uniform discrete topology that the burial suspension P+ areas 9 of the application are formed can be silicon carbide N type extension Secondary epitaxy N- drift layers are formed after piece P+ ions 10 inject, and injection mask 11 is first set before injection；It can also be silicon carbide N type The direct high-energy of epitaxial wafer injects the burial P+ to be formed knots.
As shown in figure 4, it is the square injection mask plate in P+ areas, the circular injection mask plate in P+ areas, P+ areas six successively from top to bottom Side shape injection mask plate and P+ areas annular injection mask plate.
The application is covered by being distributed one or more layers under the p-well areas of carborundum flat-grid MOSFET component cellular The uniform discrete topology in suspension P+ areas is buried, the voltage endurance capability of device can be strengthened, while shielding protection effect is played to grid；The opposing party Face, also make it that the JFET regions design of cellular is more flexible.
It is described above simply to illustrate that of the invention, it is understood that the invention is not limited in above example, meets The various variants of inventive concept are within protection scope of the present invention.

Claims (3)

1. a kind of have the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends, the structure cell includes leakage Pole, source electrode, grid, substrate, drift layer, P-well areas, p+ floor and n+ floor；Characterized in that, below the p-well areas One or more layers equally distributed discrete topology constructed by multiple burial suspension P+ areas is dispersed with the N- drift layers.
2. according to claim 1 have the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends, it is special Sign is that the discrete topology and the vertical range in the p-well areas are 0-10um.
3. according to claim 1 have the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends, it is special Sign is, the section in the burial suspension P+ areas is square, circular, hexagon or annular.
CN201710857440.2A 2017-09-21 2017-09-21 It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends Withdrawn CN107742646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710857440.2A CN107742646A (en) 2017-09-21 2017-09-21 It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710857440.2A CN107742646A (en) 2017-09-21 2017-09-21 It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends

Publications (1)

Publication Number Publication Date
CN107742646A true CN107742646A (en) 2018-02-27

Family

ID=61236124

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710857440.2A Withdrawn CN107742646A (en) 2017-09-21 2017-09-21 It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends

Country Status (1)

Country Link
CN (1) CN107742646A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540209A (en) * 2021-06-04 2021-10-22 复旦大学 Radiation reinforcement SiC device structure based on distributed capacitance
CN118136677A (en) * 2024-05-07 2024-06-04 上海陆芯电子科技有限公司 Planar gate type power metal-oxide field effect transistor and power device
WO2024206640A1 (en) * 2023-03-28 2024-10-03 Purdue Research Foundation Vertical dmosfets with buried shield for reduced gate-to-drain charge

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010020732A1 (en) * 1998-07-07 2001-09-13 Gerald Deboy Vertical semiconductor component having a reduced electrical surface field
JP2001274395A (en) * 2000-03-28 2001-10-05 Toshiba Corp Semiconductor device and manufacturing method thereof
US20020096715A1 (en) * 2001-01-25 2002-07-25 Wataru Sumida Semiconductor device
CN1855546A (en) * 2005-04-28 2006-11-01 恩益禧电子股份有限公司 Semiconductor device
CN104380472A (en) * 2012-07-25 2015-02-25 住友电气工业株式会社 Silicon carbide semiconductor device
EP2889915A1 (en) * 2013-12-30 2015-07-01 ABB Technology AG Power semiconductor device
CN105190899A (en) * 2013-03-11 2015-12-23 住友电气工业株式会社 Silicon carbide semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010020732A1 (en) * 1998-07-07 2001-09-13 Gerald Deboy Vertical semiconductor component having a reduced electrical surface field
JP2001274395A (en) * 2000-03-28 2001-10-05 Toshiba Corp Semiconductor device and manufacturing method thereof
US20020096715A1 (en) * 2001-01-25 2002-07-25 Wataru Sumida Semiconductor device
CN1855546A (en) * 2005-04-28 2006-11-01 恩益禧电子股份有限公司 Semiconductor device
CN104380472A (en) * 2012-07-25 2015-02-25 住友电气工业株式会社 Silicon carbide semiconductor device
CN105190899A (en) * 2013-03-11 2015-12-23 住友电气工业株式会社 Silicon carbide semiconductor device
EP2889915A1 (en) * 2013-12-30 2015-07-01 ABB Technology AG Power semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540209A (en) * 2021-06-04 2021-10-22 复旦大学 Radiation reinforcement SiC device structure based on distributed capacitance
WO2024206640A1 (en) * 2023-03-28 2024-10-03 Purdue Research Foundation Vertical dmosfets with buried shield for reduced gate-to-drain charge
CN118136677A (en) * 2024-05-07 2024-06-04 上海陆芯电子科技有限公司 Planar gate type power metal-oxide field effect transistor and power device

Similar Documents

Publication Publication Date Title
US9093493B2 (en) Wide bandgap insulated gate semiconductor device
US7126169B2 (en) Semiconductor element
US7989882B2 (en) Transistor with A-face conductive channel and trench protecting well region
CN109155337B (en) Electric field shielding in silicon carbide Metal Oxide Semiconductor (MOS) device cells using channel region extensions
CN103035706B (en) A kind of vertical gallium nitride radical heterojunction field effect transistor with polarization doping current barrier layer
CN102201406B (en) Bipolar CMOS DMOS (BCD) integrated device based on N type extension layer and manufacture method thereof
US20090273031A1 (en) Semiconductor device
CN104201202B (en) Gallium-nitride-based heterostructure field effect transistor with composite barrier layers
CN108028282A (en) Semiconductor device and method for manufacturing semiconductor device
JP2020077800A (en) Semiconductor device
CN106663693A (en) Silicon carbide semiconductor device
CN113257922B (en) Multi-channel enhanced gallium oxide junction field effect transistor
US7829898B2 (en) Power semiconductor device having raised channel and manufacturing method thereof
CN114447102A (en) Gallium nitride heterojunction field effect transistor with compound semiconductor layer on substrate
CN107742646A (en) It is a kind of that there is the carborundum flat-grid MOSFET component structure cell for burying the knot that suspends
CN108010958A (en) It is a kind of that there is the silicon carbide SBD device for burying suspend knot and periphery deep trench protection structure
CN115360238A (en) Honeycomb layout of semiconductor device
TW201539581A (en) SiC-trench-transistor and process for its production
KR20200039235A (en) Semiconductor device and method manufacturing the same
JPH06334188A (en) Semiconductor device
US7626232B2 (en) Voltage-controlled semiconductor device
CN104167444A (en) Gallium-nitride-based heterojunction field effect transistor with local cap layer
JP2019160901A (en) Semiconductor device
CN113363322B (en) N-channel trench VDMOS and trench IGBT
CN106783993A (en) Gallium nitride heterojunction FET with complex media Rotating fields in substrate

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication

Application publication date: 20180227

WW01 Invention patent application withdrawn after publication