EP0957420B1 - Clamping circuit - Google Patents

Description

The invention relates to a clamping circuit for generating a predetermined minimum voltage with cross-coupled first and second transistors according to the preamble of claim 1, which switches from normal operation to terminal operation, when the voltage of one supplied via an input path Signal drops below a predetermined clamping voltage.

Clamping circuits generally serve to level one to keep the signal present at a certain minimum value. Such clamping circuits are of great importance found the application of integrated circuits. A sinking of input signals in the range of a diode voltage below the ground potential and below that would namely cause that over in any integrated circuit existing parasitic device currents flow to neighboring ones Components or even the entire function of the Disrupt circuit. This danger is special, for example great if in electronic circuitry with multiple supply voltages and ground connections Error in the form of an open ground connection. Especially in safety-critical applications (for example in electronic systems in automotive electronics) It must be ensured that the error is not circuit parts directly affected are not influenced.

To solve this problem, the circuit shown in FIG. 5a with four npn transistors T1, T2, T5, T6 and a current source I _{bias is} known, for example. The first and second transistors T1 and T2, which each have a very steep output characteristic, are cross-connected.

The emitter of the first transistor T1 (output transistor) is connected to an input path Vp. the one to be monitored Input signal is present. With such a circuit a good protective effect can be achieved in clamping operation, the desired clamping voltage being observed very precisely becomes. However, this known circuit has the disadvantage that not for operation with high input voltages (for Example 40V or more) is suitable. This is because the first transistor T1, which is an NPN transistor acts due to its relatively low emitter base breakdown voltage only little strength against has such positive input voltages.

As a remedy for this, it is known to make the circuit shown in FIG. 5a according to FIG. 5b voltage-proof with a first diode D1 between the emitter of the first transistor T1 and the input path Vp for the input voltage, a second diode D2 on the emitter of the second for reasons of symmetry Transistor T2 is required. This enables the required clamping voltage to be maintained. However, this circuit has the disadvantage that the current-dependent forward voltage of the first diode D1 distorts the clamping voltage and thus the protective effect in the clamping operation is severely impaired. This problem can be partially solved by increasing the current I _bias . However, this measure has the consequence that the current through the first transistor T1 increases before the predetermined clamping voltage is reached, and thus the total current consumption of the clamping circuit also increases undesirably in normal operation.

From US 5,519,341 is a comparator circuit with cross-coupled Transistors known that the load current through a Transistor detected by means of a source resistor and detected at a predetermined current value. By means of a Flip-flops can limit the current through the transistor.

From US 5,576,616 is also an SA with cross-coupled Transistors known as the reference voltage source for an integrated circuit arrangement is used in which the Supply potential can fluctuate. The specified circuit arrangement is also insensitive to temperature fluctuations.

DE 25 49 575 is a circuit arrangement with cross-coupled Transistor described for connection to a special current or voltage source is provided. This generates one that is independent of the current or voltage source Signal.

Further such circuits are known from US 5614850, US 4764897 and US 5436552.

The invention has for its object a clamping circuit of the type mentioned at the beginning to create a high dielectric strength with exact adherence to the clamping voltage and at the same time has a low current consumption in normal operation.

This object is achieved according to claim 1 with a clamping circuit of the type mentioned at the outset, which is characterized by a third transistor M3, which is in the input path is switched that he is in the clamp operation of the circuit reverse conducting state and in normal operation of the circuit is in the forward locked state.

This solution combines two main advantages. As a result of that in clamp operation the current over the low-resistance channel and does not flow through the reverse diode RD of the transistor on the one hand, the protective function of the clamping circuit is not disturbed. On the other hand, the third transistor protects in normal operation M3 the first transistor T1 before too high voltages of the input signal, so that the desired dielectric strength the clamping circuit can be achieved.

The subclaims contain advantageous developments the invention.

Thereafter, the third transistor M3 is preferably a D-MOS field effect transistor, the gate connection of which is connected to a supply voltage V _DD for switching on the field effect transistor.

For at least partial compensation of the on-resistance of the third D-MOS field effect transistor M3 is preferred a fourth D-MOS field effect transistor M4 is provided, the one in the emitter of a fifth, through a third diode D3 connected to the supply voltage transistor T5 is, the gate terminal of the third transistor M3 connected to the collector of the fifth transistor T5 is.

Furthermore, all transistors and the third diode can be used be replaced by field effect transistors.

The clamp circuit is particularly suitable for use in connection provided with integrated circuits, the Clamp voltage in this case is 0 volts. The clamp circuit is also particularly in the BICDMOS (Bipolar, C and D-MOS) technology realizable.

Fig. 1

ein Schaltbild einer ersten Ausführungsform der Erfindung;

Fig. 2

ein Schaltbild einer zweiten Ausführungsform der Erfindung;

Fig. 3

ein Schaltbild einer dritten Ausführungsform der Erfindung;

Fig. 4

die Ausgangskennlinien der in den Figuren 1 bis 3 gezeigten Schaltungen und

Fig. 5a und 5b

eine Klemmschaltung gemäß dem Stand der Technik.

Further details, features and advantages of the invention will become apparent from the following description of preferred embodiments with reference to the drawing. Show it:

Fig. 1

a circuit diagram of a first embodiment of the invention;

Fig. 2

a circuit diagram of a second embodiment of the invention;

Fig. 3

a circuit diagram of a third embodiment of the invention;

Fig. 4

the output characteristics of the circuits shown in Figures 1 to 3 and

5a and 5b

a clamping circuit according to the prior art.

The prior art was already explained at the beginning with reference to FIGS. 5a and 5b. In contrast, Figure 1 shows a first embodiment of the invention, which has a third transistor M3 in the form of a self-blocking n-channel insulating layer field-effect transistor (D-MOS-FET), which is connected in the input path Vp of the clamping circuit, and the gate of which with a positive supply voltage V _{DD is} connected, which is sufficient to switch it on completely (for example 5V). A reverse diode RD of the field effect transistor M3 is indicated by dashed lines. Finally, there is a Zener diode ZD between the emitter of the first transistor T1 and ground.

Is in normal operation with positive input voltage the field effect transistor M3 in forward locked mode and thus protects the first transistor T1 of the clamping circuit against too high input voltages. The Zener diode ZD prevents an impermissible charging of the emitter of the first transistor T1 through the blocked through the field effect transistor M3 flowing reverse current.

The input voltage applied to the input path Vp drops to ground potential, the field effect transistor M3 goes in the reverse conducting state, and the circuit arrives in the clamp mode, in which the input signal over the first and second transistor T1, T2 connected to ground and thus preventing a further drop in the input voltage becomes. In this case, the current flows through the low-impedance Channel of the field effect transistor M3 and not via the reverse diode RD, so that the clamping voltage is not as in the beginning is distorted with reference to the circuit explained in FIG. 5b, but remains unaffected. Consequently, the protective function the clamping circuit is not affected.

Figure 2 shows a second embodiment of the invention, the compared to the first embodiment, a fourth transistor in the form of a D-MOS field effect transistor M4 and a third Has diode D3. The fourth transistor M4 is in the Emitter of the fifth transistor T5 switched while on the third diode D3 in the collector circuit of the fifth transistor T5 is located.

With this second embodiment, the influence of the on-resistance can of the third transistor M3 (field effect transistor) partially or fully compensated. For reasons of stability the fourth transistor M4 must face one the third transistor M3 smaller or the same on resistance exhibit. This mating property can in particular can be produced in that the two field effect transistors M3 and M4 operated under the same conditions become. This is switched into the collector circuit third diode D3, by an inverse operation of the fourth transistor M4 and in that the gate terminal of the third transistor M3 between the third Diode D3 and the collector of the fifth transistor T5.

This second embodiment also has the advantage that the input voltage present at the input path Vp is more precisely limited than in the first embodiment according to FIG Figure 1. When the voltage drop across the fourth transistor M4 becomes so large that the first transistor T1 saturates goes, the current can flow through the first and fifth Transistor T1, T5 no longer rise, and the output voltage sinks.

Figure 3 shows a third embodiment of the invention. This differs from the second shown in Figure 2 Embodiment in that the transistors T1, T2, T5 and T6 and the third diode D3 each through n-channel insulating layer field-effect transistors (MOS) M1, M2, M5, M6 or M7 are replaced. For safe operation of this Circuitry requires that the first and fifth Transistors M1, M5 each have the same transfer characteristic.

As the inverse diode of the fourth transistor M4 begins to conduct, before the drain-source voltage of the first transistor M1 becomes too small, this circuit does not have the same Current limiting effect like the second shown in Figure 2 Embodiment. Only if due to the lower drain-source voltage of the first transistor M1 compared to that fifth transistor M5 the transfer characteristics of both transistors deviate from each other, the output voltage increases increasing amount of output current slowly decreases.

Figure 4 finally shows output characteristics 1, 2 and 3 of the first, second and third embodiment, respectively vertical axis the output voltage and on the horizontal Axis of the output current is plotted.

LIST OF REFERENCE NUMBERS

T1 / M1

- First transistor / first field effect transistor

T2 / M2

- Second transistor / second field effect transistor

M3

- third field effect transistor

M4

- fourth field effect transistor

T5 / M5

- fifth transistor / fifth field effect transistor

T6 / M6

- sixth transistor / sixth field effect transistor

M7

- Seventh field effect transistor

D1

- first diode

D2

- second diode

D3

- third diode

ZD

- Zener diode

RD

- reverse diode

V _DD

- supply voltage

I _bias

- power source

vp

- Entry path

Claims (6)

1. Clamping circuit for generating a predetermined minimum voltage with cross-coupled first and second transistors (T₁, T₂), which changes over from a normal mode to a clamping mode if the voltage of a signal fed via an input path (Vp) falls below a predetermined clamping voltage, characterized in that a third transistor (M3) is connected into the input path (Vp) in such a way that it is in the reverse conducting state in the clamping mode of the circuit and in the forward blocked state in the normal mode of the circuit.
2. Clamping circuit according to Claim 1,
   in which the third transistor is a D-MOS field-effect transistor (M3), whose gate terminal is connected to a supply voltage (V_DD) for activating the field-effect transistor.
3. Clamping circuit according to Claim 2,
   in which a zener diode (ZD) is provided at the emitter of the first transistor (T1) for the purpose of preventing impermissible charging of the emitter by the reverse current flowing via the switched-off third transistor (M3).
4. Clamping circuit according to Claim 2 or 3,
   in which a fourth D-MOS field-effect transistor (M4) is provided, which, in order to at least partly compensate for the on resistance of the third D-MOS field-effect transistor (M3), is connected into the emitter of a fifth transistor (T5), which is connected to the supply voltage (VDD) via a third diode (D3), the gate terminal of the third transistor (M3) being connected to the. collector of the fifth transistor (T5).
5. Clamping circuit according to one of the preceding claims,
   in which the first, second, fourth and fifth transistors (T1, T2, T4, T5) and the third diode (D3) are in each case MOS field-effect transistors (M1, M2, M4, M5, M7).
6. Clamping circuit according to one of the preceding claims, in particular for use in connection with integrated circuits,
   in which the clamping voltage is 0 volts.

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