EP0951711A1 - Procede de commande d'adressage d'un panneau a plasma de type alternatif - Google Patents
Procede de commande d'adressage d'un panneau a plasma de type alternatifInfo
- Publication number
- EP0951711A1 EP0951711A1 EP98902028A EP98902028A EP0951711A1 EP 0951711 A1 EP0951711 A1 EP 0951711A1 EP 98902028 A EP98902028 A EP 98902028A EP 98902028 A EP98902028 A EP 98902028A EP 0951711 A1 EP0951711 A1 EP 0951711A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- addressing
- voltage
- pulse
- electrodes
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000012423 maintenance Methods 0.000 claims abstract description 77
- 238000012790 confirmation Methods 0.000 claims description 14
- 230000000873 masking effect Effects 0.000 claims description 13
- 238000012986 modification Methods 0.000 claims 1
- 230000004048 modification Effects 0.000 claims 1
- 230000009467 reduction Effects 0.000 abstract description 10
- 230000006870 function Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000003446 memory effect Effects 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000035508 accumulation Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000020411 cell activation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
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- 239000003989 dielectric material Substances 0.000 description 1
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- 230000003389 potentiating effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000002211 ultraviolet spectrum Methods 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
- G09G3/2922—Details of erasing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
- G09G3/2932—Addressed by writing selected cells that are in an OFF state
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/297—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using opposed discharge type panels
Definitions
- the present invention relates to a method for controlling the addressing of an alternative type plasma panel. Its implementation makes it possible, in particular, for components used for addressing operations, to reduce the performance necessary for these components and therefore to reduce their cost.
- the invention also relates to a plasma panel operating according to this method.
- Plasma panels or plasma screens are flat display screens, which use the emission of radiation in the visible or ultraviolet spectrum from a discharge in gas.
- the PAP are mainly made up of two large families, the PAP of the so-called continuous type and the PAP of the so-called alternative type.
- PAPs of the alternative type because of their particular structure, benefit in their operation from an effect called "memory effect" which makes them particularly suitable for constituting large screens with a large number of elementary cells, both for professional and large applications audience, such as high definition color television.
- each cell is defined at the crossing of a pair of so-called maintenance electrodes, with one or more other electrodes used more particularly for addressing the cells.
- the addressing functions and those aimed at producing light energy are dissociated: the light production results from an application 'in parallel' to all the cells, of a signal in slots called "signal d 'interview".
- FIG. 1 the diagram shown in FIG. 1 is that of a PAP with two crossed electrodes to define a cell.
- the PAP comprises a screen 1 formed using a network of electrodes Y1 to Y6 called “line electrodes” crossed with a second network of electrodes X1 to X6 called column electrodes. At each intersection of line and column electrodes corresponds to a cell C1 to C36. These cells are thus arranged along lines L1 to L6 and columns CL1 to CL6. In the example of FIG. 1, only 6 electrodes of each type are represented, but a PAP can comprise 1000 or plus row electrodes and as many column electrodes defining 1 million or more cells.
- Each line electrode Y1 to Y6 is connected to a line output stage SY1 to SY6 of a line 2 management device, and each column electrode X1 to X6 is connected to a column output stage SX1 to SX6 of a management device column 3.
- the operations of these two management devices 2, 3 are controlled by an image management device 4.
- the line 2 management device comprises:
- maintenance amplifier A1 producing signals called "maintenance signals" SE used for the activation of cells C1 to C36; taking into account the large power under which the signals SE must possibly be delivered, they can be supplied using a first and a second amplifier A1, A2 as in the example shown;
- first and a second line control circuits 6, 7 (which correspond to circuits called "line driver” by specialists in the field).
- the latter each respectively comprise three switching stages M1 to M3 and M4 to M6 each connected to the input of a line output stage SY1 to SY3 and SY4 to SY6, so that the first circuit 6 controls the first three row electrodes Y1 to Y3 and the second circuit 7 controls the following three electrodes Y4 to Y6.
- Each line control circuit 6, 7 is connected to one of the amplifiers A1, A2 from which it receives the maintenance signals SE, and it has the function in particular: on the one hand, of transmitting these signals SE so that they are applied simultaneously to all the line electrodes Y1 to Y6 which it controls; on the other hand, it has the function, for the electrode or electrodes selected for an addressing operation, of superimposing on the maintenance signals SE either a so-called recording pulse IS or a so-called erasing pulse IE, depending on the type of addressing to be performed.
- the function of the column management device 3 is in particular to apply a reference potential to the column electrodes X1 to X6, with respect to which so-called masking IM pulses are applied to some of these electrodes during addressing operations.
- it has a column control circuit 8, similar for example to the line control circuits 6, 7, and comprising in the example, 6 switching stages M7 to M12 each connected to a column output stage SX1 to SX6, and who are responsible for developing and switching the masking pulses.
- each cell has a space filled with gas.
- the ignition voltage "VA between the two electrodes which define a given cell By applying a sufficient voltage called the ignition voltage "VA between the two electrodes which define a given cell, an electrical discharge is caused in the gas, and an emission of light by this cell.
- the electrodes are covered with dielectric material.
- electrical charges build up on the dielectric at the electrodes which define a cell in which the discharge occurs.
- These electrical charges remain after the discharge and constitute a field electric says thamps of internal memory "specific to each cell, and allow, for the cell which has it, to cause a discharge with the application of a voltage lower than the ignition voltage. This effect constitutes the memory effect "already mentioned. Cells which have such charges are said to be in the Registered" or "on” state.
- the other cells require to produce a discharge a voltage equal to the ignition voltage, they are say 'erased' or 'off'.
- the application of the SE maintenance signals has the effect of activating cells C1 to C36 which are in the "registered” state, ie to cause discharges in these cells, without modifying their state or the state cells that are in the 'erased' state!
- the cells are put in the state Inscrifou the state "erased” according to an image to be displayed, by addressing operations often carried out line by line, ie for all cells C1 to C36 belonging to the same line L1 to L6 (or in other words, for all the cells defined along the same electrode line Y1 to Y6), then thereafter for all the cells of another line.
- V2a represents maintenance signals SE of a current type, intended to be applied to all the line electrodes Y1 to Y6
- They consist of negative voltage slots 9 and positive 10 established on either side of a reference potential V0 (which is often the potential of the mass), and which follow one another with opposite polarities. They vary between a negative potential V1 where they present a so-called negative level p-, and a positive potential V2 where they present a so-called positive level p +.
- negative and positive V1, V2 have for example a value of 150 volts, which is added to the voltage produced by the internal memory field, to substantially reach the value of ignition voltage VA.
- the voltage transition which follows the end of a slot 9; 10 can lead directly to the start of the next slot, or as in the example shown: on the one hand the negative slots 9 are separated from the positive slot 10 which follows by a wide intermediate stage 5, formed at the level of the reference potential V0 and intended to serve as the basis for an addressing pulse; and on the other hand, each positive slot 10 is separated from the negative slot which follows by a narrow intermediate bearing 11, formed on the reference potential V0.
- the reference potential V0 is applied to the column electrodes X1 to X6, so that the application of each of the positive and negative slots of the maintenance signals SE to the row electrodes Y to Y6, develops voltages alternately of signs across the cells. opposite, which generate so-called maintenance discharges in all the cells which are in the "registered" state.
- FIG. 2b represents the phase relationship between the maintenance discharges Id in cells C1 to C36, and the establishment of slots 9, 10.
- the slots 9, 10 of the maintenance signal SE follow one another with a period P1, P2, P3, P4 (usually of the order of 20 microseconds), during which the addressing of all the cells defined by an electrode takes place.
- selected line or by several in some cases).
- the addressing operations are carried out by the line and column control circuits 6,7, which for this purpose deliver specific signals.
- the addressing consists, for the line control circuit 6, 7 and using in particular that of the switching stages M1 to M6 corresponding to the selected line electrode, to superimpose the maintenance signal SE applied to this electrode, an erase pulse IE followed by an IS enrollment pulse.
- FIGS. 2c, 2d and 2e respectively illustrate addressing operations carried out on the cells of the line electrodes Y1, Y2 and Y3, which electrodes are controlled by the first line 6 control circuit. Assuming that the addressing of the electrode line Y1 takes place during a period P1 starting at an instant tO: the signal applied only to this electrode has the function of putting in the "erased" state all the cells of this electrode.
- an addressing pulse called erase IE of positive polarity
- This erase pulse IE may have a relatively slow rise time Tm, and its amplitude V4 is such that s we reach a value V3 called erase voltage "slightly lower for example than the voltage V2 of the positive slots 10.
- Such a signal applied to the line electrode Y1 while the reference potential V0 is applied to all the electrodes columns, causes a start of discharge in the cells which are in the Registered state "and has the effect of absorbing the charges electrical accumulations and therefore to delete the internal memory fields at the level of all cells.
- the erasure can also be accomplished, using an erasure pulse IE '(shown in dotted lines) superimposed at the instant tO during the establishment of the negative slot 9, and the shape of which makes it possible to confer at this establishment time a long time without modifying its amplitude.
- this addressing is accomplished under the action of the first switching stage M1, to be applied only to the first line electrode Y1. All the cells of the selected electrode Y1 being erased, the next phase consists in putting in the "registered" state only the selected cell or cells.
- a recording pulse IS is superimposed on the maintenance signal SE at an instant t2, on the positive bearing p +.
- the pulse IS has an amplitude V5 such that with this superposition, the resulting voltage V2 + V5 reaches a voltage value known as writing of value comparable to the ignition voltage VA. If at this time, the potential delivered by all the column output stages SX1 to SX6, i.e. the potential applied to all the column electrodes X1 to X6, is that of the reference potential V0, the potential difference at the terminals of cells C1 to C6 formed with the line electrode Y1 has the value of the ignition voltage VA: consequently discharges occur in all cells which consequently benefit from an internal memory field, and are therefore in the "registered" state.
- the column electrode management device 3 produces, at each IS recording pulse, a nasalisation sequence "which consists in applying to those of the column electrodes X1 to X6 which define a cell which must remain at the "erased” state, a masking pulse IM in phase with the recording pulse IS, the function of which is to prevent the potential difference across these cells from reaching the ignition value VA, and thus inhibit the action of the IS registration pulse.
- FIG. 2f represents a masking pulse IM delivered on the second column electrode X2, at time t2, that is to say in phase with the writing pulse IS applied to the first row electrode Y1.
- the IM masking pulse is positive, and its presence at this time makes that, at the end of the addressing cycle on the first line electrode Y1, the cell C2 retains an "erased" state.
- FIG. 2d illustrates the addressing carried out on the second line electrode Y2 (using the second switching stage M2), during a second period P2 which follows the first period P1.
- the addressing begins with an erasure of all the cells (C7 to C12 in the present case) using an erasure pulse IE, superimposed on a wide intermediate level 5 at an instant t3 , and this only for the second line electrode Y2.
- an IS recording pulse is superimposed on the positive bearing 10 and produces the setting in the status "Registered" of all the cells of this line for which no IM masking pulse is applied to the electrode corresponding column X1 to X6.
- no masking pulse (FIG. 2f) being applied to the second column electrode X2 at time t4, cell C8 is set to the "registered" state.
- FIG. 2e shows the addresses carried out on the third line electrode Y3 (using the third switching stage M3), during a third period P3 which follows the second P2.
- an erase pulse IE is superimposed on the large intermediate level pi.
- a registration pulse IS is superimposed on the positive level p +.
- the addressing (not shown) on the line electrodes Y4, Y5, Y6 is then carried out in the same way, starting with that of the electrode Y4 which is carried out during the period P4.
- the addressing operations described above are of two types: the addressing which consists in putting in the same “erased” state all the cells of the same line electrode without distinction, is of the type “semi-selective addressing; and that which consists in putting selected cells in the Registered state "is of the type” selective addressing "But semi-selective and selective addressing can also consist, in putting all the cells of a same line in the Registered state” to the "semi-selective, 'and in the' erased 'state, certain selected cells, as regards the" selective.
- These explanations on the operation of an alternative PAP highlight the importance, the large number and the complexity of the functions fulfilled by a line or column control circuit 6, 7 or 8. To ensure all these functions, these control circuits are themselves complex electronic components. Their manufacture uses technologies that are all the more sophisticated and expensive as the performance required for these components is high.
- the line control circuits 6, 7 must have much more efficient technical characteristics for delivering the addressing pulses IS, IE, than for delivering the maintenance signals SE. Indeed, the latter are permanently applied to all the electrodes Y1 to Y6, they do not have to be neither selected nor switched, they are produced by the amplifiers A1, A2 and only pass through the switching stages M1 to M6. Addressing pulses, on the contrary, use different complex electronic circuits to be constructed, selected, switched and superimposed on the maintenance signals with the appropriate synchronism and speed, as well as with sufficient power to possibly generate discharges simultaneously in a large number of cells.
- One of the aims of the present invention is to allow the use, in alternative PAPs, of line control and / or column control circuits having the lowest cost.
- Another object of the invention is to reduce the so-called capacitive consumption of alternative PAPs.
- the capacities presented by the various elements such as for example, the tracks which constitute the electrodes, the different connections, and the capacities specific to electronic circuits, form a relatively large overall capacity, consuming alternating currents.
- the invention proposes to make selective and / or semi-selective addressing in a way which makes it possible to reduce the amplitude of the addressing pulses distributed by the control circuits 6, 7, 8.
- the invention relates to a method for controlling the addressing of an AC plasma panel comprising at least one array of so-called row electrodes crossed with at least one array of so-called column electrodes, cells being formed at the intersections of the row electrodes. and columns, said method consisting in applying to all the line electrodes maintenance signals formed by a succession of slots having a given period and established with respect to a reference potential applied to the column electrodes, each period possibly constituting a cycle d addressing comprising at least one addressing of the semi-selective type and at least one addressing of the selective type, each type of addressing consisting in applying to at least one selected line electrodes, a so-called addressing pulse whose voltage is added to a so-called line voltage already present on this electrode, with a view to applying to the terminals of cells formed by this electrode selected a so-called addressing voltage of given value corresponding to the addressing to be carried out, the method being characterized in that for at least one of the two types of addressing, the addressing pulse has an amplitude
- the method according to the invention consists in superimposing on the maintenance signals during a period of the latter, at least one voltage level called the additional level so as to constitute a voltage base called the addressing base on which is superimposed at least one addressing pulse.
- the method according to the invention consists in forming a registration addressing voltage base with a slot and superimposing on this addressing base an addressing pulse consisting of a pulse so-called registration.
- the method consists in establishing between two consecutive slots, an intermediate bearing having a voltage lower than the voltage of the slots and in adding to said intermediate bearing an additional bearing in order to constitute an erasing addressing base and then superimposing on this base of erase, an addressing pulse consisting of an erase pulse.
- the intermediate bearing is at the same voltage as the reference potential.
- the additional landings added on slots are superimposed on these after an instant when a so-called maintenance discharge occurs.
- the additional landings formed on slots are eliminated substantially at the end of these slots.
- the additional steps formed on slots encompass the whole of one or more addressing pulses of a selected row electrode.
- the additional steps used to constitute an erasing base have an amplitude equal to or greater than the difference between a so-called erasing voltage and the amplitude of the erasing pulses.
- FIG. 3 shows an alternative PAP implementing the method
- FIG. 4a to 4j show signals applied to the PAP electrodes of Figure 3 in accordance with the method of the invention
- FIG. 5 represents maintenance signals in the case of addressing of the so-called multiple type;
- - Figures 6a, 6b, 6c illustrate a version of the invention consisting in modifying a potential applied to column electrodes;
- FIG. 3 represents a PAP similar to that shown in FIG. 1 except with regard to its maintenance amplifiers A1 ⁇ A2 ', which include means allowing the implementation of the method of the invention.
- Each amplifier A1 ⁇ A2 comprises a maintenance generator 12, 14 in itself conventional, producing the maintenance signals SE, and with respect to the amplifiers A1, A2 of FIG. 1, they also comprise a circuit called' superposition "15 cooperating with the maintenance generator to superimpose on the maintenance signals SE, at given instants, voltage signals called" additional stages "PS.
- a maintenance generator 12, 14 may for example comprise a first and a second voltage source 25, 16 respectively negative and positive, one polarity of which is at the reference potential VO or ground in the example, and the other polarity of which delivers the negative voltage V1 (voltage of the negative slots 9) for the source 25, and delivers the positive voltage V2 (voltage of the psitive slots 10) for the source 16.
- the maintenance signal SE delivered at output 17 of an amplifier A1 ', A2', results from a switching of one of these three potent iel on this output 17; this switching is accomplished using of three switching elements symbolized in the figure by switches 11, 12, 13 respectively switching the negative potential V1, the positive potential V2, and that of the ground.
- the superposition circuit 15 comprises a third and a fourth voltage sources 18, 26 having a polarity connected to ground; the other polarity of the third and fourth sources respectively deliver a positive voltage V7 and a positive voltage V6 which corresponds to the amplitude of at least one of the additional steps.
- the voltage V7 is equal to the sum of the positive voltage V2 and the positive voltage V6 of the additional bearings.
- the voltages V6, V7 can be applied to the output 17 of the amplifier A1 ', A2' using respectively a fourth and fifth switching elements or switches 14, 15.
- a diode 19 disposed between the output 17 and the fourth voltage source 16 avoids any current flow therein due to the application of the voltage V7.
- a similar operation carried out with in particular negative voltage sources 18, 26, would make it possible to superimpose additional bearings of negative polarity.
- Figures 4a and 4g to 4j show signals intended to be applied to the line electrodes Y1 to Y6 of the PAP shown in Figure 3, in order to operate the latter in accordance with the invention.
- These signals include maintenance signals SE and erase and write pulses IE, IS, and their shape differs from that of the signals of the known art shown in FIGS. 2a, 2c, 2d, 2e in that, according to a characteristic of the invention, they also include the additional bearings PS1, PS2 mentioned above.
- the additional steps are superimposed on the maintenance signals SE, and the voltage which results from this first superposition forms a voltage base called the addressing base on which the addressing pulses IE, IS are themselves superimposed.
- the maintenance signals SE are made up like those shown in FIG. 2a, by a succession of negative and positive slots 9, 10, 9 ', 10' separated by intermediate bearings 5, 5 '; they are established with a period P1 to P4 and with respect to a reference potential V0 itself applied to the column electrodes X1 to X6.
- the additional stages PS1, PS2 include all of the addressing pulses of a selected line electrode.
- FIG. 4a represents an addressing cycle accomplished on the cells formed by the first line electrode Y1, during a period P1.
- the additional bearings PS1, PS2 are positive, they correspond respectively to an erasing operation and to a recording operation.
- the first additional stage PS1 is superimposed on the maintenance signals SE on a wide intermediate stage 5. It has a voltage lower in absolute value than the voltage V1, V2 of the slots.
- the wide intermediate stages 5 being at the reference potential VO, it is only the voltage V6 of the first additional stage PS1 which serves as the erasing base b1 to the erasing pulse IE.
- This voltage V6 has a value for example of 50 volts; assuming that the erasing voltage V4 is of the order of 120 volts, or slightly lower than those of negative and positive slots V1, V2 9, 10 (of the order of 150 volts), when the pulse d erasing IE is applied and superimposed on said base b1, it suffices that its amplitude V3 is of the order of 70 to 80 volts so that the erasing voltage V4 is obtained, and that erasing is carried out.
- the intermediate bearing 5 used to form the erasing base b1 is established between a negative slot 9 followed by a positive slot 10.
- the second level PS2 is superimposed on the positive slot 10.
- Its voltage V6 is in the example substantially the same as that of the first additional level (it is of course possible to give different values to the two additional levels if necessary) and s' adds to the voltage V2 of this slot, to constitute a second voltage base b2 intended to receive the registration pulse IS.
- the potential difference or writing voltage VA necessary for the registration of the cells is of the order for example 270 volts
- the voltage of the additional bearings PS1, PS2 is of the order of 50 volts
- the first level PS1 As for the first level PS1, it is applied largely after time td1 of the maintenance discharge due to the establishment of a negative stage p-, and it ends before the start of the positive stage p + which follows and therefore before the instant td2 of the discharge which follows.
- its amplitude V6 remains sufficiently lower than the voltage of the maintenance signals SE, so as not to itself generate a discharge (taking into account in particular the dispersions in the characteristics presented by the cells).
- the second level PS2 is superimposed on the positive slot 10, after the instant td2 when a maintenance discharge occurs, and its presence therefore in no way affects the conditions of this discharge. It should be understood that its amplitude remains limited to a value such that, added to the voltage V2 of the slot 10, the resulting voltage remains lower than that which is capable of causing discharges of the type of registration discharges.
- the second additional stage PS2 ends in phase with the end of the slot 10: consequently the voltage transition which follows and which leads to the reference potential V0 has a greater amplitude than that which it would have in the absence of the second additional stage PS2, but which has little influence on the maintenance discharge occurring at the instant td4 which follows, since this discharge is caused by the potential difference generated with the establishment of the negative slot 9 belonging to the following period P2. It can be seen that under these conditions, the superimposition on the maintenance signals SE of the first or second additional stage PS1, PS2 or of these two stages PS1, PS2 cannot significantly affect the maintenance discharges. Instead of the additional stages PS1, PS2 and the writing pulses IS and erasing IE being positive, they can be negative as illustrated diagrammatically in FIG.
- the first additional negative PS1 stage could be added to a wide intermediate stage 5 'leading to a negative slot 9' of the maintenance signal SE.
- a negative IE erase pulse would be added to the first additional stage PS1.
- the intermediate bearing 5 ′ serving to form an erasing base would be established between a positive slot 10 ′′, followed by a negative slot 9 ′ of the maintenance signal SE.
- the second additional negative PS2 landing would be superimposed on a negative slot 9 ' of maintenance signal SE. It would constitute a voltage base b2 to which would be added the IS negative registration pulse.
- Figures 4b, 4c, 4d, 4th, 4f to be read with Figure 4a respectively show the action of the first, second, third, fourth and fifth switches 11, 12, 13, 14 and 15 and illustrate the operation of a signal generator 12 cooperating with its superposition circuit 15, to produce during the first period P1, the maintenance signals SE with additional superimposed bearings.
- the first switch 11 With the start of the period P1, the first switch 11 is closed “(the other switches are” open 1 ) and applies the negative voltage V1 which corresponds to the negative level p-. At the end of the stage p-, the first switch 11 goes to the buverf state and the fourth switch 14 goes to the closed state "which determines the wide intermediate stage 5, with the first additional stage PS1 superimposed. At the end of the wide bearing 5, the switch 14 goes to the "open” state and the second switch 12 is closed and applies the voltage V2 corresponding to the positive bearing p + of the positive slot 10.
- the second switch 12 retains its "closed” state until after the instant td2 when a maintenance discharge occurs, then it is open and it is the fifth switch 15 which goes to the closed state and applies the voltage V7 corresponding to the second additional stage PS2.
- the fifth switch 15 is open and the third switch 13 goes to the closed state and applies the ground potential; this corresponds to establishing the narrow intermediate bearing 11 until the start of the negative slot 9 which follows and which belongs to a following period P2.
- the additional stages PS1, PS2 can be designed and superimposed on the maintenance signals in different ways. For example, this can be done in a simple manner in each of the maintenance generators 12, 14 so that these additional bearings PS1, PS2 are applied simultaneously and permanently, to all the line electrodes Y1 to Y6 of the PAP, or else so that these additional steps are applied only to those of the line electrodes connected to a line control circuit 6, 7 in the process of addressing. This latter method corresponds to the example represented with the aid of FIGS.
- the addresses on the line electrodes Y2, Y3 are carried out respectively during the periods P2, P3, using additional steps and erasure and writing pulses IE, IS as shown below. above explained.
- FIG. 4i represents the addressing carried out at the period P4 which follows, on the fourth line electrode Y4 which it depends on the second line control circuit 7.
- the period P4 is that from which ceases the superposition of the additional stages PS1, PS2 on the maintenance signals SE distributed to the electrodes Y1 to Y3, and where on the other hand this superposition begins on the signals SE distributed to the electrodes Y4 to Y6.
- the addressing on the line electrode Y4 as well as those (not shown) then carried out at subsequent periods on the electrodes Y5, Y6, are carried out in the same way as explained above, by superposition of additional steps and erase and write pulses IE, IS.
- FIG. 5 represents the form of the maintenance signals SE ′ for such a “multiple pulse” addressing case.
- a period P'1 of the signals SE ′ making it possible to carry out a cycle d addressing, begins with a negative slot 9, followed by a positive slot 10a from which it is separated by a wide intermediate bearing 5 formed at the level of the reference potential VO; this positive slot 10a is followed by a narrow intermediate plateau 11 preceding another negative slot 9 which itself is followed by a narrow plateau 11; there is then a narrow positive slot 10b, then finally a narrow intermediate stage 11 which precedes a negative slot by a following period P2 '.
- the last negative and positive slots 9, 10b having the sole function of causing maintenance discharges, it is not superimposed on them with an additional bearing.
- the negative slot 9 has a duration T1, much less than the duration T2 of the positive slot 10a, duration T2 which corresponds to the time necessary to achieve the selective addressing of the cells formed along several generally controlled line electrodes by the same line control circuit, as is the case for example of the groups of line electrodes Y1 to Y3 and Y4 to Y6 controlled respectively by the control circuits 6, 7.
- control circuits of the type of circuits 6, 7 are commonly found, having several outputs each connected to a line electrode.
- Each of these control circuits can for example have 32, 40, 64 or even 128 outputs.
- an erase pulse IE which can, in the known art, be superimposed directly on a wide intermediate bearing 5, in order to simultaneously erasing all the cells from all the electrodes to which it is applied;
- these control circuits receive a series of writing pulses IS1, IS2, IS3, ..., ISn, these control circuits have the means which allow them to distribute each writing pulse to a line electrode, electrode by electrode; these registration pulses are each superimposed on the same positive slot of the SE signals, at different times along this slot.
- the registration of the cells of the n line electrodes can thus be accomplished using a single slot 10a, with high speed.
- FIG. 5 This organization according to the prior art is illustrated in FIG. 5 in which, in addition, and according to the invention, there is at least one additional bearing serving for the erase pulse IE, and / or for the write pulses IS1 at ISn.
- a first additional bearing PS1 ' On the wide intermediate bearing 5 which comprises the period P'1, is superimposed a first additional bearing PS1 ', having for example the same shape and the same value as those of the first bearing PS1 shown in FIG. 4a (assuming that the slots of the maintenance signals SE of FIG. 4a have the same value V1, V2 as those of the signals SE 'of FIG. 5).
- an erasure pulse IE symbolized in FIG. 5 in dotted lines
- FIG. 4a erasure pulse IE (symbolized in FIG. 5 in dotted lines) having the same value as that of FIG. 4a can therefore be superimposed, in order to perform the erasure.
- a second additional stage PS2 ′ is superimposed on the first positive slot 10a, after the instant td when the maintenance discharge produced by the establishment of this slot occurs.
- Inscriptions can therefore be obtained by superposing inscription pulses IS1, IS2, ..., ISn, on the voltage base b2 'resulting from the voltages of this additional bearing PS2' and the positive slot 10a, and by distributing these signals to the line electrodes as explained above.
- FIGS. 6a, 6b, 6c represent another way of compensating for the reduction in amplitude of the writing and erasing pulses, which consists in modifying the voltage applied to the column electrodes X1 to X6, or at least to those of these electrodes which define an addressed cell.
- FIG. 6a represents a period P'1 of maintenance signals SE 'similar to those of FIG. 5 (that is to say allowing addressing of the "multiple addressing" type), period which illustrates an addressing sequence performed according to this new version of the process of the invention.
- These signals include a negative slot 9 and a positive slot 10a separated by a wide intermediate bearing 5.
- This bearing 5 and this slot 10a are intended to receive respectively, an erase pulse IE and write pulses IS1, IS2, without prior overlapping of additional bearings.
- FIG. 6b represents variations of a voltage VX applied to a column electrode, the second electrode X2 for example (example which is valid for all the other column electrodes X1 to X6); these variations are due to signals constituted on the one hand, by IM masking pulses (which oppose the execution of an addressing), and on the other hand by so-called “confirmation” pulses or slots. , 31 which on the contrary favor the execution of the addressing. In the absence of these pulses, the voltage VX applied by the output SX2 to the electrode X2 has a value VX0 corresponding to the reference potential V0.
- the erasure pulse IE When the erasure pulse IE is superimposed on the large bearing 5, the resulting voltage reaches a value V3 (of 80 volts for example) lower than that of the voltage V4 (of the order of 120 volts) required to accomplish the erasure.
- the difference V4 - V3 is then compensated by the voltage VX applied to the electrode X2: for this purpose, a negative slot forming an erase confirmation pulse 30 having an amplitude Vce (of the order of 40 volts for example) , is then applied (in phase with the erase pulse IE), passing the voltage VX to a value -VX.
- This has the effect of increasing the potential difference applied to the terminals of the cells to be "erased” until it reaches the value of the erasing voltage V4.
- the column voltage VX then covers the value of the reference potential VO until the recording phase, or at least until after the instant td when a maintenance discharge occurs.
- the confirmation pulses have an amplitude equal to or greater than a difference between the addressing voltage and the voltage which on the selected line electrode results from the addressing pulse
- this writing phase comprises a first and a second writing pulse IS1, IS2 consecutive (applied to different line electrodes), having an amplitude V5 as superimposed on the positive slot 10a
- the resulting voltage V2 + V5 is less than the VA value required for registration
- a negative slot 31 constituting a pulse of confirmation of registration having an amplitude Vci (of l 'order for example of 40 volts) is then applied to the second electrode X2 (in phase with the first recording pulse IS1).
- FIG. 7 schematically represents such an organization, in which the closure of a first or a second or a third switching element 1, 2, P3, respectively causes the application to a column electrode X1 to X6, mass, negative voltage -VX, positive voltage + VX.
- the mass here constitutes the reference potential with respect to which the voltages of the maintenance signals are alternately positive and negative, but also constitutes the reference voltage V0'1 specific to the operation of the elements of the circuit of control column 8, and with respect to which the pulses 30, 31 and IM1 are delivered.
- FIG. 6c illustrates another method for producing the same addressing sequence as that of FIG. 6b with addressing pulses IE, IS1, IS2 of reduced amplitude, which makes it possible to use the outputs of the column control circuit 8 in a way that is more related to its most common possibilities, and in which the reference voltage V0'1 specific to the control circuit 8 is always negative with respect to the pulses 30, 31, IM1 delivered.
- the voltage VX on the column electrode X2 has the value VX0 corresponding to the reference potential V0, but which also corresponds at the first reference voltage V0'1 specific to the operation of the column control circuit 8.
- the confirmation slot or pulse 30 which is formed on the voltage VX results from a change in reference voltage specific to the control circuit: in fact, by the play of a switching (not shown, within the reach of any specialist in the field), we substitute for the first reference voltage V0'1 specific to the circuit 8, a second voltage of reference V0'2 negative with respect to the first and which corresponds to the value of the negative voltage -VX.
- This second reference voltage V0'2 is kept until the start of the following positive slot 10a, from which it is replaced by the first reference voltage V0'1, to achieve the end of the erase confirmation pulse. 30 before the instant td of a maintenance discharge and not risking modifying the conditions thereof. The confirmation of erasure is thus somehow integrated into the reference voltage.
- the second reference voltage V0'2 is again substituted for the first in order to produce the confirmation pulse d inscription 31.
- the first tension of reference V0'1 then replaces the second reference voltage V0'2 to form the end of this registration confirmation.
- a positive pulse is applied with respect to the value VXO which represents the reference potential VO as well as the first reference voltage specific to circuit 8, a positive pulse which constitutes a masking pulse IM1 and which during its duration gives the voltage VX the value + VX.
- the compensations for potential differences operated at the level of the voltage applied to the column electrodes X1 to X6, as described above, are particularly advantageous in terms of the reduction of the capacitive power (in particular because they lead to a large reduction in the amplitude of the masking pulses) because the capacity seen by the pulses distributed on the columns X1 to X6, is much greater than that encountered on the row electrodes Y1 to Y6.
- the reduction in amplitude of the addressing pulses IE, IS can also be compensated for by combining the amplitude of the additional steps with the amplitude of the confirmation slots.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of Gas Discharge Display Tubes (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9700075A FR2758204B1 (fr) | 1997-01-07 | 1997-01-07 | Procede de commande d'adressage d'un panneau a plasma de type alternatif |
FR9700075 | 1997-01-07 | ||
PCT/FR1998/000011 WO1998031001A1 (fr) | 1997-01-07 | 1998-01-06 | Procede de commande d'adressage d'un panneau a plasma de type alternatif |
Publications (2)
Publication Number | Publication Date |
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EP0951711A1 true EP0951711A1 (fr) | 1999-10-27 |
EP0951711B1 EP0951711B1 (fr) | 2001-10-24 |
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ID=9502410
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Application Number | Title | Priority Date | Filing Date |
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EP98902028A Expired - Lifetime EP0951711B1 (fr) | 1997-01-07 | 1998-01-06 | Procede de commande d'adressage d'un panneau a plasma de type alternatif |
Country Status (6)
Country | Link |
---|---|
US (1) | US6525703B1 (fr) |
EP (1) | EP0951711B1 (fr) |
JP (1) | JP2001507820A (fr) |
KR (1) | KR100484366B1 (fr) |
FR (1) | FR2758204B1 (fr) |
WO (1) | WO1998031001A1 (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2000000953A1 (fr) | 1998-06-30 | 2000-01-06 | Daewoo Electronics Co., Ltd. | Appareil d'interface de donnees et systeme d'ecran a plasma a courant alternatif |
KR100869413B1 (ko) * | 1998-09-04 | 2008-11-21 | 파나소닉 주식회사 | 고화질과 고휘도를 표시할 수 있는 플라즈마 표시 패널구동방법 및 화상표시장치 |
JP3365324B2 (ja) * | 1998-10-27 | 2003-01-08 | 日本電気株式会社 | プラズマディスプレイ及びその駆動方法 |
KR100585633B1 (ko) * | 1999-06-02 | 2006-06-02 | 엘지전자 주식회사 | 고주파용 플라즈마 표시장치의 구동방법 |
KR100349924B1 (ko) * | 2000-10-13 | 2002-08-24 | 삼성에스디아이 주식회사 | 플라즈마 표시패널의 구동방법 |
WO2008127287A2 (fr) * | 2006-10-11 | 2008-10-23 | Biolife, L.L.C. | Matériaux et méthodes de traitement de plaies |
CN101887682B (zh) * | 2010-06-29 | 2013-01-23 | 四川虹欧显示器件有限公司 | 一种解决高温下pdp面低放电的方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US4496879A (en) * | 1980-07-07 | 1985-01-29 | Interstate Electronics Corp. | System for driving AC plasma display panel |
DE3486401T2 (de) * | 1983-12-09 | 1996-01-04 | Fujitsu Ltd | Verfahren zur Steuerung einer Gasentladungsanzeigevorrichtung. |
JPH0673066B2 (ja) * | 1984-04-28 | 1994-09-14 | ソニー株式会社 | 放電表示装置 |
FR2572805A1 (fr) | 1984-11-06 | 1986-05-09 | Thomson Csf | Procede de mesure du centrage d'un barreau cylindrique dans un revetement transparent cylindrique et dispositif de mise en oeuvre |
FR2635901B1 (fr) | 1988-08-26 | 1990-10-12 | Thomson Csf | Procede de commande ligne par ligne d'un panneau a plasma du type alternatif a entretien coplanaire |
FR2635902B1 (fr) | 1988-08-26 | 1990-10-12 | Thomson Csf | Procede de commande tres rapide par adressage semi-selectif et adressage selectif d'un panneau a plasma alternatif a entretien coplanaire |
FR2635900B1 (fr) | 1988-08-30 | 1990-10-12 | Thomson Csf | Panneau a plasma a adressabilite accrue |
FR2648953A1 (fr) | 1989-06-23 | 1990-12-28 | Thomson Tubes Electroniques | Panneaux a plasma a zones de decharges delimitees |
FR2662292B1 (fr) | 1990-05-15 | 1992-07-24 | Thomson Tubes Electroniques | Procede de reglage de la luminosite d'ecrans de visualisation. |
FR2741468B1 (fr) | 1995-11-17 | 1997-12-12 | Thomson Tubes Electroniques | Procede de commande d'un ecran de visualisation et dispositif de visualisation mettant en oeuvre ce procede |
JP3263310B2 (ja) * | 1996-05-17 | 2002-03-04 | 富士通株式会社 | プラズマディスプレイパネル駆動方法及びこの駆動方法を用いたプラズマディスプレイ装置 |
JP3221341B2 (ja) * | 1997-01-27 | 2001-10-22 | 富士通株式会社 | プラズマディスプレイパネルの駆動方法、プラズマディスプレイパネル及び表示装置 |
-
1997
- 1997-01-07 FR FR9700075A patent/FR2758204B1/fr not_active Expired - Fee Related
-
1998
- 1998-01-06 WO PCT/FR1998/000011 patent/WO1998031001A1/fr active IP Right Grant
- 1998-01-06 EP EP98902028A patent/EP0951711B1/fr not_active Expired - Lifetime
- 1998-01-06 JP JP53059598A patent/JP2001507820A/ja not_active Withdrawn
- 1998-01-06 US US09/331,892 patent/US6525703B1/en not_active Expired - Fee Related
- 1998-01-06 KR KR10-1999-7005024A patent/KR100484366B1/ko not_active IP Right Cessation
Non-Patent Citations (1)
Title |
---|
See references of WO9831001A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO1998031001A1 (fr) | 1998-07-16 |
KR20000069331A (ko) | 2000-11-25 |
KR100484366B1 (ko) | 2005-04-20 |
FR2758204A1 (fr) | 1998-07-10 |
FR2758204B1 (fr) | 1999-04-09 |
JP2001507820A (ja) | 2001-06-12 |
US6525703B1 (en) | 2003-02-25 |
EP0951711B1 (fr) | 2001-10-24 |
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