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EP0517247A3 - - Google Patents

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Publication number
EP0517247A3
EP0517247A3 EP19920109550 EP92109550A EP0517247A3 EP 0517247 A3 EP0517247 A3 EP 0517247A3 EP 19920109550 EP19920109550 EP 19920109550 EP 92109550 A EP92109550 A EP 92109550A EP 0517247 A3 EP0517247 A3 EP 0517247A3
Authority
EP
European Patent Office
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19920109550
Other versions
EP0517247B1 (en
EP0517247A2 (en
Inventor
Naohiko Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0517247A2 publication Critical patent/EP0517247A2/en
Publication of EP0517247A3 publication Critical patent/EP0517247A3/xx
Application granted granted Critical
Publication of EP0517247B1 publication Critical patent/EP0517247B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
EP92109550A 1991-06-06 1992-06-05 Multilayer package Expired - Lifetime EP0517247B1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP13461391 1991-06-06
JP134613/91 1991-06-06
JP13461391 1991-06-06
JP13900692 1992-05-29
JP139006/92 1992-05-29
JP4139006A JPH05160292A (ja) 1991-06-06 1992-05-29 多層パッケージ

Publications (3)

Publication Number Publication Date
EP0517247A2 EP0517247A2 (en) 1992-12-09
EP0517247A3 true EP0517247A3 (zh) 1994-02-16
EP0517247B1 EP0517247B1 (en) 2001-08-22

Family

ID=26468670

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92109550A Expired - Lifetime EP0517247B1 (en) 1991-06-06 1992-06-05 Multilayer package

Country Status (4)

Country Link
US (1) US5309024A (zh)
EP (1) EP0517247B1 (zh)
JP (1) JPH05160292A (zh)
DE (1) DE69232012T2 (zh)

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US5338970A (en) * 1993-03-24 1994-08-16 Intergraph Corporation Multi-layered integrated circuit package with improved high frequency performance
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US6111306A (en) 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
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US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
JP3727062B2 (ja) * 1994-03-11 2005-12-14 ザ パンダ プロジェクト 高帯域幅コンピュータ用モジュール式構造
US5543586A (en) * 1994-03-11 1996-08-06 The Panda Project Apparatus having inner layers supporting surface-mount components
US6339191B1 (en) * 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
GB2288286A (en) * 1994-03-30 1995-10-11 Plessey Semiconductors Ltd Ball grid array arrangement
US5576931A (en) * 1994-05-03 1996-11-19 The Panda Project Computer with two fans and two air circulation areas
TW276356B (zh) * 1994-06-24 1996-05-21 Ibm
US5654204A (en) * 1994-07-20 1997-08-05 Anderson; James C. Die sorter
US5461260A (en) * 1994-08-01 1995-10-24 Motorola Inc. Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density
US6031723A (en) * 1994-08-18 2000-02-29 Allen-Bradley Company, Llc Insulated surface mount circuit board construction
US5483099A (en) * 1994-08-31 1996-01-09 Intel Corporation Standardized power and ground design for pin grid array packages
US5892273A (en) * 1994-10-03 1999-04-06 Kabushiki Kaisha Toshiba Semiconductor package integral with semiconductor chip
US5714801A (en) * 1995-03-31 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor package
JP3432963B2 (ja) * 1995-06-15 2003-08-04 沖電気工業株式会社 半導体集積回路
JP2716005B2 (ja) * 1995-07-04 1998-02-18 日本電気株式会社 ワイヤボンド型半導体装置
US5629241A (en) * 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5623160A (en) * 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
US5895977A (en) 1996-08-08 1999-04-20 Intel Corporation Bond pad functional layout on die to improve package manufacturability and assembly
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
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US7321485B2 (en) 1997-04-08 2008-01-22 X2Y Attenuators, Llc Arrangement for energy conditioning
US7336468B2 (en) 1997-04-08 2008-02-26 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
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US6100853A (en) 1997-09-10 2000-08-08 Hughes Electronics Corporation Receiver/transmitter system including a planar waveguide-to-stripline adapter
US6028354A (en) 1997-10-14 2000-02-22 Amkor Technology, Inc. Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package
US6133628A (en) * 1997-12-18 2000-10-17 Advanced Micro Devices, Inc. Metal layer interconnects with improved performance characteristics
US6169664B1 (en) * 1998-01-05 2001-01-02 Texas Instruments Incorporated Selective performance enhancements for interconnect conducting paths
JP3610221B2 (ja) * 1998-01-27 2005-01-12 キヤノン株式会社 多層プリント配線基板
US6078102A (en) * 1998-03-03 2000-06-20 Silicon Bandwidth, Inc. Semiconductor die package for mounting in horizontal and upright configurations
US6141869A (en) 1998-10-26 2000-11-07 Silicon Bandwidth, Inc. Apparatus for and method of manufacturing a semiconductor die carrier
US6664620B2 (en) 1999-06-29 2003-12-16 Intel Corporation Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
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EP1376698A1 (en) * 2002-06-25 2004-01-02 STMicroelectronics S.r.l. Electrically erasable and programable non-volatile memory cell
JP4206885B2 (ja) * 2003-09-26 2009-01-14 ソニー株式会社 半導体装置の製造方法
US7782587B2 (en) 2005-03-01 2010-08-24 X2Y Attenuators, Llc Internally overlapped conditioners
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Citations (5)

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EP0517247B1 (en) 2001-08-22
JPH05160292A (ja) 1993-06-25
US5309024A (en) 1994-05-03
DE69232012T2 (de) 2002-03-14
EP0517247A2 (en) 1992-12-09

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