EP0111178B1 - Control device with several detectors connected in chain form to a signal line - Google Patents

Description

The invention relates to a monitoring system with a plurality of detectors lying in a chain on a detection line, which are connected to a control center with an evaluation unit, in each of which a series switch is opened to a first value by a jump in the interrogation voltage generated by the control center, and the series switch is jumped switches the same interrogation voltage to a second value and after a time determined by the detector state to the next detector or to the next control unit, an electronic circuit part generating electrical signals with time intervals characterizing the detector state and giving them to the evaluation unit.

When monitoring buildings, tunnels, underground garages, rooms or other objects that should function optimally to successfully fight fire outbreaks, smoke and harmful gas developments or burglaries or theft, there is a need to keep the individual detectors and sensors constantly on their Check the condition, which is known to make a statement about the detector and sensor and its surroundings. The following states can exist: Quiet (operational readiness), (pre) warning, alarm, fault. The fault can occur in the detector, in the electronic circuit or on the detection line and is evaluated separately. The fault on the detection line can be a short circuit or an open circuit. A surveillance system is usually used for large buildings with many different rooms and objects. A large number of detectors or sensors are used for various monitoring tasks. Different types such as ionization detectors, optical smoke detectors, heat, radiation, gas and intrusion detectors (intrusion) can be combined in one monitoring system. These different types have a different response behavior and unfortunately had to be used in a previous system such as B. is described in DE-PS 2 533 382, can be integrated into the monitoring system by means of separate evaluation and increased effort.

European patent specification 0 042 501 describes a method for identifying detectors within a fire alarm system. If a fault occurs, the query direction for the affected zone is reversed.

EP-A-0 093 872 also describes a method for identifying detectors in a monitoring system. Each of the detectors has an address memory that is provided with the address that is characteristic of the detector.

The methods described in European Patent Specification 0 042 501 and in EP-A-0 093 872 have the disadvantage of great expense and the impossibility of converting existing monitoring systems. Furthermore, no short circuit can be detected and the system is no longer functional in the event of such a fault.

The object of the invention is to eliminate the disadvantages of the known systems. In particular, the purpose of the invention is to achieve that the detectors or sensors of different types can be operated in the same detection line. The following types are to be understood: ionization, optical smoke, heat, radiation, gas and intrusion detectors or sensors. Fire alarm buttons and control devices are also provided, which are connected to the same line as the detectors. The different types of detectors can be connected to a detection line or control center in the invention without any adjustment problems because each detector or sensor makes its own decision about its state (silence, warning, alarm, fault). Existing surveillance systems can therefore be modernized with little effort. If the electronic circuit is installed in the detector base, the circuits and the control center form a complete transmission system. This has the great advantage that a system can also be put into operation when only some of the detectors are used (commissioning, conversion, revision by sector).

The object is achieved in accordance with the features of the characterizing part of patent claim 1.

The electronic circuit according to the invention allows the transmission of all signals (information signals from the detectors to the control center and control signals in the opposite direction) on only one line pair. By drastically reducing the three or more lines (wires), such as. B. still common in the prior art, on two lines there is a strong reduction in the susceptibility to interference of the lines or the entire system in the invention.

Instead of only one, several detectors or sensors can also be connected to the electronic circuit according to the invention. This is an advantage if several detectors or sensors are housed in the same room. No matter which detector or sensor responds, only the room is detected. Each detector switches on the associated alarm indicator (e.g. LED) with its alarm status.

The electronic circuit according to the invention also serves to detect a short circuit in the direction of the next detector. The short-circuit point can be located precisely and the fault can therefore be remedied quickly and easily. Despite the short circuit, the full working voltage is maintained across the entire detector line. Only the part of the detector line on which the short circuit exists is switched off. This has the advantage that, despite a short circuit, the polling cycle of the individual detectors or sensors is still carried out and a change in their status is recognized immediately.

The electrical signals corresponding to the detector states are only in the control center predetermined time ranges evaluated. The intervening time periods are defined as "fault bands". Signals falling in these fault bands then cause a corresponding fault message in the control center. Furthermore, the invention allows those electrical signals which the control center emits to combat the alarm recognized and reported by one or more detectors to be sent on the same lines. In contrast, in the prior art, these signals are sent on additional, separate lines. The invention therefore saves a lot of wiring material.

• Fig. 1 eine bekannte Überwachungsanlage, in der die Erfindung eingesetzt ist;
• Fig. 2 ein Spannungs- und Stromdiagramm eines Abfragezyklus erster Art;
• Fig. 3 ein Spannungs- und Stromdiagramm eines Abfragezyklus zweiter Art;
• Fig. 4 eine Ausführung der Erfindung für die Diagramme der Fig. 2 und 3;
• Fig. 5 eine Ausführungsvariante der Fig. 4;
• Fig. 6 eine Schaltung zum Erzeugen einer Steuerfunktion;
• Fig. 7 die Erfindung mit mehreren, angeschlossenen Meldern;
• Fig. 8 die Anordnung der Erfindung in einem Verbindungsstück zwischen Meldersockel und Meldereinsatz;
• Fig. 9 die Anordnung der Erfindung im Meldereinsatz; und
• Fig. 10 die Auswertung der Melderzeiten mit «Störungsbändern».
• Fig. 11 die Anordnung zur Erzeugung der Linienspannung, zur Linienumschaltung und zur Stromauswertung.

Embodiments of the invention are explained in more detail with reference to the drawings. Show it:

• 1 shows a known monitoring system in which the invention is used;
• Fig. 2 is a voltage and current diagram of an interrogation cycle of the first kind;
• 3 is a voltage and current diagram of a query cycle of the second kind;
• 4 shows an embodiment of the invention for the diagrams of FIGS. 2 and 3;
• FIG. 5 shows an embodiment variant of FIG. 4;
• 6 shows a circuit for generating a control function;
• 7 shows the invention with a plurality of connected detectors;
• 8 shows the arrangement of the invention in a connecting piece between the detector base and detector insert;
• 9 shows the arrangement of the invention in the detector insert; and
• 10 the evaluation of the detector times with "fault bands".
• 11 shows the arrangement for generating the line voltage, for line switching and for current evaluation.

1 shows the control center 7 of a monitoring system. The individual detectors with detector bases F1, F2 to Fn and detector inserts ME1, ME2 to MEn are connected to the control center on detector lines 1, 4, 5. The detector inserts can be designed as ionization, heat, radiation, gas, intrusion inserts and optical smoke detector inserts. The lines of the chain-connected detectors are connected to terminals A1 and A2 of control center 7 and evaluation unit 71. In the example of FIG. 1, the electronic circuit of the invention is arranged in each of the detector bases F1, F2 to Fn. At least one detector insert is provided on each base. In order to make FIG. 1 clear, only switches S1, S2 to Sn and electronic circuits B1, B2 to Bn are drawn in the base of the invention.

After the interrogation of a detector by the control center 7, the switch of the same detector closes and connects the control center to the next detector, which is then queried. In this way, all detectors are queried individually and in sequence. The signals that represent the status of the detectors are evaluated in the evaluation unit 71. As soon as a detector reports an unusual condition [such as B. not ready, warning, alarm, fault of the detector, the electronic circuit or the detector line (short circuit, interruption)], this is indicated acoustically and optically or fixed in writing and the appropriate countermeasures initiated by the control center 7. Since this is generally known and does not form part of the subject matter of the invention, it is not dealt with in more detail here.

The electronic circuit B, which is drawn in FIGS. 4, 5, 6, can also be accommodated in each of the detector inserts ME of FIG. 1. This is e.g. shown in Fig. 9. It has also been considered to install the electronic circuit in a connector V between the detector insert and base F, as shown in FIG. 8. If old surveillance systems are to be modernized, this can be done without much effort, since the invention can be arranged either in the detector base, in the detector insert or in connector V.

The invention is explained below with reference to FIGS. 2 to 4. The upper part of FIG. 2 shows the two-stage interrogation voltage U. The time t is entered on the abscissa and the voltage U on lines 1, 4 is entered on the ordinate. The control voltage 8 within the query voltage 9 will be explained later in connection with FIG. 6. The dashed control pulse 8 is also used to reset a detector that is in the alarm state. This has the advantage that detectors are reset to their normal idle status after their alarm is triggered individually or differentiated according to the type of detector. This query voltage of FIG. 2 is generated by the control center 7 and given to the lines or detector line. One stage 11 of the voltage U is z. B. at 0 volts; the other level is 20 volts, for example. This voltage curve is given to the detector line at certain time intervals. In an interval of e.g. B. 1 to 2 seconds. All detectors are queried. Each detector transmits its status to the control center 7 one after the other. This is shown in the lower part of FIG. 2. There the time t is drawn on the abscissa and the current I of the detector line is drawn on the ordinate. It can be seen that the interrogation voltage 9 causes the switch S1 in the base F1 of the detector to be closed after a certain time t ₁ , and the electronic circuit B1 generates a current pulse 10 of a certain amplitude and duration. The time t ₁ is now a sign for the evaluation unit 71 that the detectors F1 and ME1 are in the normal idle state of the operational readiness.

The same condition can be found in the next detector F2 and ME2. The time t ₂ is equal to t ₁ . It is now assumed that the third detector is in the alarm state. As soon as the switch S2 has switched through, the current amplitude jumps to a high value (caused by the additional current of the alarm indicator L,). Furthermore, the time t ₃ (the time from connecting the third detector to switching the third Switch to the fourth detector) is significantly longer than the other "normal" times t ₁ and t ₂ . The evaluation unit 71 recognizes these two criteria (current amplitudes and times) of the alarm state of the third detector. The control center 7 then initiates the corresponding measures. The fourth detector is supposed to be in the normal idle state of operational readiness again. This is shown by the fact that the time t ₄ (from connecting the fourth detector to turning on the fourth switch) is in the normal range. The detector states can also be transmitted to the evaluation unit 71 only by one criterion (current amplitude or times) or with different current amplitudes, but with identical times.

A fault state of the third detector is assumed in the lower part of FIG. 2 as a further example. While the two detectors, consisting of the bases F1 and insert ME1 and base F2 and insert ME2, are in the idle state, the time t ' _{3 is} much longer. The evaluation unit 71 evaluates this as a fault in the third detector. The head office starts the corresponding measures. The following detectors are once again in the normal idle state of operational readiness. For better distinction, this second example is shown in dashed lines. If a detector is in the fault state, the alarm indicator is not activated, and the dashed current curve in FIG. 2 therefore shows no jump in the current amplitude when S2 is switched through. The transmission of an alarm status to the control center is extremely reliable thanks to the high current amplitude. The identification of the alarmed detector is also very useful and could be achieved by giving each detector its own number (address), so that the exact location of an event is immediately known. The address and the status of the detector could therefore be transmitted to the control center using digital methods, for example. However, such a system is very complex and prone to failure. It is also difficult to install because each detector has to be assigned a special number. The system may stop working if there is a single error. In the monitoring system described here, on the other hand, the addressing of the individual detectors and the associated problems are eliminated. Rather, the numbering (identification) of the detectors is done by counting the current pulses (10) by the control center in each cycle.

To complete the explanation of FIG. 2, it is pointed out that the time intervals between the individual current pulses 10 can be arranged in such a way that the shortest time corresponds to the normal idle state (operational readiness), an average time for alarm, and the longest time for Disturbance is provided. The time for the warning can either be the same as the time of the fault or it can be different. It is also easily possible for the shortest time to correspond to the alarm state, an average time for the normal idle state (operational readiness) and the longest time for the fault to be provided. In this case too, the time for the warning is either the same as that for the fault or different. All of these possible combinations can be provided on a case-by-case basis.

Circuit B of the invention is drawn in FIG. 4. The interrogation voltage U of the control center 7 is at the terminals of lines 1 and 4. The detector insert ME is connected to the circuit in the middle of FIG. 4. A state of the detector insert corresponds to a specific voltage or current value at its terminals 1a, 4a. When the detector insert ME is connected to the circuit, the switch W is closed. The switch is open when the detector is removed.

To explain how this circuit works, it is assumed that the normal operating state has leveled off. During the currentless time 11 of the interrogation cycle, capacitor C1 feeds the entire circuit including the detector insert. The collector-base path of T11 is polarized forward and a current across R7 creates a stable voltage on Zener diode D7. Transistor T3 acts with R8 as a constant current source, the current of which is mirrored via R9, R12 and T5. A limited current is thus available at terminal 4a for supplying the detector insert ME. The transistors T1, T2, T4, T6, T7, T8, T9, T10, T15, T17, T18 are not conductive and C6 is discharged. R22 blocks switches T9, T10 during this time.

If the line voltage at terminal 4 now rises to query value 9, point «z» is raised to the same value via the integral diode in T10. First, the voltage at C6 will rise to Zener voltage D7 via R15, T17, T18. The resistance divider R13-R17 is dimensioned so that C2 charges up to D3 and T8, and this happens differently, quickly, depending on the voltage at the detector insert ME or at terminal 4a. For a large voltage at 4a, corresponding to the detector idle state, the charging time is T _R , but if there is no detector, for example, no current flows via R13 (switch W open) and the charging time for C2 is relatively long, corresponding to T _s . For an average voltage value at 4a, corresponding to a detector in the alarm state, there is an average charging time T _A , where T _R <T _A <T _s . When T8 switches on, T7 also conducts and the current pulse 10, determined by C3, R20, is registered by the evaluation unit 71 of the control center. R21 keeps T7, T8 in the conductive state and also serves to discharge C3 when the line voltage later goes back to zero. The gates of T9, T10 are controlled by T8 so that these two FETs switch to the next detector (terminal 5) as soon as the multivibrator T7, T8 conducts. It is clear that the cathodes of T9, T10 are interchanged, depending on whether terminal 4 or 5 as input or. Output serves. The capacitance C6 maintains the voltage across R14-R17 during the brief control pulse voltage dips.

The network D1, D2, T6, R18, R19 checks the following line section (terminals 1 and 5) for short circuit. T6 acts as an emitter follower, which charges the section in question, for example, to the voltage at the base voltage divider R18, R19. If there is a short circuit, T6 remains conductive and keeps the voltage between R16, R17 so low that C2 cannot be charged to the switch-on voltage of T8. In the event of a short circuit, there is therefore no current pulse 10. In the event of a short circuit, the two FETs T9 and T10 remain open and disconnect the line to the next detector and thus the short circuit from the control center 7. In this case, the evaluation unit 71 receives no current pulse for a long time. The control center now switches the next polling cycle to lines 1 and 5. The query direction of the detectors is reversed. It is essential that, despite a short circuit, the detectors are queried undisturbed.

When the line voltage jumps from zero value 11 to query value 9, C4 on the right side is raised negatively by D6 by the same jump, so that the base of T11 becomes so negative that T11 blocks. C4 now discharges via the circuit R7, D7, R23 and via R10, T15. As long as T11 is blocked, C1 cannot reload (delay time Tv). During this time, however, T15 conducts and the collector current from T15 flows via D5 via D7 if ME is at rest (high voltage at 4a) and otherwise via T4, D4, ME and T4, R6, R5. If the voltage at ME is medium (alarm status), T2 will switch on via R6, R5 and T1 conducts, ie the alarm indicator L1 flashes and shows the alarm status visually directly at the detector. A remote display can also be connected between terminals 1 and 6. The required voltage is generated across the Zener diode D8. This external display lights up in sync with L1. If ME is in the fault state, the voltage at R5, R6 is not sufficient to activate T1, ie L1 does not light up in the event of a fault. The dashed relay Y indicates that external loads can also be switched by the L1 pulse. The current for L1 comes partly from the line via D9, R2 and partly from the memory C1 via D10, R1. The portion over R2 is the large current increase after t ₂ (FIG. 2) and is reliably detected by the center 71 as an alarm criterion. The voltage divider R3, R4 blocks the current draw from the memory C1 as soon as its voltage drops too far. Since C1 is the supply voltage source, it must not discharge too far. It is clear that T1 no longer conducts as soon as C4 is discharged to such an extent that T15 blocks. At this time T11 goes on line and C1 is reloaded via D9, R2, R1, T11. The polling cycle is complete when the line voltage drops back to zero 11.

FIG. 3 shows a query cycle of the second type, which is also carried out with the circuit of FIG. 4. In the upper part of FIG. 3, the time t is entered on the abscissa and the interrogation voltage U of lines 1, 4 and 5 on the ordinate. The upper part of FIG. 3 shows the interrogation voltage 9, to which an increased voltage 13 is connected. The increased voltage 13 is intended to support the capacitor C1 of FIG. 4. If a large number of detectors are connected to a detector line and are queried, the capacitors C1 of the last detectors MEn, MEn-1 discharge relatively strongly. With the help of voltage 13, all capacitors C1 can be recharged sufficiently. In this case, the circuit (Fig. 4) must be dimensioned or. the interrogation voltage 9 can be selected such that the times t are formed and the FET switches switch on, but the recharging of the storage capacitors is only activated by the increased voltage 13. In addition, the LED L _{1 of} a detector which is in the alarm state will only light up after the interrogation voltage 9. This avoids malfunctions and incorrect information which may arise due to the current increase caused by the lighting up of the light emitting diode during the interrogation cycle. In fact, all LEDs now light up at a point in time where otherwise only small currents flow. This results in a very high level of security for the entire monitoring system. The control signal 8 will be explained later in connection with FIG. 6. The dashed control pulse 8 is also used to reset a detector that is in the alarm state. This has the advantage that detectors are reset to their normal idle status after their alarm is triggered individually or differentiated according to the type of detector.

In the lower part of Fig. 3, the current pulses 10 of the individual detectors and the current caused by the increased voltage are drawn. The time t is shown on the abscissa and the current I of the detector line is shown on the ordinate. The query cycle shows that the first two detectors are again in the idle state since the times t ₁ and t _{2 of} their current pulses 10 are in the normal range. The third detector is in the alarm state because the time t _{3 of} its current pulse is longer than the other two times. After the interrogation cycle, the LED L _{1 of} this detector lights up. This is represented by an increased current amplitude 12. The capacitor C ₁ (Fig. 4) also charges sufficiently and can take over the power supply of this detector. The charging of the capacitor is delayed by the time Tv, so that the current profile caused by the light-emitting diode L ₁ can be reliably detected as an alarm criterion by the evaluation unit 71. This is shown in the lower part of FIG. 3. After a certain time, the next polling cycle comes.

FIG. 5 shows a further embodiment of the switch S. This example is used in the lower right part of the circuit B of FIG. 4 at the positions X, Z, 4 and 5. The JFET circuit of FIG. 5 replaces the two FET's T9 and T10 of FIG. 4. The capacitor C5 stores the gate bias for safe blocking of the JFET's T12 during the dead time 11 and the resistors R24, R25, R39 represent the correct DC voltage level at the gate of the JFET. The diodes D11, D13 perform the same function as the integral diodes of the switching FETs T9 and T10 in FIG. 4.

Fig. 6 shows a further embodiment of the invention which can also be used so that control units can optionally be installed in the same detection line (lines 1, 4, 5 of Fig. 1) as the detectors, the control functions for taking countermeasures in the event of an alarm or execute fault. It should be emphasized that only as many control units are exchanged for detectors as the organization of the monitoring system requires. Due to the free interchangeability between detector and control unit, existing monitoring systems can easily be reorganized for changed monitoring conditions. Via lines 1, 4 and 5, therefore, not only are the signal signals from the detectors to the control center 7, but also the control signals 8 (FIGS. 2 and 3) from the control center 7 to the control units of FIG. 6.

A preferred embodiment of the circuit for receiving the control pulses 8 (FIGS. 2 and 3) is shown in FIG. 6. This receiver circuit is connected at points “+1” and “z” to the circuit according to FIG. 4. The output of the receiver circuit is preferably connected to terminal 4a in FIG. 4. When a control pulse 8 has been received, the output transistor of the receiver conducts and then causes a long time interval T _{s of} the driven base. The control center thus receives an acknowledgment that the control pulse was received correctly. The circuit of FIG. 6 in the example described is obviously used for the targeted resetting of alarmed detector inserts ME. Of course, the receiving circuit can also be used to trigger a wide variety of functions, in particular also to control relays in order to combat dangerous situations. In the prior art, separate lines are used for control functions. The monitoring system described here saves a lot of installation material.

In order to understand the mode of operation of the receiving circuit (FIG. 6) it is assumed that the storage capacitor C14 is charged to its normal operating voltage via D12 and R59, R60. The instantaneous voltage at «z» is zero, corresponding to level 11 in the polling cycle (Fig. 2, 3). The transistor T33 conducts via R56, R58 because of the basic control, while T34 is blocked via R61. This means that T35 and T36 are also non-conductive. The capacitor C11 has discharged via R51, R52 to such an extent that T31 blocks. As long as there is zero voltage at «z», T32 also blocks. C12 is discharged via R55 and at C13 there is a voltage determined by voltage divider R56, R58.

As soon as the interrogation voltage (9) is connected to this detector, C11 charges via R51 and T31 becomes conductive after a certain delay. T32 remains blocked during this delay time. The voltage at C12 rises rapidly, with C13 also rapidly charging to a high proportion of this voltage. If a control pulse 8 occurs at “z”, T32 acts as an emitter follower and the voltage at C12 drops rapidly to the voltage of the control pulse, while the voltage at C13 can only change slowly due to the high resistances R56, R58. As a result, the voltage at node R56, R58, C13 becomes positive enough that T33 blocks. As soon as T33 locks, the flip-flop T34, T35 via T34 is made conductive from R60, R61. As a result, the output transistor T36 also turns on. The timing elements R62, C16 essentially serve to maintain the supply voltage across the flip-flop even during the duration of the control pulse, where the voltage at point "z _" can drop to zero. The elements R63-R66, C15 increase the interference immunity. It is clear that the control pulse can only switch on the flip-flop as long as T31 is blocking, ie the control pulse must be present during the delay time formed by C11, R51, R52. At all other times the control pulse remains ineffective. This is extremely important for individual detectors can be controlled selectively from the control center.

For the sake of completeness it should be mentioned that by slight modification of the circuit (Fig. 6), e.g. several rapidly consecutive control pulses can be received and counted, e.g. B. to trigger various functions, depending on the number of control pulses. Likewise, other features of the control pulses (e.g. width, height, frequency) commonly used in telecontrol technology can also be used to trigger control functions in a differentiated manner.

FIG. 7 shows the arrangement that a plurality of detector inserts ME1, ME2 to MEn are connected in parallel to the terminals 1a and 4a (FIG. 4) of a detector base F1 or F2 to Fn, which in turn is chain-like at the control center 7 with its evaluation unit 71 . The electronic circuit B of FIG. 4 is arranged in the detector base F with or without a combination of FIG. 5, which is indicated by the switches S1, S2, Sn. The mode of operation is the same as in the arrangement of FIG. 1. Of course, the states of the detector inserts ME connected in parallel to the terminals 1a and 4a are no longer individually known. Because the detector inserts in the quiescent, warning, alarm and fault states switch very different impedances via their terminals 1a and 4a, the base F practically detects the detector state with the lowest impedance. This state is then transmitted to the control center via the circuit B in the base F. Fig. 7 is to illustrate the diversity in the arrangement of the detectors.

FIG. 8 shows the arrangement of the electronic circuit B from FIG. 4 in a connecting piece V between the detector insert ME and the detector base F. This is particularly necessary for those monitoring systems which are to be modernized while maintaining the old base and line routing.

FIG. 9 shows the arrangement of the electronic circuit B from FIG. 4 in the detector insert ME, which is arranged on the detector base F. These detectors can easily be used in existing surveillance systems.

FIG. 10 shows how the area used in the evaluation unit 71 for the detector times is divided into “good” and “bad” areas. At t = 0 in Fig. 10, a circuit B is applied to voltage. After a certain measuring time T _M resp. The current pulse 10 is generated T _n '. If the recorded measuring time T _M resp. T _n '(corresponding to t ₁ , t ₂ , t ₃ , t ₄ , t' ₃ of FIGS. 2 and 3) in a good area (TR, TA, TS), depending on the readiness for operation, warning, Alarm or fault of the detector decided. If a measuring time falls outside of tolerance, ie in one of the forbidden bad areas (TF1, TF2, TF3, TF4), then a fault in the electronic circuit B (e.g. components outside of tolerance) or a disturbing influence on the Detector lines 1, 4, 5 (e.g. electromagnetic interference) must be closed. The evaluation unit 71 contains a microprocessor, not shown, which compares the times t ₁ , t ₂ , t ₃ , t ' ₃ , t _{4 of} the states of the detectors and connections with the program-stored “good” and “bad” time ranges. Not only the detectors of FIGS. 1, 7, 8, 9 and the control unit of FIG. 6, but also the electronic circuit B of FIGS. 4 and 5 and all lines between the detectors, control units and the control center 7 are continuously monitored. This significantly improves transmission security.

11 shows a simple embodiment of the control center 7 with the evaluation unit 71. The microprocessor takes over all the necessary control and monitoring functions. The figure is divided into a circuit for the voltage controller 73 and the current evaluation 72 as well as a line switching device 74. The line voltage is carried out via the programming input of the voltage regulator IC (for example LM 304). If transistor T41 is controlled via processor output I, U _line = 0. If neither T41 nor T40 is activated or in the conductive state, voltage 13 (FIG. 3) is set by R70. When transistor T40 is driven by H, R70 and R71 are connected in parallel. The interrogation voltage 9 (FIG. 3) is generated.

The current measurement takes place in a known manner, via an operational amplifier OP1 which is connected as a comparator by means of R72 to R76 and whose output Up is connected to an input of the microprocessor. This processor can now measure the times t ₁ , t ₂ etc. and assign them to one of the “time windows” shown in FIG. 10 (T _R , T _A , T _S , T _F1 to T _F4 ) and thus determine in which state every single switch or detector is located.

In the upper right part of FIG. 11, a switchover device is also shown, which is used to query the detection line either from the front A1 or from the rear A2 with the aid of a relay. This is very useful when there is a short or an open on the line.

Claims (20)

1. Monitoring system comprising a number of detecting and signalling stations series-connected in a signal line being connected to a central signal station (7) including a signal processing unit (71), each said detecting and signalling station including a series-connected switching element (S) adapted to be opened by a sudden change in the interrogation voltage produced by said signal processing unit to a first value (11) and to be closed by a sudden change in said interrogation voltage to a second value (9) and to making a through-connection to the next detecting and signalling station or to the next control unit after a predetermined period of time (t) which is determined by the state of said detecting and signalling station, each said detecting and signalling station being provided with an electronic circuit member (B) generating electrical signals (10), at distinct time intervals (t1, t2, t3, t4) being characteristic of each one of said stages of said detecting and signalling station, and sending said electric signals to said signal processing unit (71), characterized in that for the surveillance of said electronic circuit member (B) said electric signals (10) are compared in said signal processing unit (71) with a time pattern comprising periods of time (TR, TA, TS) for determined states of the detecting and signalling stations and time intervals (TF1, TF2, TF3, TF4) between said periods of time.

2. Monitoring system according to claim 1, characterized in that said periods of time (TR, TA, TS) are provided for the states of the detecting and signalling stations corresponding to an inactive state, to an alarm state or to a malfunction state of said detecting and signalling station and that the time intervals (TF1/TF4) being arranged between said periods of time are provided for malfunction states of the transmitting electronic circuits between the detecting and signalling station and the central station (7).

3. Monitoring system according to claim 1, characterized in that said electronic circuit member (B) transmits to said signal processing unit (71) a further state (e.g. a warning state) with the same time interval (t'3) as the state "malfunction" (TS).

4. Monitoring system according to claim 1, characterized in that said electronic circuit member (B) transmits to said signal processing unit (71) a further state (e.g. a warning state) with a time interval being different from the time interval of the other states.

5. Monitoring system according to claim 1, characterized in that said electronic circuit member (B) transmits to said signal processing unit (71) the states of said detecting and signalling stations in the form of amplitudes of said electrical signals (10) and of said time intervals (t1, t2, t3, t4).

6. Monitoring system according to claim 1, characterized in that only a single time is possible and that said electronic circuit member (B) transmits said states of said detecting and signalling stations to said signal processing unit (71) in the form of amplitudes of said electrical signals (10).

7. Monitoring system according to anyone of the claims 5 and 6, characterized in that said electronic circuit member (B) transmits said states of said detecting and signalling stations in the form of the pulse width of said electrical signals (10).

8. Monitoring system according to claim 1, characterized in that the detecting and signalling station responding to the interrogation voltage (9) switches on its alarm indicator (L1) only in case of a predetermined change in voltage on said signal line (1, 4, 5).

9. Monitoring system according to anyone of the claims 1 to 8, characterized in that the increase in current flow (12) caused by said alarm indicator (L1) is transmitted for evaluation to said central signal station (7) only within a distinct time period during which said interrogation voltage assumes a further value (13).

10. Monitoring system according to anyone of the claims 1 to 9, characterized in that the electronic circuit member (B) comprises a circuit component (T11, C4, R23) which separates during said alarm stage of said detector insert (ME1, ME2, MEn) said illuminated period of said optical indicator (L1) and the period during which said increased current flow is conducted at said signal line (1,4,5) by a predetermined period of time (Tv) from said predetermined moment of time at which said capacitor (C1) is charged.

11. Monitoring system according to claim 10, characterized in that said capacitor (C1) is charged at a delay by said predetermined period of time (Tv) provided that said alarm indicator (L1) is in a non-luminescent state.

12. Monitoring system according to anyone of the claims 1 to 11, characterized in that said electronic circuit member (B) comprises a detector circuit component (R18, R19, D1, D2, T6) for detecting a short-circuit in the line leading to the next electronic circuit member and blocking the through-connection of said series-connected switching element (S).

13. Monitoring system according to anyone of the claims 1 to 12, characterized in that one electronic circuit member (B) is provided for a number of said detector inserts.

14. Monitoring system according to claim 1, characterized in that said series-connected switching element (S) in said electronic circuit member (B) is formed by one or by two field effect transistors.

15. Monitoring system according to claim 1, characterized in that said central signal station (7) during said active phase (t1, t2, t3) of said electronic circuit member (B) and prior to said making a through-connection of said series-connected switching element (S) generates a control pulse (8) which is detected by the electronic circuit member as an order for triggering a relay (Z) which relay triggers countermeasures in the case of an alarm or malfunction.

16. Monitoring system according to claim 1, characterized in that said central signal station (7) during said active phase (t1, t2, t3) of said electronic circuit member (B) and prior to said making a through-connection of said series-connected switching element (S) generates a control pulse (8) which sets said detecting and signalling station into one of said distinct states.

17. Monitoring system according to claim 1, characterized in that said central signal station (7) during said active phase (t1, t2, t3) of said electronic circuit member (B) and prior to said making a through-connection of said series-connected switching element (S) generates a control pulse (8) which resets said detecting and signalling station from said alarm stage.

18. Monitoring system according to anyone of the claims 15 to 17, characterized in that means are provided to generate a preprogrammed sequence of control pulses which trigger distinct control functions during interrogation of said detecting and signalling stations ME1 to MEn.

19. Monitoring system according to anyone of the claims 1 to 17, characterized in that said electronic circuit member (B) is incorporated in a socket member (F), in said detecting and signalling station (ME) or in a connecting member (V).

20. Monitoring system according to claim 1, characterized in that a switching circuit component (T1, D8, L1) is provided between the two supply lines (1, 4) of said signal line for energizing a luminescent diode (L1) and/or a relay (Y) in case that an alarm or malfunction is signalled to said central signal station.

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