EP1206765B1 - Method and device for automatically allocating detector addresses in an alarm system - Google Patents

Abstract

A process for automatically assigning detector addresses in a danger detection system, comprising a master station and at least one two-wire detection line linked thereto to which a multiplicity of detectors are connected wherein each detector has a capacitor for power accumulation, a measuring resistor in one wire, an evaluation device evaluating the voltage drop on the measuring resistor to which an address latch is connected, and a switch controllable by the evaluation device between the wires.

Description

The invention relates to a method for automatic assignment of Detector addresses in the event of a large number of detectors having alarm system according to claim 1.

Security alarm systems, e.g. Fire alarm systems usually have a larger one Number of hazard detectors connected to a two-wire signaling line are. This can be designed as a stub or as a loop, via which the individual detectors communicate with a central office. Every detector has a sensor or the like which depends on parameters of its Environment measured values produced. The measured values are sent via the line the control center, this usually the individual detectors cyclically queries. To assign the measured values to the individual detectors It is necessary to assign an identifier or an address to each detector. The address is stored in a non-volatile memory.

It is therefore known when commissioning such a hazard alarm system first assign the individual detectors an address. This is preferably done an automatic procedure applied.

The prior art has a number of methods for addressing and operation have become known by hazard warning systems, which are briefly discussed below becomes.

From DE 25 33 330 it is known when query the detectors a line to one for each Detector characteristic lead time the delivery of a current pulse with a to cause its measured value proportional pulse duration. In the central Evaluation device, the lead time is measured and as an address of the individual Detector determined. From DE 25 33 382 a method is known in which the detectors a line at the beginning of each polling cycle of the reporting line electrically are disconnected and then switched chain-shaped in a predetermined order become. Each detector switches after a corresponding time delay following detector. An evaluation device in the center determines the respective increases in the line current, the detector address of the number of Increases in the line current corresponds. Since it is not possible or useful, Measured values of different detector types according to a uniform procedure too process is also known from DE 25 33 354, the individual detectors Assign timers, as in the above-described prior art the case is. The timers are used to transmit control commands on the Line to the individual detectors used, with the detectors only during runtime the individual timers are ready to receive. With provided in the detector Control devices are only within one control cycle on the reporting line a timer can be switched on, wherein the starting time of the individual timers in the Central is evaluated as an address. In this connection, EP 0 098 552 also known in a cyclic query a hazard detection system in each detector an influenceable by the measured value via a transducer Switch timer to the reporting line and in the control center from the number of thereby causing increases in the line current to derive the detector address. Each detector is equipped with an output signal generated in a transducer, this is the sum of the detector measured value and a detector identification signal represents the duration of the timer controlled and in the control center next to the detector address from the respective switching delay both the detector measured value as also derives the detector identifier of the relevant detector.

Thus a larger number of fire detectors connected to individual reporting lines or to send a higher current through a reporting line to be known from EP 0 042 501, the message line annular close. In the absence of signals on a message line, the query direction vice versa. The measured value is transmitted either by a corresponding time delay until the connection of the following detector or in the form of a coded pulse train, which is forwarded to the central office.

From EP 0 212 106 it has also become known to the detectors in a chain-like Line address memory allocate, which in a predetermined order of the central office with the addresses are occupied. This happens in the way that a transfer to the next detector only takes place if an address in the previous Detector is locked. For this purpose is in each detector a Switch arranged, which has a wire for switching to the next detector short-circuits.

From DE 32 25 032 has become known, the desired distinction of Detector type, identifier and measured value to bring about that of the Central control commands transmitted to the detectors targeted at individual detectors Switching devices are controlled by the detector measured value transmission switch over to the detector identification transmission. About a polling cycle Then the respective detector identifier is transmitted to the central office, where they are stored and further processed. In this case, a device is provided in each detector, with which the detector identifier, e.g. Detector type or detector status.

All the reported detectors have in common that they are one in line with a vein lying switch, which must be closed so that the in line next following detector is connected to the control center. In contrast, too Solutions are known, the other switching means for a chain-switching of provide for individual detectors.

In DE 32 11 550 a two-wire signal line is provided in which each detector a series resistor and a switch between the wires the reporting line is closed and is closed in case of alarm. The response of the Detector causes a change in the total resistance of the reporting line. One in the Central arranged measuring and evaluation device assigns each detector a window discriminator. Triggering the detector causes with the for him characteristic resistance value a corresponding measurement voltage. Of the this measuring voltage associated window discriminator then switches its output to the display device associated with the alarmed detector.

From DE 40 38 992 is a method for automatic assignment of detector addresses become known in a security alarm system, in which a central office connected to a two-wire reporting line to the chain-like individual detectors are connected. Each detector has a transmission device, a Data memory, an address memory and a voltage measuring device as well as a switch. In a first phase of the center is a rest voltage connected to the line, whereby the detectors are powered by Charging a capacitor. In a second phase, a short-circuit voltage placed on the line, eliminating all detectors whose address memory is empty is short circuit the line by means of its switch. In a third phase will the line impressed a measuring current and thereby the first detector with closed Switch dropping voltage is from the voltage measuring device determined. Its value is stored in the measured value memory. In a fourth Phase, a query voltage is applied to the line, whereby the detector whose Memory is occupied, but the address memory is empty, capable of communication and gets assigned an address from the central office, which in the Address memory is stored. This process is repeated by the control center until all detectors are provided with addresses. The end of the process can be recognized by the central office that in the third phase, no short-circuit current more flows.

The last-mentioned known solution requires, on the one hand, a not insignificant one Circuit complexity in the detectors. Furthermore, it requires a longer Period for addressing. The phases 2 to 4 described above must be for every detector of a line will be repeated, which will take a longer time especially with a larger number of detectors in a network.

The prior art also includes further addressing or detection methods. Such is described for example in EP 0 546 401, which consists in that an identification module is present in a detector base of each detector is, for each individual detector base an unchangeable identification number is provided, which differs from that of the other detector base is. Means are provided in the detector which recognize the identification number. The identification module mounted in the detector base either turns off a resistor combination, a ROM, a PROM, an EPROM, a EEPROM or an optical bar mark formed. The reading of the identification number via contacts or an optical transmission device. The localization of the detector base is done either by inserting the Detector in the specified order during initial startup by initial detector alarm e.g. with test gas in the given order or by Assign the address using a programmer before inserting. In EP 0 362 985 attempts to solve the problematic addressing method described above thereby improving that in the notification socket one manually to a binary code adjustable mechanical device on corresponding resilient elements of the inserted measuring head for transmitting the detector address presses. Although the switch is facilitated for maintenance purposes. A time consuming manual setting of the coding for the socket address is also included this solution required. Furthermore, the unstable spring elements and contact points a security risk.

Finally, EP 0 485 878 discloses a method for determining the configuration the detector of a security alarm system has become known, in which in each detector A binary serial number is stored by the manufacturer. At the installation 12 are sometimes very time-consuming and complex process steps to determine the number of detectors in the plant their position or networking carried out on the determination of their serial numbers. The more complex the Networking of ring and stub lines is, the tighter the known Method.

The invention is based on the object, a method for automatic assignment of detector addresses in a hazard alarm system indicate that a low circuit complexity required in the individual detectors, within short time is feasible and even with long transmission lines works with a large number of detectors error-free.

This object is solved by the features of patent claim 1.

In the method according to the invention is in a first phase as in the genus in accordance with the state of the art in the center a voltage to the line through which the capacitors are charged. This is an energy supply the detector is secured at short notice. In a second phase sends the control panel a switching signal to close the switch of all detectors. According to one Embodiment of the method according to the invention, this switching signal from a voltage-modulated data word of the center formed. In a third phase are immediately after closing the switch in a predetermined Alternating constant currents with different level of the line impressed. The constant current with changing level generates at the measuring resistor of all detectors, whose switch is open, and thus at the detector to be addressed changing Brownouts. which of a pulse receiver in the detector, in a data word forming digital signal. This digital signal is given as an address directly in the memory, if not already is occupied by an address. Once this process is completed, the opens Logic circuit the switch and locks the storage of another data word in the address memory.

During the described addressing process, the following detectors receive no evaluable voltage pulses through their resistors and thus none Communication address, as the switch of the addressed detector the transmission line short circuits to the following detectors. After the addressed If the detector has saved his address, as mentioned, his switch is opened.

The control panel can continue to flow one of the impressed currents. The central office registers the opening of the switch by a voltage jump to the Terminals. This can be used as an acknowledgment signal for making the first one Detector has properly received its communication address. immediate Subsequently, the control panel sends another communication address, which also by an impressed current-modulated serial signal from the two constant currents is formed. Since the switch of the first detector is open, receives also the second detector via its measuring resistor evaluable voltage pulses. All other detectors receive no usable voltage pulses via their Measuring resistors. After storing his address, the second detector opens his switch. For each additional detector, the control panel repeats the last one described Step with a different data word. This is by a Rapid transmission of the communication addresses of a large number of detectors Allocated communication address. Is the assignment of the communication addresses completed, the control panel no longer receives a voltage jump. This can the control center will consider the automatic process completed.

A circuit arrangement for achieving the object of the invention provides for each detector connected to the two-wire signaling line in line with a diode switched capacitor, a controllable switch between the Cores, a measuring resistor in the course of a wire, a pulse receiver, a Logic circuit and an address memory connected to the logic circuit in front. As already explained, the impressed constant currents at the Measuring resistor generates voltage pulses, which evaluates the pulse receiver. The Logic circuit provides for feeding into the address memory. For the pulse receiver can be a simple standard amplifier with a fixed gain and a downstream transistor stage may be provided. In one embodiment the invention is alternatively provided to use the microprocessor for this purpose, which is usually arranged in each detector for the implementation measurements and communication with the control center. For the pulse receiver the A / D converter of the microprocessor are provided and a corresponding Program of the microprocessor. An additional circuit complexity is therefore not required for the pulse receiver. The impressing of constant currents in the signaling line ensures that the detector has the same size at each measuring resistor Voltage drops are generated, regardless of the number the detector, the length of the reporting line and other line parameters.

Would a mechanical switch, such as a relay, for each detector provided, due to its almost ideal resistance conditions also clear voltage relationships between the respective address reception pending resistance, which is identical for all detectors, and those the short-circuited downstream detector. From cost but also technical For reasons, preferably semiconductor switches, e.g. FET switches. used. These have switched on, i. conductive state a volume resistance, which can be less than 50 milliohms. As a result, corresponding small form Voltage drops across the terminals of each electrical switch. These residual stresses are still on the following measuring resistor shorted detector measurable. Thus, not all the electricity flowing from the headquarters of the line is impressed, by the short-circuited Detector. It is therefore provided according to an embodiment of the invention that the Ratio of the resistance value from the measuring resistor to the resistance of the through-connected semiconductor switch is greater than 10: 1. That way, one becomes unambiguous identification of the pending from the control center for addressing Melders reached. For the required cable lengths, cable cross-sections and e.g. a number of detectors in a loop of 128 pieces is included usual supply voltages of e.g. 24 volts addressing all Detector according to the inventive method in a short time automatically performed. In normal installation conditions, the voltage signal is through the impressed constant currents via the measuring resistor of the addressed Detector is generated, many times higher than the voltage drop at the following still with a semiconductor switch shorted detector.

In summary, it can be stated that the method according to the invention with a low circuit complexity even with extensive alarm systems within a short time allows automatic assignment of addresses. Because of the low time utilization of each detector for the addressing process The capacitor can be designed relatively small, which is the expense further reduced.

Fig. 1

zeigt schematisch eine Schaltungsanordnung zur Durchführung des Verfahrens nach der Erfindung.

Fig. 2

zeigt eine andere Ausführungsform für eine Adressierschaltung eines Melders der Gefahrenmeldeanlage nach Fig. 1.

The invention will be explained below with reference to a Ausrührungsbeispiels shown in the drawings.

Fig. 1

schematically shows a circuit arrangement for carrying out the method according to the invention.

Fig. 2

shows another embodiment for an addressing circuit of a detector of the hazard detection system of FIG. 1.

In Fig. 1 is a center Z of a hazard detection system, such as a Fire alarm system, shown, with a transmission line is connected to the wires A and B. The transmission line can be a branch or a ring line be, as it is known. The control panel has a power supply in the form of a power supply NT, a microprocessor μC, a constant current source K, a modulator M and a voltage measuring device VM. On the Function of the individual components will be discussed below.

To the transmission line a plurality of detectors is connected, for example 128. However, only two detectors M1 and M2 are shown in FIG. Each of the detectors M1 and M2 has a resistance Rm1 or Rm2 in the course a wire, a capacitor C1 or C2 in series with a diode D1 or D2 between the wires, a controllable switch SK1 or SK2, a Pulse receiver PE, a logic circuit L and an address memory SP. Everyone Detector contains a number of other components necessary for its operation are. However, as described here only the assignment of an address to each detector are, these blocks are not shown and are not described.

The assignment of addresses to the individual detectors M1 to Mn described with reference to FIG. 1.

In a first phase, the center Z switches a supply voltage to the Transmission line. Via the identically dimensioned measuring resistors Rm1, Rm2 ... Rinn gets the supply voltage to all detectors M1, M2 ... Mn. Your Capacitors C1, C2 ... Cn are charged via the diodes D1, D2 ... Dn. The charged ones Capacitors supply the logic circuits L, the address memories SP and the pulse receiver PE with electrical energy during the addressing phase. The switches SK1, SK2 ... SKn are open and do not carry any current.

In a second phase, the center Z transmits a voltage-modulated by means of the modulator M. Data word as collective command "Initialization" to all detectors M1, M2 ... Mn. The required circuit corresponds to the prior art and will not be described further. The demodulators necessary for the reception in the detectors are not relevant for the address assignment to the detectors and therefore not shown in Fig. 1. After receiving this command, all detectors switch M1, M2 ... Mn their switches SK1, SK2 ... SKn.

In a third phase, the control panel sends with the help of the constant current source K and of the microprocessor μC a data word on the transmission line. The data word consists of a predetermined change of two impressed currents Ik0 and Ikl. The two currents cause the resistor Rm1 of the detector M1 Voltage pulses, which are converted by means of the pulse receiver PE into digital signals become. The logic unit L passes the interpreted as a communication address Data word to the non-volatile address memory SP on. The detector M2 and all subsequent detectors receive no evaluable voltage pulses about their resistances Rm2 ... Rmn and thus no communication address, since the Switch SK1 the transmission line to the subsequent detectors M2 ... Mn short-circuits.

After the detector M1 has stored its address in SP, SK1 is opened. This can be done, for example, by immediately after sending the address from the central Z and storage in the detector M1, the central office current-modulating logic signal sends what the logic L in the detector M1 for opening his switch SK1 causes. In this way takes place at the output of Central Z a voltage jump instead of, as an acknowledgment for a given address assignment is evaluated to the detector M1. The measurement of the voltage jump takes place at the current measuring device VM, which is connected to the microprocessor μC is.

Subsequently, the central Z sends another address, which also by a impressed current-modulated serial signal from the constant currents Ik0 and Ik1 is formed. Since switch SK1 is open, the second detector M2 also receives voltage pulses which can be evaluated via its measuring resistor Rm2 and that from the pulse receiver PE are evaluated. The logic circuit of the first detector M1 ignores this address signal because its address memory is already occupied. The addressing process then continue, as already described for M1. For every detector the center repeats this step. This is achieved by a speedy broadcast the communication addresses a large number of detectors within a short time an address provided. Once the assignment of addresses has been completed, this can be done be determined by the head office that a surge in its Connections of the voltage measuring device VM is no longer registered.

FIG. 2 shows a detector with regard to its addressing circuit, which partly the same components as the detectors M1 and M2 of FIG. 1. As can be seen, a logic circuit L is shown instead of the pulse receiver PE with integrated A / D converter. These are "components" a commonly installed in the detector microprocessor whose A / D converter and its program with the voltage drop across the measuring resistor Rm with compares given digital values. The resulting data word becomes interpreted as an address and stored in the address memory SP, if this empty is. The remaining process steps are identical to those already described.

Claims (9)

1. A process for automatically assigning detector addresses in a danger detection system, comprising a master station and at least one two-wire detection line linked thereto to which a multiplicity of detectors are connected wherein each detector has a capacitor for power accumulation, a measuring resistor in- one wire, an evaluation device evaluating the voltage drop on the measuring resistor to which an address latch is connected, and a switch controllable by the evaluation device between the wires, including the following process steps:

   In a first phase, a voltage is applied to the line from the master station and the capacitors are charged,

   in a second phase, the master station emits a switch signal to close the switches of all detectors on the detection line,

   in a third phase, two constant currents having different levels are impressed on the detection line at a predetermined alternation and are transformed by means of a pulse receiver in the detector into a digital signal constituting a data word which is stored in the address latch, and a logic circuit blocks another information from being rolled into the address latch and opens the switch, and

   the third phase is repeated with another data word for each detector ready for reception the address latch of which is not occupied.
2. The process according to claim 1 wherein the switch is opened by a current-modulated signal of the master station which is detected in the evaluation device and is used by it for producing a control command for the switch.
3. The process according to claim 1 or 2 wherein one of the two currents continues to flow while or after the switch is opened and the master station determines an acknowledge signal from the voltage jump for the purpose of producing a next serial signal consisting of the constant currents for the succeeding detector.
4. The process according to claim 3 wherein the master station terminates the assignment of addresses if a voltage jump is no longer found to exist.
5. The process according to any one of claims 1 to 4 wherein the switch signal is constituted by a voltage-modulated data word of the master station.
6. A circuitry for automatically assigning detector addresses in a danger detection system, comprising:

   a master station (Z) which has a power supply (NT), a microprocessor (µC), a constant-current source (K), and a current modulator (M),

   a multiplicity of detectors (M1, M2...Mn) which are connected to at least one two-wire detection line (A, B) wherein

   each detector (M1, M2...Mn) has a capacitor (C1, C2...Cn) connected between the wires (A, B) in series with a diode (D1, D2...Dn), a controllable switch (SK1, SK2...SKn) between the wires (A, B), a measuring resistor (Rm1, Rm2...Rmn), a pulse receiver (PE) connected parallel to the measuring resistor, a logic circuit (L), and an address latch (SP) connected to the logic circuit (L), and wherein

   the logic circuit (L) is designed so as to close the switch (SK1, SK2...SKn) during a first pulse sequence arriving from the pulse receiver (PE), and inputs it into the address latch (SP) if this one is not occupied yet by an address, during a second pulse sequence arriving from the pulse receiver (PE).
7. The circuitry according to claim 6, characterized in that a semiconductor switch, preferably a FET, is provided as a switch and the ratio of resistance from the measuring resistor (Rm1, Rm2...Rmn) to the resistance value of the switched-through semiconductor switch is more than 10 : 1.
8. The circuitry according to claim 6 or 7, characterized in that the detector (M) includes a microprocessor and the pulse receiver is constituted by the A/D converter and the program of the microprocessor.
9. The circuitry according to any one of claims 6 to 8, characterized in that the master station (Z) has a voltage measuring device (VM) connected to the wires (A, B).

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