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DE69719711D1 - Verfahren zur Herstellung eines Bipolartransistors mit dielektrischer Isolation - Google Patents

Verfahren zur Herstellung eines Bipolartransistors mit dielektrischer Isolation

Info

Publication number
DE69719711D1
DE69719711D1 DE69719711T DE69719711T DE69719711D1 DE 69719711 D1 DE69719711 D1 DE 69719711D1 DE 69719711 T DE69719711 T DE 69719711T DE 69719711 T DE69719711 T DE 69719711T DE 69719711 D1 DE69719711 D1 DE 69719711D1
Authority
DE
Germany
Prior art keywords
manufacturing
bipolar transistor
dielectric isolation
isolation bipolar
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69719711T
Other languages
English (en)
Inventor
Yvon Gris
Jocelyne Mourier
Germaine Troillard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69719711D1 publication Critical patent/DE69719711D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE69719711T 1996-12-27 1997-12-24 Verfahren zur Herstellung eines Bipolartransistors mit dielektrischer Isolation Expired - Lifetime DE69719711D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9616337A FR2758004B1 (fr) 1996-12-27 1996-12-27 Transistor bipolaire a isolement dielectrique

Publications (1)

Publication Number Publication Date
DE69719711D1 true DE69719711D1 (de) 2003-04-17

Family

ID=9499405

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69719711T Expired - Lifetime DE69719711D1 (de) 1996-12-27 1997-12-24 Verfahren zur Herstellung eines Bipolartransistors mit dielektrischer Isolation

Country Status (7)

Country Link
US (1) US5970333A (de)
EP (1) EP0851488B1 (de)
JP (1) JP2970637B2 (de)
KR (1) KR19980064721A (de)
DE (1) DE69719711D1 (de)
FR (1) FR2758004B1 (de)
TW (1) TW405208B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2756100B1 (fr) 1996-11-19 1999-02-12 Sgs Thomson Microelectronics Transistor bipolaire a emetteur inhomogene dans un circuit integre bicmos
FR2756103B1 (fr) * 1996-11-19 1999-05-14 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos et d'un condensateur
JP3003632B2 (ja) * 1997-06-27 2000-01-31 日本電気株式会社 半導体集積回路およびその製造方法
JP3070674B2 (ja) * 1997-11-06 2000-07-31 日本電気株式会社 半導体装置の製造方法
US6080612A (en) * 1998-05-20 2000-06-27 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI electrostatic discharge protection device
JP3532770B2 (ja) * 1998-07-08 2004-05-31 松下電器産業株式会社 半導体装置及びその製造方法
KR20000023299A (ko) * 1998-09-22 2000-04-25 다니엘 이. 박서 게이트 산화물 및 비정질 실리콘 전극을 원 위치에데포지트하는 방법 및 그에 해당하는 구조
FR2790867B1 (fr) * 1999-03-12 2001-11-16 St Microelectronics Sa Procede de fabrication de transistor bipolaire
US6261932B1 (en) * 1999-07-29 2001-07-17 Fairchild Semiconductor Corp. Method of fabricating Schottky diode and related structure
US6600199B2 (en) 2000-12-29 2003-07-29 International Business Machines Corporation Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity
SE0103036D0 (sv) * 2001-05-04 2001-09-13 Ericsson Telefon Ab L M Semiconductor process and integrated circuit
US6511873B2 (en) * 2001-06-15 2003-01-28 International Business Machines Corporation High-dielectric constant insulators for FEOL capacitors
KR100741682B1 (ko) 2004-12-03 2007-07-23 한국전자통신연구원 실리콘 게르마늄 바이시모스 소자의 제조 방법
US20100047987A1 (en) * 2005-04-28 2010-02-25 Nxp B.V. Method of fabricating a bipolar transistor
CN103137564B (zh) * 2011-11-22 2015-02-04 上海华虹宏力半导体制造有限公司 一种实现BiCMOS器件中扩展基区结构的方法
KR102209097B1 (ko) 2014-02-27 2021-01-28 삼성전자주식회사 이미지 센서 및 이의 제조 방법
KR102366416B1 (ko) 2014-08-11 2022-02-23 삼성전자주식회사 Cmos 이미지 센서
KR102466904B1 (ko) 2016-01-12 2022-11-15 삼성전자주식회사 씨모스 이미지 센서

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
KR0140715B1 (ko) * 1987-12-07 1998-07-15 엔. 라이스 머레트 반도체 집적회로 구조물 및 그 제조방법
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US5089429A (en) * 1989-06-22 1992-02-18 David Sarnoff Research Center, Inc. Self-aligned emitter bicmos process
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
JP2625602B2 (ja) * 1991-01-18 1997-07-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 集積回路デバイスの製造プロセス
JP3273681B2 (ja) * 1993-12-16 2002-04-08 三菱電機株式会社 半導体装置の製造方法
KR0158065B1 (ko) * 1995-05-29 1998-12-01 스기야마 가즈히코 반도체 집적회로장치 및 그 제조방법
US5547893A (en) * 1995-12-27 1996-08-20 Vanguard International Semiconductor Corp. method for fabricating an embedded vertical bipolar transistor and a memory cell

Also Published As

Publication number Publication date
EP0851488A1 (de) 1998-07-01
EP0851488B1 (de) 2003-03-12
JPH10200004A (ja) 1998-07-31
KR19980064721A (ko) 1998-10-07
US5970333A (en) 1999-10-19
FR2758004A1 (fr) 1998-07-03
JP2970637B2 (ja) 1999-11-02
FR2758004B1 (fr) 1999-03-05
TW405208B (en) 2000-09-11

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Legal Events

Date Code Title Description
8332 No legal effect for de